1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/hwmon.h> 8 #include <linux/jiffies.h> 9 #include <linux/types.h> 10 #include <linux/units.h> 11 12 #include <drm/drm_managed.h> 13 #include "regs/xe_gt_regs.h" 14 #include "regs/xe_mchbar_regs.h" 15 #include "regs/xe_pcode_regs.h" 16 #include "xe_device.h" 17 #include "xe_hwmon.h" 18 #include "xe_mmio.h" 19 #include "xe_pcode.h" 20 #include "xe_pcode_api.h" 21 #include "xe_sriov.h" 22 #include "xe_pm.h" 23 #include "xe_vsec.h" 24 #include "regs/xe_pmt.h" 25 26 enum xe_hwmon_reg { 27 REG_TEMP, 28 REG_PKG_RAPL_LIMIT, 29 REG_PKG_POWER_SKU, 30 REG_PKG_POWER_SKU_UNIT, 31 REG_GT_PERF_STATUS, 32 REG_PKG_ENERGY_STATUS, 33 REG_FAN_SPEED, 34 }; 35 36 enum xe_hwmon_reg_operation { 37 REG_READ32, 38 REG_RMW32, 39 REG_READ64, 40 }; 41 42 enum xe_hwmon_channel { 43 CHANNEL_CARD, 44 CHANNEL_PKG, 45 CHANNEL_VRAM, 46 CHANNEL_MAX, 47 }; 48 49 enum xe_fan_channel { 50 FAN_1, 51 FAN_2, 52 FAN_3, 53 FAN_MAX, 54 }; 55 56 /* Attribute index for powerX_xxx_interval sysfs entries */ 57 enum sensor_attr_power { 58 SENSOR_INDEX_PSYS_PL1, 59 SENSOR_INDEX_PKG_PL1, 60 SENSOR_INDEX_PSYS_PL2, 61 SENSOR_INDEX_PKG_PL2, 62 }; 63 64 /* 65 * For platforms that support mailbox commands for power limits, REG_PKG_POWER_SKU_UNIT is 66 * not supported and below are SKU units to be used. 67 */ 68 #define PWR_UNIT 0x3 69 #define ENERGY_UNIT 0xe 70 #define TIME_UNIT 0xa 71 72 /* 73 * SF_* - scale factors for particular quantities according to hwmon spec. 74 */ 75 #define SF_POWER 1000000 /* microwatts */ 76 #define SF_CURR 1000 /* milliamperes */ 77 #define SF_VOLTAGE 1000 /* millivolts */ 78 #define SF_ENERGY 1000000 /* microjoules */ 79 #define SF_TIME 1000 /* milliseconds */ 80 81 /* 82 * PL*_HWMON_ATTR - mapping of hardware power limits to corresponding hwmon power attribute. 83 */ 84 #define PL1_HWMON_ATTR hwmon_power_max 85 #define PL2_HWMON_ATTR hwmon_power_cap 86 87 #define PWR_ATTR_TO_STR(attr) (((attr) == hwmon_power_max) ? "PL1" : "PL2") 88 89 /* 90 * Timeout for power limit write mailbox command. 91 */ 92 #define PL_WRITE_MBX_TIMEOUT_MS (1) 93 94 /** 95 * struct xe_hwmon_energy_info - to accumulate energy 96 */ 97 struct xe_hwmon_energy_info { 98 /** @reg_val_prev: previous energy reg val */ 99 u32 reg_val_prev; 100 /** @accum_energy: accumulated energy */ 101 long accum_energy; 102 }; 103 104 /** 105 * struct xe_hwmon_fan_info - to cache previous fan reading 106 */ 107 struct xe_hwmon_fan_info { 108 /** @reg_val_prev: previous fan reg val */ 109 u32 reg_val_prev; 110 /** @time_prev: previous timestamp */ 111 u64 time_prev; 112 }; 113 114 /** 115 * struct xe_hwmon - xe hwmon data structure 116 */ 117 struct xe_hwmon { 118 /** @hwmon_dev: hwmon device for xe */ 119 struct device *hwmon_dev; 120 /** @xe: Xe device */ 121 struct xe_device *xe; 122 /** @hwmon_lock: lock for rw attributes*/ 123 struct mutex hwmon_lock; 124 /** @scl_shift_power: pkg power unit */ 125 int scl_shift_power; 126 /** @scl_shift_energy: pkg energy unit */ 127 int scl_shift_energy; 128 /** @scl_shift_time: pkg time unit */ 129 int scl_shift_time; 130 /** @ei: Energy info for energyN_input */ 131 struct xe_hwmon_energy_info ei[CHANNEL_MAX]; 132 /** @fi: Fan info for fanN_input */ 133 struct xe_hwmon_fan_info fi[FAN_MAX]; 134 /** @boot_power_limit_read: is boot power limits read */ 135 bool boot_power_limit_read; 136 /** @pl1_on_boot: power limit PL1 on boot */ 137 u32 pl1_on_boot[CHANNEL_MAX]; 138 /** @pl2_on_boot: power limit PL2 on boot */ 139 u32 pl2_on_boot[CHANNEL_MAX]; 140 141 }; 142 143 static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel, 144 u32 *uval) 145 { 146 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 147 u32 val0 = 0, val1 = 0; 148 int ret = 0; 149 150 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 151 (channel == CHANNEL_CARD) ? 152 READ_PSYSGPU_POWER_LIMIT : 153 READ_PACKAGE_POWER_LIMIT, 154 hwmon->boot_power_limit_read ? 155 READ_PL_FROM_PCODE : READ_PL_FROM_FW), 156 &val0, &val1); 157 158 if (ret) { 159 drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 160 channel, val0, val1, ret); 161 *uval = 0; 162 return ret; 163 } 164 165 /* return the value only if limit is enabled */ 166 if (attr == PL1_HWMON_ATTR) 167 *uval = (val0 & PWR_LIM_EN) ? val0 : 0; 168 else if (attr == PL2_HWMON_ATTR) 169 *uval = (val1 & PWR_LIM_EN) ? val1 : 0; 170 else if (attr == hwmon_power_label) 171 *uval = (val0 & PWR_LIM_EN) ? 1 : (val1 & PWR_LIM_EN) ? 1 : 0; 172 else 173 *uval = 0; 174 175 return ret; 176 } 177 178 static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr, u8 channel, 179 u32 clr, u32 set) 180 { 181 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 182 u32 val0, val1; 183 int ret = 0; 184 185 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 186 (channel == CHANNEL_CARD) ? 187 READ_PSYSGPU_POWER_LIMIT : 188 READ_PACKAGE_POWER_LIMIT, 189 hwmon->boot_power_limit_read ? 190 READ_PL_FROM_PCODE : READ_PL_FROM_FW), 191 &val0, &val1); 192 193 if (ret) 194 drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 195 channel, val0, val1, ret); 196 197 if (attr == PL1_HWMON_ATTR) 198 val0 = (val0 & ~clr) | set; 199 else if (attr == PL2_HWMON_ATTR) 200 val1 = (val1 & ~clr) | set; 201 else 202 return -EIO; 203 204 ret = xe_pcode_write64_timeout(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 205 (channel == CHANNEL_CARD) ? 206 WRITE_PSYSGPU_POWER_LIMIT : 207 WRITE_PACKAGE_POWER_LIMIT, 0), 208 val0, val1, PL_WRITE_MBX_TIMEOUT_MS); 209 if (ret) 210 drm_dbg(&hwmon->xe->drm, "write failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 211 channel, val0, val1, ret); 212 return ret; 213 } 214 215 static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, 216 int channel) 217 { 218 struct xe_device *xe = hwmon->xe; 219 220 switch (hwmon_reg) { 221 case REG_TEMP: 222 if (xe->info.platform == XE_BATTLEMAGE) { 223 if (channel == CHANNEL_PKG) 224 return BMG_PACKAGE_TEMPERATURE; 225 else if (channel == CHANNEL_VRAM) 226 return BMG_VRAM_TEMPERATURE; 227 } else if (xe->info.platform == XE_DG2) { 228 if (channel == CHANNEL_PKG) 229 return PCU_CR_PACKAGE_TEMPERATURE; 230 else if (channel == CHANNEL_VRAM) 231 return BMG_VRAM_TEMPERATURE; 232 } 233 break; 234 case REG_PKG_RAPL_LIMIT: 235 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) 236 return PVC_GT0_PACKAGE_RAPL_LIMIT; 237 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) 238 return PCU_CR_PACKAGE_RAPL_LIMIT; 239 break; 240 case REG_PKG_POWER_SKU: 241 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) 242 return PVC_GT0_PACKAGE_POWER_SKU; 243 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) 244 return PCU_CR_PACKAGE_POWER_SKU; 245 break; 246 case REG_PKG_POWER_SKU_UNIT: 247 if (xe->info.platform == XE_PVC) 248 return PVC_GT0_PACKAGE_POWER_SKU_UNIT; 249 else if (xe->info.platform == XE_DG2) 250 return PCU_CR_PACKAGE_POWER_SKU_UNIT; 251 break; 252 case REG_GT_PERF_STATUS: 253 if (xe->info.platform == XE_DG2 && channel == CHANNEL_PKG) 254 return GT_PERF_STATUS; 255 break; 256 case REG_PKG_ENERGY_STATUS: 257 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { 258 return PVC_GT0_PLATFORM_ENERGY_STATUS; 259 } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) { 260 return PCU_CR_PACKAGE_ENERGY_STATUS; 261 } 262 break; 263 case REG_FAN_SPEED: 264 if (channel == FAN_1) 265 return BMG_FAN_1_SPEED; 266 else if (channel == FAN_2) 267 return BMG_FAN_2_SPEED; 268 else if (channel == FAN_3) 269 return BMG_FAN_3_SPEED; 270 break; 271 default: 272 drm_warn(&xe->drm, "Unknown xe hwmon reg id: %d\n", hwmon_reg); 273 break; 274 } 275 276 return XE_REG(0); 277 } 278 279 #define PL_DISABLE 0 280 281 /* 282 * HW allows arbitrary PL1 limits to be set but silently clamps these values to 283 * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the 284 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display 285 * clamped values when read. 286 */ 287 static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *value) 288 { 289 u64 reg_val = 0, min, max; 290 struct xe_device *xe = hwmon->xe; 291 struct xe_reg rapl_limit, pkg_power_sku; 292 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 293 294 mutex_lock(&hwmon->hwmon_lock); 295 296 if (hwmon->xe->info.has_mbx_power_limits) { 297 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, (u32 *)®_val); 298 } else { 299 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 300 pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 301 reg_val = xe_mmio_read32(mmio, rapl_limit); 302 } 303 304 /* Check if PL limits are disabled. */ 305 if (!(reg_val & PWR_LIM_EN)) { 306 *value = PL_DISABLE; 307 drm_info(&hwmon->xe->drm, "%s disabled for channel %d, val 0x%016llx\n", 308 PWR_ATTR_TO_STR(attr), channel, reg_val); 309 goto unlock; 310 } 311 312 reg_val = REG_FIELD_GET(PWR_LIM_VAL, reg_val); 313 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power); 314 315 /* For platforms with mailbox power limit support clamping would be done by pcode. */ 316 if (!hwmon->xe->info.has_mbx_power_limits) { 317 reg_val = xe_mmio_read64_2x32(mmio, pkg_power_sku); 318 min = REG_FIELD_GET(PKG_MIN_PWR, reg_val); 319 max = REG_FIELD_GET(PKG_MAX_PWR, reg_val); 320 min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power); 321 max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power); 322 if (min && max) 323 *value = clamp_t(u64, *value, min, max); 324 } 325 unlock: 326 mutex_unlock(&hwmon->hwmon_lock); 327 } 328 329 static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channel, long value) 330 { 331 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 332 int ret = 0; 333 u32 reg_val, max; 334 struct xe_reg rapl_limit; 335 336 mutex_lock(&hwmon->hwmon_lock); 337 338 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 339 340 /* Disable Power Limit and verify, as limit cannot be disabled on all platforms. */ 341 if (value == PL_DISABLE) { 342 if (hwmon->xe->info.has_mbx_power_limits) { 343 drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n", 344 PWR_ATTR_TO_STR(attr), channel); 345 xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM_EN, 0); 346 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, ®_val); 347 } else { 348 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0); 349 reg_val = xe_mmio_read32(mmio, rapl_limit); 350 } 351 352 if (reg_val & PWR_LIM_EN) { 353 drm_warn(&hwmon->xe->drm, "Power limit disable is not supported!\n"); 354 ret = -EOPNOTSUPP; 355 } 356 goto unlock; 357 } 358 359 /* Computation in 64-bits to avoid overflow. Round to nearest. */ 360 reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER); 361 362 /* 363 * Clamp power limit to GPU firmware default as maximum, as an additional protection to 364 * pcode clamp. 365 */ 366 if (hwmon->xe->info.has_mbx_power_limits) { 367 max = (attr == PL1_HWMON_ATTR) ? 368 hwmon->pl1_on_boot[channel] : hwmon->pl2_on_boot[channel]; 369 max = REG_FIELD_PREP(PWR_LIM_VAL, max); 370 if (reg_val > max) { 371 reg_val = max; 372 drm_dbg(&hwmon->xe->drm, 373 "Clamping power limit to GPU firmware default 0x%x\n", 374 reg_val); 375 } 376 } 377 378 reg_val = PWR_LIM_EN | REG_FIELD_PREP(PWR_LIM_VAL, reg_val); 379 380 if (hwmon->xe->info.has_mbx_power_limits) 381 ret = xe_hwmon_pcode_rmw_power_limit(hwmon, attr, channel, PWR_LIM, reg_val); 382 else 383 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM, reg_val); 384 unlock: 385 mutex_unlock(&hwmon->hwmon_lock); 386 return ret; 387 } 388 389 static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, u32 attr, int channel, 390 long *value) 391 { 392 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 393 u32 reg_val; 394 395 if (hwmon->xe->info.has_mbx_power_limits) { 396 /* PL1 is rated max if supported. */ 397 xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, channel, ®_val); 398 } else { 399 /* 400 * This sysfs file won't be visible if REG_PKG_POWER_SKU is invalid, so valid check 401 * for this register can be skipped. 402 * See xe_hwmon_power_is_visible. 403 */ 404 struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 405 406 reg_val = xe_mmio_read32(mmio, reg); 407 } 408 409 reg_val = REG_FIELD_GET(PKG_TDP, reg_val); 410 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power); 411 } 412 413 /* 414 * xe_hwmon_energy_get - Obtain energy value 415 * 416 * The underlying energy hardware register is 32-bits and is subject to 417 * overflow. How long before overflow? For example, with an example 418 * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and 419 * a power draw of 1000 watts, the 32-bit counter will overflow in 420 * approximately 4.36 minutes. 421 * 422 * Examples: 423 * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days 424 * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes 425 * 426 * The function significantly increases overflow duration (from 4.36 427 * minutes) by accumulating the energy register into a 'long' as allowed by 428 * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()), 429 * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and 430 * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before 431 * energyN_input overflows. This at 1000 W is an overflow duration of 278 years. 432 */ 433 static void 434 xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy) 435 { 436 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 437 struct xe_hwmon_energy_info *ei = &hwmon->ei[channel]; 438 u32 reg_val; 439 int ret = 0; 440 441 /* Energy is supported only for card and pkg */ 442 if (channel > CHANNEL_PKG) { 443 *energy = 0; 444 return; 445 } 446 447 if (hwmon->xe->info.platform == XE_BATTLEMAGE) { 448 u64 pmt_val; 449 450 ret = xe_pmt_telem_read(to_pci_dev(hwmon->xe->drm.dev), 451 xe_mmio_read32(mmio, PUNIT_TELEMETRY_GUID), 452 &pmt_val, BMG_ENERGY_STATUS_PMT_OFFSET, sizeof(pmt_val)); 453 if (ret != sizeof(pmt_val)) { 454 drm_warn(&hwmon->xe->drm, "energy read from pmt failed, ret %d\n", ret); 455 *energy = 0; 456 return; 457 } 458 459 if (channel == CHANNEL_PKG) 460 reg_val = REG_FIELD_GET64(ENERGY_PKG, pmt_val); 461 else 462 reg_val = REG_FIELD_GET64(ENERGY_CARD, pmt_val); 463 } else { 464 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, 465 channel)); 466 } 467 468 ei->accum_energy += reg_val - ei->reg_val_prev; 469 ei->reg_val_prev = reg_val; 470 471 *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY, 472 hwmon->scl_shift_energy); 473 } 474 475 static ssize_t 476 xe_hwmon_power_max_interval_show(struct device *dev, struct device_attribute *attr, 477 char *buf) 478 { 479 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 480 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 481 u32 x, y, x_w = 2; /* 2 bits */ 482 u64 r, tau4, out; 483 int channel = (to_sensor_dev_attr(attr)->index % 2) ? CHANNEL_PKG : CHANNEL_CARD; 484 u32 power_attr = (to_sensor_dev_attr(attr)->index > 1) ? PL2_HWMON_ATTR : PL1_HWMON_ATTR; 485 486 int ret = 0; 487 488 xe_pm_runtime_get(hwmon->xe); 489 490 mutex_lock(&hwmon->hwmon_lock); 491 492 if (hwmon->xe->info.has_mbx_power_limits) { 493 ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, (u32 *)&r); 494 if (ret) { 495 drm_err(&hwmon->xe->drm, 496 "power interval read fail, ch %d, attr %d, r 0%llx, ret %d\n", 497 channel, power_attr, r, ret); 498 r = 0; 499 } 500 } else { 501 r = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel)); 502 } 503 504 mutex_unlock(&hwmon->hwmon_lock); 505 506 xe_pm_runtime_put(hwmon->xe); 507 508 x = REG_FIELD_GET(PWR_LIM_TIME_X, r); 509 y = REG_FIELD_GET(PWR_LIM_TIME_Y, r); 510 511 /* 512 * tau = (1 + (x / 4)) * power(2,y), x = bits(23:22), y = bits(21:17) 513 * = (4 | x) << (y - 2) 514 * 515 * Here (y - 2) ensures a 1.x fixed point representation of 1.x 516 * As x is 2 bits so 1.x can be 1.0, 1.25, 1.50, 1.75 517 * 518 * As y can be < 2, we compute tau4 = (4 | x) << y 519 * and then add 2 when doing the final right shift to account for units 520 */ 521 tau4 = (u64)((1 << x_w) | x) << y; 522 523 /* val in hwmon interface units (millisec) */ 524 out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 525 526 return sysfs_emit(buf, "%llu\n", out); 527 } 528 529 static ssize_t 530 xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *attr, 531 const char *buf, size_t count) 532 { 533 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 534 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 535 u32 x, y, rxy, x_w = 2; /* 2 bits */ 536 u64 tau4, r, max_win; 537 unsigned long val; 538 int channel = (to_sensor_dev_attr(attr)->index % 2) ? CHANNEL_PKG : CHANNEL_CARD; 539 u32 power_attr = (to_sensor_dev_attr(attr)->index > 1) ? PL2_HWMON_ATTR : PL1_HWMON_ATTR; 540 int ret; 541 542 ret = kstrtoul(buf, 0, &val); 543 if (ret) 544 return ret; 545 546 /* 547 * Max HW supported tau in '(1 + (x / 4)) * power(2,y)' format, x = 0, y = 0x12. 548 * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds. 549 * 550 * The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register. 551 * However, it is observed that existing discrete GPUs does not provide correct 552 * PKG_MAX_WIN value, therefore a using default constant value. For future discrete GPUs 553 * this may get resolved, in which case PKG_MAX_WIN should be obtained from PKG_PWR_SKU. 554 */ 555 #define PKG_MAX_WIN_DEFAULT 0x12ull 556 557 /* 558 * val must be < max in hwmon interface units. The steps below are 559 * explained in xe_hwmon_power_max_interval_show() 560 */ 561 r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT); 562 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); 563 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); 564 tau4 = (u64)((1 << x_w) | x) << y; 565 max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 566 567 if (val > max_win) 568 return -EINVAL; 569 570 /* val in hw units */ 571 val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME) + 1; 572 573 /* 574 * Convert val to 1.x * power(2,y) 575 * y = ilog2(val) 576 * x = (val - (1 << y)) >> (y - 2) 577 */ 578 if (!val) { 579 y = 0; 580 x = 0; 581 } else { 582 y = ilog2(val); 583 x = (val - (1ul << y)) << x_w >> y; 584 } 585 586 rxy = REG_FIELD_PREP(PWR_LIM_TIME_X, x) | 587 REG_FIELD_PREP(PWR_LIM_TIME_Y, y); 588 589 xe_pm_runtime_get(hwmon->xe); 590 591 mutex_lock(&hwmon->hwmon_lock); 592 593 if (hwmon->xe->info.has_mbx_power_limits) 594 xe_hwmon_pcode_rmw_power_limit(hwmon, power_attr, channel, PWR_LIM_TIME, rxy); 595 else 596 r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel), 597 PWR_LIM_TIME, rxy); 598 599 mutex_unlock(&hwmon->hwmon_lock); 600 601 xe_pm_runtime_put(hwmon->xe); 602 603 return count; 604 } 605 606 /* PSYS PL1 */ 607 static SENSOR_DEVICE_ATTR(power1_max_interval, 0664, 608 xe_hwmon_power_max_interval_show, 609 xe_hwmon_power_max_interval_store, SENSOR_INDEX_PSYS_PL1); 610 /* PKG PL1 */ 611 static SENSOR_DEVICE_ATTR(power2_max_interval, 0664, 612 xe_hwmon_power_max_interval_show, 613 xe_hwmon_power_max_interval_store, SENSOR_INDEX_PKG_PL1); 614 /* PSYS PL2 */ 615 static SENSOR_DEVICE_ATTR(power1_cap_interval, 0664, 616 xe_hwmon_power_max_interval_show, 617 xe_hwmon_power_max_interval_store, SENSOR_INDEX_PSYS_PL2); 618 /* PKG PL2 */ 619 static SENSOR_DEVICE_ATTR(power2_cap_interval, 0664, 620 xe_hwmon_power_max_interval_show, 621 xe_hwmon_power_max_interval_store, SENSOR_INDEX_PKG_PL2); 622 623 static struct attribute *hwmon_attributes[] = { 624 &sensor_dev_attr_power1_max_interval.dev_attr.attr, 625 &sensor_dev_attr_power2_max_interval.dev_attr.attr, 626 &sensor_dev_attr_power1_cap_interval.dev_attr.attr, 627 &sensor_dev_attr_power2_cap_interval.dev_attr.attr, 628 NULL 629 }; 630 631 static umode_t xe_hwmon_attributes_visible(struct kobject *kobj, 632 struct attribute *attr, int index) 633 { 634 struct device *dev = kobj_to_dev(kobj); 635 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 636 int ret = 0; 637 int channel = (index % 2) ? CHANNEL_PKG : CHANNEL_CARD; 638 u32 power_attr = (index > 1) ? PL2_HWMON_ATTR : PL1_HWMON_ATTR; 639 u32 uval = 0; 640 struct xe_reg rapl_limit; 641 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 642 643 xe_pm_runtime_get(hwmon->xe); 644 645 if (hwmon->xe->info.has_mbx_power_limits) { 646 xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, &uval); 647 } else if (power_attr != PL2_HWMON_ATTR) { 648 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 649 if (xe_reg_is_valid(rapl_limit)) 650 uval = xe_mmio_read32(mmio, rapl_limit); 651 } 652 ret = (uval & PWR_LIM_EN) ? attr->mode : 0; 653 654 xe_pm_runtime_put(hwmon->xe); 655 656 return ret; 657 } 658 659 static const struct attribute_group hwmon_attrgroup = { 660 .attrs = hwmon_attributes, 661 .is_visible = xe_hwmon_attributes_visible, 662 }; 663 664 static const struct attribute_group *hwmon_groups[] = { 665 &hwmon_attrgroup, 666 NULL 667 }; 668 669 static const struct hwmon_channel_info * const hwmon_info[] = { 670 HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL, 671 HWMON_T_INPUT | HWMON_T_LABEL), 672 HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT | 673 HWMON_P_CAP, 674 HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CAP), 675 HWMON_CHANNEL_INFO(curr, HWMON_C_LABEL, HWMON_C_CRIT | HWMON_C_LABEL), 676 HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL), 677 HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT | HWMON_E_LABEL, HWMON_E_INPUT | HWMON_E_LABEL), 678 HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT, HWMON_F_INPUT, HWMON_F_INPUT), 679 NULL 680 }; 681 682 /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */ 683 static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval) 684 { 685 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 686 687 /* Avoid Illegal Subcommand error */ 688 if (hwmon->xe->info.platform == XE_DG2) 689 return -ENXIO; 690 691 return xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 692 POWER_SETUP_SUBCOMMAND_READ_I1, 0), 693 uval, NULL); 694 } 695 696 static int xe_hwmon_pcode_write_i1(const struct xe_hwmon *hwmon, u32 uval) 697 { 698 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 699 700 return xe_pcode_write(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 701 POWER_SETUP_SUBCOMMAND_WRITE_I1, 0), 702 (uval & POWER_SETUP_I1_DATA_MASK)); 703 } 704 705 static int xe_hwmon_pcode_read_fan_control(const struct xe_hwmon *hwmon, u32 subcmd, u32 *uval) 706 { 707 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 708 709 /* Platforms that don't return correct value */ 710 if (hwmon->xe->info.platform == XE_DG2 && subcmd == FSC_READ_NUM_FANS) { 711 *uval = 2; 712 return 0; 713 } 714 715 return xe_pcode_read(root_tile, PCODE_MBOX(FAN_SPEED_CONTROL, subcmd, 0), uval, NULL); 716 } 717 718 static int xe_hwmon_power_curr_crit_read(struct xe_hwmon *hwmon, int channel, 719 long *value, u32 scale_factor) 720 { 721 int ret; 722 u32 uval; 723 724 mutex_lock(&hwmon->hwmon_lock); 725 726 ret = xe_hwmon_pcode_read_i1(hwmon, &uval); 727 if (ret) 728 goto unlock; 729 730 *value = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), 731 scale_factor, POWER_SETUP_I1_SHIFT); 732 unlock: 733 mutex_unlock(&hwmon->hwmon_lock); 734 return ret; 735 } 736 737 static int xe_hwmon_power_curr_crit_write(struct xe_hwmon *hwmon, int channel, 738 long value, u32 scale_factor) 739 { 740 int ret; 741 u32 uval; 742 743 mutex_lock(&hwmon->hwmon_lock); 744 745 uval = DIV_ROUND_CLOSEST_ULL(value << POWER_SETUP_I1_SHIFT, scale_factor); 746 ret = xe_hwmon_pcode_write_i1(hwmon, uval); 747 748 mutex_unlock(&hwmon->hwmon_lock); 749 return ret; 750 } 751 752 static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *value) 753 { 754 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 755 u64 reg_val; 756 757 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, channel)); 758 /* HW register value in units of 2.5 millivolt */ 759 *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE); 760 } 761 762 static umode_t 763 xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 764 { 765 switch (attr) { 766 case hwmon_temp_input: 767 case hwmon_temp_label: 768 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0; 769 default: 770 return 0; 771 } 772 } 773 774 static int 775 xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 776 { 777 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 778 u64 reg_val; 779 780 switch (attr) { 781 case hwmon_temp_input: 782 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel)); 783 784 /* HW register value is in degrees Celsius, convert to millidegrees. */ 785 *val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE; 786 return 0; 787 default: 788 return -EOPNOTSUPP; 789 } 790 } 791 792 static umode_t 793 xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 794 { 795 u32 uval = 0; 796 struct xe_reg reg; 797 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 798 799 switch (attr) { 800 case hwmon_power_max: 801 case hwmon_power_cap: 802 if (hwmon->xe->info.has_mbx_power_limits) { 803 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &uval); 804 } else if (attr != PL2_HWMON_ATTR) { 805 reg = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 806 if (xe_reg_is_valid(reg)) 807 uval = xe_mmio_read32(mmio, reg); 808 } 809 if (uval & PWR_LIM_EN) { 810 drm_info(&hwmon->xe->drm, "%s is supported on channel %d\n", 811 PWR_ATTR_TO_STR(attr), channel); 812 return 0664; 813 } 814 drm_dbg(&hwmon->xe->drm, "%s is unsupported on channel %d\n", 815 PWR_ATTR_TO_STR(attr), channel); 816 return 0; 817 case hwmon_power_rated_max: 818 if (hwmon->xe->info.has_mbx_power_limits) { 819 return 0; 820 } else { 821 reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 822 if (xe_reg_is_valid(reg)) 823 uval = xe_mmio_read32(mmio, reg); 824 return uval ? 0444 : 0; 825 } 826 case hwmon_power_crit: 827 if (channel == CHANNEL_CARD) { 828 xe_hwmon_pcode_read_i1(hwmon, &uval); 829 return (uval & POWER_SETUP_I1_WATTS) ? 0644 : 0; 830 } 831 break; 832 case hwmon_power_label: 833 if (hwmon->xe->info.has_mbx_power_limits) { 834 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &uval); 835 } else { 836 reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 837 if (xe_reg_is_valid(reg)) 838 uval = xe_mmio_read32(mmio, reg); 839 840 if (!uval) { 841 reg = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 842 if (xe_reg_is_valid(reg)) 843 uval = xe_mmio_read32(mmio, reg); 844 } 845 } 846 if ((!(uval & PWR_LIM_EN)) && channel == CHANNEL_CARD) { 847 xe_hwmon_pcode_read_i1(hwmon, &uval); 848 return (uval & POWER_SETUP_I1_WATTS) ? 0444 : 0; 849 } 850 return (uval) ? 0444 : 0; 851 default: 852 return 0; 853 } 854 return 0; 855 } 856 857 static int 858 xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 859 { 860 switch (attr) { 861 case hwmon_power_max: 862 case hwmon_power_cap: 863 xe_hwmon_power_max_read(hwmon, attr, channel, val); 864 return 0; 865 case hwmon_power_rated_max: 866 xe_hwmon_power_rated_max_read(hwmon, attr, channel, val); 867 return 0; 868 case hwmon_power_crit: 869 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_POWER); 870 default: 871 return -EOPNOTSUPP; 872 } 873 } 874 875 static int 876 xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 877 { 878 switch (attr) { 879 case hwmon_power_cap: 880 case hwmon_power_max: 881 return xe_hwmon_power_max_write(hwmon, attr, channel, val); 882 case hwmon_power_crit: 883 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_POWER); 884 default: 885 return -EOPNOTSUPP; 886 } 887 } 888 889 static umode_t 890 xe_hwmon_curr_is_visible(const struct xe_hwmon *hwmon, u32 attr, int channel) 891 { 892 u32 uval; 893 894 /* hwmon sysfs attribute of current available only for package */ 895 if (channel != CHANNEL_PKG) 896 return 0; 897 898 switch (attr) { 899 case hwmon_curr_crit: 900 return (xe_hwmon_pcode_read_i1(hwmon, &uval) || 901 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644; 902 case hwmon_curr_label: 903 return (xe_hwmon_pcode_read_i1(hwmon, &uval) || 904 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0444; 905 break; 906 default: 907 return 0; 908 } 909 return 0; 910 } 911 912 static int 913 xe_hwmon_curr_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 914 { 915 switch (attr) { 916 case hwmon_curr_crit: 917 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_CURR); 918 default: 919 return -EOPNOTSUPP; 920 } 921 } 922 923 static int 924 xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 925 { 926 switch (attr) { 927 case hwmon_curr_crit: 928 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_CURR); 929 default: 930 return -EOPNOTSUPP; 931 } 932 } 933 934 static umode_t 935 xe_hwmon_in_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 936 { 937 switch (attr) { 938 case hwmon_in_input: 939 case hwmon_in_label: 940 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, 941 channel)) ? 0444 : 0; 942 default: 943 return 0; 944 } 945 } 946 947 static int 948 xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 949 { 950 switch (attr) { 951 case hwmon_in_input: 952 xe_hwmon_get_voltage(hwmon, channel, val); 953 return 0; 954 default: 955 return -EOPNOTSUPP; 956 } 957 } 958 959 static umode_t 960 xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 961 { 962 long energy = 0; 963 964 switch (attr) { 965 case hwmon_energy_input: 966 case hwmon_energy_label: 967 if (hwmon->xe->info.platform == XE_BATTLEMAGE) { 968 xe_hwmon_energy_get(hwmon, channel, &energy); 969 return energy ? 0444 : 0; 970 } else { 971 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, 972 channel)) ? 0444 : 0; 973 } 974 default: 975 return 0; 976 } 977 } 978 979 static int 980 xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 981 { 982 switch (attr) { 983 case hwmon_energy_input: 984 xe_hwmon_energy_get(hwmon, channel, val); 985 return 0; 986 default: 987 return -EOPNOTSUPP; 988 } 989 } 990 991 static umode_t 992 xe_hwmon_fan_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 993 { 994 u32 uval; 995 996 if (!hwmon->xe->info.has_fan_control) 997 return 0; 998 999 switch (attr) { 1000 case hwmon_fan_input: 1001 if (xe_hwmon_pcode_read_fan_control(hwmon, FSC_READ_NUM_FANS, &uval)) 1002 return 0; 1003 1004 return channel < uval ? 0444 : 0; 1005 default: 1006 return 0; 1007 } 1008 } 1009 1010 static int 1011 xe_hwmon_fan_input_read(struct xe_hwmon *hwmon, int channel, long *val) 1012 { 1013 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 1014 struct xe_hwmon_fan_info *fi = &hwmon->fi[channel]; 1015 u64 rotations, time_now, time; 1016 u32 reg_val; 1017 int ret = 0; 1018 1019 mutex_lock(&hwmon->hwmon_lock); 1020 1021 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_FAN_SPEED, channel)); 1022 time_now = get_jiffies_64(); 1023 1024 /* 1025 * HW register value is accumulated count of pulses from PWM fan with the scale 1026 * of 2 pulses per rotation. 1027 */ 1028 rotations = (reg_val - fi->reg_val_prev) / 2; 1029 1030 time = jiffies_delta_to_msecs(time_now - fi->time_prev); 1031 if (unlikely(!time)) { 1032 ret = -EAGAIN; 1033 goto unlock; 1034 } 1035 1036 /* 1037 * Calculate fan speed in RPM by time averaging two subsequent readings in minutes. 1038 * RPM = number of rotations * msecs per minute / time in msecs 1039 */ 1040 *val = DIV_ROUND_UP_ULL(rotations * (MSEC_PER_SEC * 60), time); 1041 1042 fi->reg_val_prev = reg_val; 1043 fi->time_prev = time_now; 1044 unlock: 1045 mutex_unlock(&hwmon->hwmon_lock); 1046 return ret; 1047 } 1048 1049 static int 1050 xe_hwmon_fan_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 1051 { 1052 switch (attr) { 1053 case hwmon_fan_input: 1054 return xe_hwmon_fan_input_read(hwmon, channel, val); 1055 default: 1056 return -EOPNOTSUPP; 1057 } 1058 } 1059 1060 static umode_t 1061 xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type, 1062 u32 attr, int channel) 1063 { 1064 struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata; 1065 int ret; 1066 1067 xe_pm_runtime_get(hwmon->xe); 1068 1069 switch (type) { 1070 case hwmon_temp: 1071 ret = xe_hwmon_temp_is_visible(hwmon, attr, channel); 1072 break; 1073 case hwmon_power: 1074 ret = xe_hwmon_power_is_visible(hwmon, attr, channel); 1075 break; 1076 case hwmon_curr: 1077 ret = xe_hwmon_curr_is_visible(hwmon, attr, channel); 1078 break; 1079 case hwmon_in: 1080 ret = xe_hwmon_in_is_visible(hwmon, attr, channel); 1081 break; 1082 case hwmon_energy: 1083 ret = xe_hwmon_energy_is_visible(hwmon, attr, channel); 1084 break; 1085 case hwmon_fan: 1086 ret = xe_hwmon_fan_is_visible(hwmon, attr, channel); 1087 break; 1088 default: 1089 ret = 0; 1090 break; 1091 } 1092 1093 xe_pm_runtime_put(hwmon->xe); 1094 1095 return ret; 1096 } 1097 1098 static int 1099 xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, 1100 int channel, long *val) 1101 { 1102 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 1103 int ret; 1104 1105 xe_pm_runtime_get(hwmon->xe); 1106 1107 switch (type) { 1108 case hwmon_temp: 1109 ret = xe_hwmon_temp_read(hwmon, attr, channel, val); 1110 break; 1111 case hwmon_power: 1112 ret = xe_hwmon_power_read(hwmon, attr, channel, val); 1113 break; 1114 case hwmon_curr: 1115 ret = xe_hwmon_curr_read(hwmon, attr, channel, val); 1116 break; 1117 case hwmon_in: 1118 ret = xe_hwmon_in_read(hwmon, attr, channel, val); 1119 break; 1120 case hwmon_energy: 1121 ret = xe_hwmon_energy_read(hwmon, attr, channel, val); 1122 break; 1123 case hwmon_fan: 1124 ret = xe_hwmon_fan_read(hwmon, attr, channel, val); 1125 break; 1126 default: 1127 ret = -EOPNOTSUPP; 1128 break; 1129 } 1130 1131 xe_pm_runtime_put(hwmon->xe); 1132 1133 return ret; 1134 } 1135 1136 static int 1137 xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, 1138 int channel, long val) 1139 { 1140 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 1141 int ret; 1142 1143 xe_pm_runtime_get(hwmon->xe); 1144 1145 switch (type) { 1146 case hwmon_power: 1147 ret = xe_hwmon_power_write(hwmon, attr, channel, val); 1148 break; 1149 case hwmon_curr: 1150 ret = xe_hwmon_curr_write(hwmon, attr, channel, val); 1151 break; 1152 default: 1153 ret = -EOPNOTSUPP; 1154 break; 1155 } 1156 1157 xe_pm_runtime_put(hwmon->xe); 1158 1159 return ret; 1160 } 1161 1162 static int xe_hwmon_read_label(struct device *dev, 1163 enum hwmon_sensor_types type, 1164 u32 attr, int channel, const char **str) 1165 { 1166 switch (type) { 1167 case hwmon_temp: 1168 if (channel == CHANNEL_PKG) 1169 *str = "pkg"; 1170 else if (channel == CHANNEL_VRAM) 1171 *str = "vram"; 1172 return 0; 1173 case hwmon_power: 1174 case hwmon_energy: 1175 case hwmon_curr: 1176 case hwmon_in: 1177 if (channel == CHANNEL_CARD) 1178 *str = "card"; 1179 else if (channel == CHANNEL_PKG) 1180 *str = "pkg"; 1181 return 0; 1182 default: 1183 return -EOPNOTSUPP; 1184 } 1185 } 1186 1187 static const struct hwmon_ops hwmon_ops = { 1188 .is_visible = xe_hwmon_is_visible, 1189 .read = xe_hwmon_read, 1190 .write = xe_hwmon_write, 1191 .read_string = xe_hwmon_read_label, 1192 }; 1193 1194 static const struct hwmon_chip_info hwmon_chip_info = { 1195 .ops = &hwmon_ops, 1196 .info = hwmon_info, 1197 }; 1198 1199 static void 1200 xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon) 1201 { 1202 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 1203 long energy, fan_speed; 1204 u64 val_sku_unit = 0; 1205 int channel; 1206 struct xe_reg pkg_power_sku_unit; 1207 1208 if (hwmon->xe->info.has_mbx_power_limits) { 1209 /* Check if GPU firmware support mailbox power limits commands. */ 1210 if (xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_CARD, 1211 &hwmon->pl1_on_boot[CHANNEL_CARD]) | 1212 xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_PKG, 1213 &hwmon->pl1_on_boot[CHANNEL_PKG]) | 1214 xe_hwmon_pcode_read_power_limit(hwmon, PL2_HWMON_ATTR, CHANNEL_CARD, 1215 &hwmon->pl2_on_boot[CHANNEL_CARD]) | 1216 xe_hwmon_pcode_read_power_limit(hwmon, PL2_HWMON_ATTR, CHANNEL_PKG, 1217 &hwmon->pl2_on_boot[CHANNEL_PKG])) { 1218 drm_warn(&hwmon->xe->drm, 1219 "Failed to read power limits, check GPU firmware !\n"); 1220 } else { 1221 drm_info(&hwmon->xe->drm, "Using mailbox commands for power limits\n"); 1222 /* Write default limits to read from pcode from now on. */ 1223 xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR, 1224 CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME, 1225 hwmon->pl1_on_boot[CHANNEL_CARD]); 1226 xe_hwmon_pcode_rmw_power_limit(hwmon, PL1_HWMON_ATTR, 1227 CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME, 1228 hwmon->pl1_on_boot[CHANNEL_PKG]); 1229 xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR, 1230 CHANNEL_CARD, PWR_LIM | PWR_LIM_TIME, 1231 hwmon->pl2_on_boot[CHANNEL_CARD]); 1232 xe_hwmon_pcode_rmw_power_limit(hwmon, PL2_HWMON_ATTR, 1233 CHANNEL_PKG, PWR_LIM | PWR_LIM_TIME, 1234 hwmon->pl2_on_boot[CHANNEL_PKG]); 1235 hwmon->scl_shift_power = PWR_UNIT; 1236 hwmon->scl_shift_energy = ENERGY_UNIT; 1237 hwmon->scl_shift_time = TIME_UNIT; 1238 hwmon->boot_power_limit_read = true; 1239 } 1240 } else { 1241 drm_info(&hwmon->xe->drm, "Using register for power limits\n"); 1242 /* 1243 * The contents of register PKG_POWER_SKU_UNIT do not change, 1244 * so read it once and store the shift values. 1245 */ 1246 pkg_power_sku_unit = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 0); 1247 if (xe_reg_is_valid(pkg_power_sku_unit)) { 1248 val_sku_unit = xe_mmio_read32(mmio, pkg_power_sku_unit); 1249 hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); 1250 hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit); 1251 hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit); 1252 } 1253 } 1254 /* 1255 * Initialize 'struct xe_hwmon_energy_info', i.e. set fields to the 1256 * first value of the energy register read 1257 */ 1258 for (channel = 0; channel < CHANNEL_MAX; channel++) 1259 if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, channel)) 1260 xe_hwmon_energy_get(hwmon, channel, &energy); 1261 1262 /* Initialize 'struct xe_hwmon_fan_info' with initial fan register reading. */ 1263 for (channel = 0; channel < FAN_MAX; channel++) 1264 if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel)) 1265 xe_hwmon_fan_input_read(hwmon, channel, &fan_speed); 1266 } 1267 1268 static void xe_hwmon_mutex_destroy(void *arg) 1269 { 1270 struct xe_hwmon *hwmon = arg; 1271 1272 mutex_destroy(&hwmon->hwmon_lock); 1273 } 1274 1275 int xe_hwmon_register(struct xe_device *xe) 1276 { 1277 struct device *dev = xe->drm.dev; 1278 struct xe_hwmon *hwmon; 1279 int ret; 1280 1281 /* hwmon is available only for dGfx */ 1282 if (!IS_DGFX(xe)) 1283 return 0; 1284 1285 /* hwmon is not available on VFs */ 1286 if (IS_SRIOV_VF(xe)) 1287 return 0; 1288 1289 hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL); 1290 if (!hwmon) 1291 return -ENOMEM; 1292 1293 mutex_init(&hwmon->hwmon_lock); 1294 ret = devm_add_action_or_reset(dev, xe_hwmon_mutex_destroy, hwmon); 1295 if (ret) 1296 return ret; 1297 1298 /* There's only one instance of hwmon per device */ 1299 hwmon->xe = xe; 1300 xe->hwmon = hwmon; 1301 1302 xe_hwmon_get_preregistration_info(hwmon); 1303 1304 drm_dbg(&xe->drm, "Register xe hwmon interface\n"); 1305 1306 /* hwmon_dev points to device hwmon<i> */ 1307 hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe", hwmon, 1308 &hwmon_chip_info, 1309 hwmon_groups); 1310 if (IS_ERR(hwmon->hwmon_dev)) { 1311 drm_err(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev); 1312 xe->hwmon = NULL; 1313 return PTR_ERR(hwmon->hwmon_dev); 1314 } 1315 1316 return 0; 1317 } 1318 MODULE_IMPORT_NS("INTEL_PMT_TELEMETRY"); 1319