1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/hwmon.h> 8 #include <linux/types.h> 9 10 #include <drm/drm_managed.h> 11 #include "regs/xe_gt_regs.h" 12 #include "regs/xe_mchbar_regs.h" 13 #include "regs/xe_pcode_regs.h" 14 #include "xe_device.h" 15 #include "xe_gt.h" 16 #include "xe_hwmon.h" 17 #include "xe_mmio.h" 18 #include "xe_pcode.h" 19 #include "xe_pcode_api.h" 20 #include "xe_sriov.h" 21 #include "xe_pm.h" 22 23 enum xe_hwmon_reg { 24 REG_PKG_RAPL_LIMIT, 25 REG_PKG_POWER_SKU, 26 REG_PKG_POWER_SKU_UNIT, 27 REG_GT_PERF_STATUS, 28 REG_PKG_ENERGY_STATUS, 29 }; 30 31 enum xe_hwmon_reg_operation { 32 REG_READ32, 33 REG_RMW32, 34 REG_READ64, 35 }; 36 37 enum xe_hwmon_channel { 38 CHANNEL_CARD, 39 CHANNEL_PKG, 40 CHANNEL_MAX, 41 }; 42 43 /* 44 * SF_* - scale factors for particular quantities according to hwmon spec. 45 */ 46 #define SF_POWER 1000000 /* microwatts */ 47 #define SF_CURR 1000 /* milliamperes */ 48 #define SF_VOLTAGE 1000 /* millivolts */ 49 #define SF_ENERGY 1000000 /* microjoules */ 50 #define SF_TIME 1000 /* milliseconds */ 51 52 /** 53 * struct xe_hwmon_energy_info - to accumulate energy 54 */ 55 struct xe_hwmon_energy_info { 56 /** @reg_val_prev: previous energy reg val */ 57 u32 reg_val_prev; 58 /** @accum_energy: accumulated energy */ 59 long accum_energy; 60 }; 61 62 /** 63 * struct xe_hwmon - xe hwmon data structure 64 */ 65 struct xe_hwmon { 66 /** @hwmon_dev: hwmon device for xe */ 67 struct device *hwmon_dev; 68 /** @gt: primary gt */ 69 struct xe_gt *gt; 70 /** @hwmon_lock: lock for rw attributes*/ 71 struct mutex hwmon_lock; 72 /** @scl_shift_power: pkg power unit */ 73 int scl_shift_power; 74 /** @scl_shift_energy: pkg energy unit */ 75 int scl_shift_energy; 76 /** @scl_shift_time: pkg time unit */ 77 int scl_shift_time; 78 /** @ei: Energy info for energyN_input */ 79 struct xe_hwmon_energy_info ei[CHANNEL_MAX]; 80 }; 81 82 static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, 83 int channel) 84 { 85 struct xe_device *xe = gt_to_xe(hwmon->gt); 86 87 switch (hwmon_reg) { 88 case REG_PKG_RAPL_LIMIT: 89 if (xe->info.platform == XE_BATTLEMAGE) { 90 if (channel == CHANNEL_PKG) 91 return BMG_PACKAGE_RAPL_LIMIT; 92 else 93 return BMG_PLATFORM_POWER_LIMIT; 94 } else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { 95 return PVC_GT0_PACKAGE_RAPL_LIMIT; 96 } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) { 97 return PCU_CR_PACKAGE_RAPL_LIMIT; 98 } 99 break; 100 case REG_PKG_POWER_SKU: 101 if (xe->info.platform == XE_BATTLEMAGE) 102 return BMG_PACKAGE_POWER_SKU; 103 else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) 104 return PVC_GT0_PACKAGE_POWER_SKU; 105 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) 106 return PCU_CR_PACKAGE_POWER_SKU; 107 break; 108 case REG_PKG_POWER_SKU_UNIT: 109 if (xe->info.platform == XE_BATTLEMAGE) 110 return BMG_PACKAGE_POWER_SKU_UNIT; 111 else if (xe->info.platform == XE_PVC) 112 return PVC_GT0_PACKAGE_POWER_SKU_UNIT; 113 else if (xe->info.platform == XE_DG2) 114 return PCU_CR_PACKAGE_POWER_SKU_UNIT; 115 break; 116 case REG_GT_PERF_STATUS: 117 if (xe->info.platform == XE_DG2 && channel == CHANNEL_PKG) 118 return GT_PERF_STATUS; 119 break; 120 case REG_PKG_ENERGY_STATUS: 121 if (xe->info.platform == XE_BATTLEMAGE) { 122 if (channel == CHANNEL_PKG) 123 return BMG_PACKAGE_ENERGY_STATUS; 124 else 125 return BMG_PLATFORM_ENERGY_STATUS; 126 } else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { 127 return PVC_GT0_PLATFORM_ENERGY_STATUS; 128 } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) { 129 return PCU_CR_PACKAGE_ENERGY_STATUS; 130 } 131 break; 132 default: 133 drm_warn(&xe->drm, "Unknown xe hwmon reg id: %d\n", hwmon_reg); 134 break; 135 } 136 137 return XE_REG(0); 138 } 139 140 #define PL1_DISABLE 0 141 142 /* 143 * HW allows arbitrary PL1 limits to be set but silently clamps these values to 144 * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the 145 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display 146 * clamped values when read. 147 */ 148 static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, int channel, long *value) 149 { 150 u64 reg_val, min, max; 151 struct xe_device *xe = gt_to_xe(hwmon->gt); 152 struct xe_reg rapl_limit, pkg_power_sku; 153 154 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 155 pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 156 157 /* 158 * Valid check of REG_PKG_RAPL_LIMIT is already done in xe_hwmon_power_is_visible. 159 * So not checking it again here. 160 */ 161 if (!xe_reg_is_valid(pkg_power_sku)) { 162 drm_warn(&xe->drm, "pkg_power_sku invalid\n"); 163 *value = 0; 164 return; 165 } 166 167 mutex_lock(&hwmon->hwmon_lock); 168 169 reg_val = xe_mmio_read32(hwmon->gt, rapl_limit); 170 /* Check if PL1 limit is disabled */ 171 if (!(reg_val & PKG_PWR_LIM_1_EN)) { 172 *value = PL1_DISABLE; 173 goto unlock; 174 } 175 176 reg_val = REG_FIELD_GET(PKG_PWR_LIM_1, reg_val); 177 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power); 178 179 reg_val = xe_mmio_read64_2x32(hwmon->gt, pkg_power_sku); 180 min = REG_FIELD_GET(PKG_MIN_PWR, reg_val); 181 min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power); 182 max = REG_FIELD_GET(PKG_MAX_PWR, reg_val); 183 max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power); 184 185 if (min && max) 186 *value = clamp_t(u64, *value, min, max); 187 unlock: 188 mutex_unlock(&hwmon->hwmon_lock); 189 } 190 191 static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, int channel, long value) 192 { 193 int ret = 0; 194 u64 reg_val; 195 struct xe_reg rapl_limit; 196 197 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 198 199 mutex_lock(&hwmon->hwmon_lock); 200 201 /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */ 202 if (value == PL1_DISABLE) { 203 reg_val = xe_mmio_rmw32(hwmon->gt, rapl_limit, PKG_PWR_LIM_1_EN, 0); 204 reg_val = xe_mmio_read32(hwmon->gt, rapl_limit); 205 if (reg_val & PKG_PWR_LIM_1_EN) { 206 drm_warn(>_to_xe(hwmon->gt)->drm, "PL1 disable is not supported!\n"); 207 ret = -EOPNOTSUPP; 208 } 209 goto unlock; 210 } 211 212 /* Computation in 64-bits to avoid overflow. Round to nearest. */ 213 reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER); 214 reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val); 215 reg_val = xe_mmio_rmw32(hwmon->gt, rapl_limit, PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val); 216 217 unlock: 218 mutex_unlock(&hwmon->hwmon_lock); 219 return ret; 220 } 221 222 static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, int channel, long *value) 223 { 224 struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 225 u64 reg_val; 226 227 /* 228 * This sysfs file won't be visible if REG_PKG_POWER_SKU is invalid, so valid check 229 * for this register can be skipped. 230 * See xe_hwmon_power_is_visible. 231 */ 232 reg_val = xe_mmio_read32(hwmon->gt, reg); 233 reg_val = REG_FIELD_GET(PKG_TDP, reg_val); 234 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power); 235 } 236 237 /* 238 * xe_hwmon_energy_get - Obtain energy value 239 * 240 * The underlying energy hardware register is 32-bits and is subject to 241 * overflow. How long before overflow? For example, with an example 242 * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and 243 * a power draw of 1000 watts, the 32-bit counter will overflow in 244 * approximately 4.36 minutes. 245 * 246 * Examples: 247 * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days 248 * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes 249 * 250 * The function significantly increases overflow duration (from 4.36 251 * minutes) by accumulating the energy register into a 'long' as allowed by 252 * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()), 253 * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and 254 * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before 255 * energyN_input overflows. This at 1000 W is an overflow duration of 278 years. 256 */ 257 static void 258 xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy) 259 { 260 struct xe_hwmon_energy_info *ei = &hwmon->ei[channel]; 261 u64 reg_val; 262 263 reg_val = xe_mmio_read32(hwmon->gt, xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, 264 channel)); 265 266 if (reg_val >= ei->reg_val_prev) 267 ei->accum_energy += reg_val - ei->reg_val_prev; 268 else 269 ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val; 270 271 ei->reg_val_prev = reg_val; 272 273 *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY, 274 hwmon->scl_shift_energy); 275 } 276 277 static ssize_t 278 xe_hwmon_power_max_interval_show(struct device *dev, struct device_attribute *attr, 279 char *buf) 280 { 281 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 282 u32 x, y, x_w = 2; /* 2 bits */ 283 u64 r, tau4, out; 284 int sensor_index = to_sensor_dev_attr(attr)->index; 285 286 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 287 288 mutex_lock(&hwmon->hwmon_lock); 289 290 r = xe_mmio_read32(hwmon->gt, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, sensor_index)); 291 292 mutex_unlock(&hwmon->hwmon_lock); 293 294 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 295 296 x = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_X, r); 297 y = REG_FIELD_GET(PKG_PWR_LIM_1_TIME_Y, r); 298 299 /* 300 * tau = 1.x * power(2,y), x = bits(23:22), y = bits(21:17) 301 * = (4 | x) << (y - 2) 302 * 303 * Here (y - 2) ensures a 1.x fixed point representation of 1.x 304 * As x is 2 bits so 1.x can be 1.0, 1.25, 1.50, 1.75 305 * 306 * As y can be < 2, we compute tau4 = (4 | x) << y 307 * and then add 2 when doing the final right shift to account for units 308 */ 309 tau4 = (u64)((1 << x_w) | x) << y; 310 311 /* val in hwmon interface units (millisec) */ 312 out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 313 314 return sysfs_emit(buf, "%llu\n", out); 315 } 316 317 static ssize_t 318 xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *attr, 319 const char *buf, size_t count) 320 { 321 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 322 u32 x, y, rxy, x_w = 2; /* 2 bits */ 323 u64 tau4, r, max_win; 324 unsigned long val; 325 int ret; 326 int sensor_index = to_sensor_dev_attr(attr)->index; 327 328 ret = kstrtoul(buf, 0, &val); 329 if (ret) 330 return ret; 331 332 /* 333 * Max HW supported tau in '1.x * power(2,y)' format, x = 0, y = 0x12. 334 * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds. 335 * 336 * The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register. 337 * However, it is observed that existing discrete GPUs does not provide correct 338 * PKG_MAX_WIN value, therefore a using default constant value. For future discrete GPUs 339 * this may get resolved, in which case PKG_MAX_WIN should be obtained from PKG_PWR_SKU. 340 */ 341 #define PKG_MAX_WIN_DEFAULT 0x12ull 342 343 /* 344 * val must be < max in hwmon interface units. The steps below are 345 * explained in xe_hwmon_power_max_interval_show() 346 */ 347 r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT); 348 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); 349 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); 350 tau4 = (u64)((1 << x_w) | x) << y; 351 max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 352 353 if (val > max_win) 354 return -EINVAL; 355 356 /* val in hw units */ 357 val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME); 358 359 /* 360 * Convert val to 1.x * power(2,y) 361 * y = ilog2(val) 362 * x = (val - (1 << y)) >> (y - 2) 363 */ 364 if (!val) { 365 y = 0; 366 x = 0; 367 } else { 368 y = ilog2(val); 369 x = (val - (1ul << y)) << x_w >> y; 370 } 371 372 rxy = REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_X, x) | REG_FIELD_PREP(PKG_PWR_LIM_1_TIME_Y, y); 373 374 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 375 376 mutex_lock(&hwmon->hwmon_lock); 377 378 r = xe_mmio_rmw32(hwmon->gt, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, sensor_index), 379 PKG_PWR_LIM_1_TIME, rxy); 380 381 mutex_unlock(&hwmon->hwmon_lock); 382 383 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 384 385 return count; 386 } 387 388 static SENSOR_DEVICE_ATTR(power1_max_interval, 0664, 389 xe_hwmon_power_max_interval_show, 390 xe_hwmon_power_max_interval_store, CHANNEL_CARD); 391 392 static SENSOR_DEVICE_ATTR(power2_max_interval, 0664, 393 xe_hwmon_power_max_interval_show, 394 xe_hwmon_power_max_interval_store, CHANNEL_PKG); 395 396 static struct attribute *hwmon_attributes[] = { 397 &sensor_dev_attr_power1_max_interval.dev_attr.attr, 398 &sensor_dev_attr_power2_max_interval.dev_attr.attr, 399 NULL 400 }; 401 402 static umode_t xe_hwmon_attributes_visible(struct kobject *kobj, 403 struct attribute *attr, int index) 404 { 405 struct device *dev = kobj_to_dev(kobj); 406 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 407 int ret = 0; 408 409 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 410 411 ret = xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, index)) ? attr->mode : 0; 412 413 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 414 415 return ret; 416 } 417 418 static const struct attribute_group hwmon_attrgroup = { 419 .attrs = hwmon_attributes, 420 .is_visible = xe_hwmon_attributes_visible, 421 }; 422 423 static const struct attribute_group *hwmon_groups[] = { 424 &hwmon_attrgroup, 425 NULL 426 }; 427 428 static const struct hwmon_channel_info * const hwmon_info[] = { 429 HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL, 430 HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_CRIT | HWMON_P_LABEL), 431 HWMON_CHANNEL_INFO(curr, HWMON_C_LABEL, HWMON_C_CRIT | HWMON_C_LABEL), 432 HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL), 433 HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT | HWMON_E_LABEL, HWMON_E_INPUT | HWMON_E_LABEL), 434 NULL 435 }; 436 437 /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */ 438 static int xe_hwmon_pcode_read_i1(struct xe_gt *gt, u32 *uval) 439 { 440 /* Avoid Illegal Subcommand error */ 441 if (gt_to_xe(gt)->info.platform == XE_DG2) 442 return -ENXIO; 443 444 return xe_pcode_read(gt, PCODE_MBOX(PCODE_POWER_SETUP, 445 POWER_SETUP_SUBCOMMAND_READ_I1, 0), 446 uval, NULL); 447 } 448 449 static int xe_hwmon_pcode_write_i1(struct xe_gt *gt, u32 uval) 450 { 451 return xe_pcode_write(gt, PCODE_MBOX(PCODE_POWER_SETUP, 452 POWER_SETUP_SUBCOMMAND_WRITE_I1, 0), 453 (uval & POWER_SETUP_I1_DATA_MASK)); 454 } 455 456 static int xe_hwmon_power_curr_crit_read(struct xe_hwmon *hwmon, int channel, 457 long *value, u32 scale_factor) 458 { 459 int ret; 460 u32 uval; 461 462 mutex_lock(&hwmon->hwmon_lock); 463 464 ret = xe_hwmon_pcode_read_i1(hwmon->gt, &uval); 465 if (ret) 466 goto unlock; 467 468 *value = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), 469 scale_factor, POWER_SETUP_I1_SHIFT); 470 unlock: 471 mutex_unlock(&hwmon->hwmon_lock); 472 return ret; 473 } 474 475 static int xe_hwmon_power_curr_crit_write(struct xe_hwmon *hwmon, int channel, 476 long value, u32 scale_factor) 477 { 478 int ret; 479 u32 uval; 480 481 mutex_lock(&hwmon->hwmon_lock); 482 483 uval = DIV_ROUND_CLOSEST_ULL(value << POWER_SETUP_I1_SHIFT, scale_factor); 484 ret = xe_hwmon_pcode_write_i1(hwmon->gt, uval); 485 486 mutex_unlock(&hwmon->hwmon_lock); 487 return ret; 488 } 489 490 static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *value) 491 { 492 u64 reg_val; 493 494 reg_val = xe_mmio_read32(hwmon->gt, xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, channel)); 495 /* HW register value in units of 2.5 millivolt */ 496 *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE); 497 } 498 499 static umode_t 500 xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 501 { 502 u32 uval; 503 504 switch (attr) { 505 case hwmon_power_max: 506 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, 507 channel)) ? 0664 : 0; 508 case hwmon_power_rated_max: 509 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, 510 channel)) ? 0444 : 0; 511 case hwmon_power_crit: 512 if (channel == CHANNEL_PKG) 513 return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) || 514 !(uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644; 515 break; 516 case hwmon_power_label: 517 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 518 channel)) ? 0444 : 0; 519 default: 520 return 0; 521 } 522 return 0; 523 } 524 525 static int 526 xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 527 { 528 switch (attr) { 529 case hwmon_power_max: 530 xe_hwmon_power_max_read(hwmon, channel, val); 531 return 0; 532 case hwmon_power_rated_max: 533 xe_hwmon_power_rated_max_read(hwmon, channel, val); 534 return 0; 535 case hwmon_power_crit: 536 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_POWER); 537 default: 538 return -EOPNOTSUPP; 539 } 540 } 541 542 static int 543 xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 544 { 545 switch (attr) { 546 case hwmon_power_max: 547 return xe_hwmon_power_max_write(hwmon, channel, val); 548 case hwmon_power_crit: 549 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_POWER); 550 default: 551 return -EOPNOTSUPP; 552 } 553 } 554 555 static umode_t 556 xe_hwmon_curr_is_visible(const struct xe_hwmon *hwmon, u32 attr, int channel) 557 { 558 u32 uval; 559 560 /* hwmon sysfs attribute of current available only for package */ 561 if (channel != CHANNEL_PKG) 562 return 0; 563 564 switch (attr) { 565 case hwmon_curr_crit: 566 return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) || 567 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644; 568 case hwmon_curr_label: 569 return (xe_hwmon_pcode_read_i1(hwmon->gt, &uval) || 570 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0444; 571 break; 572 default: 573 return 0; 574 } 575 return 0; 576 } 577 578 static int 579 xe_hwmon_curr_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 580 { 581 switch (attr) { 582 case hwmon_curr_crit: 583 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_CURR); 584 default: 585 return -EOPNOTSUPP; 586 } 587 } 588 589 static int 590 xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 591 { 592 switch (attr) { 593 case hwmon_curr_crit: 594 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_CURR); 595 default: 596 return -EOPNOTSUPP; 597 } 598 } 599 600 static umode_t 601 xe_hwmon_in_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 602 { 603 switch (attr) { 604 case hwmon_in_input: 605 case hwmon_in_label: 606 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, 607 channel)) ? 0444 : 0; 608 default: 609 return 0; 610 } 611 } 612 613 static int 614 xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 615 { 616 switch (attr) { 617 case hwmon_in_input: 618 xe_hwmon_get_voltage(hwmon, channel, val); 619 return 0; 620 default: 621 return -EOPNOTSUPP; 622 } 623 } 624 625 static umode_t 626 xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 627 { 628 switch (attr) { 629 case hwmon_energy_input: 630 case hwmon_energy_label: 631 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, 632 channel)) ? 0444 : 0; 633 default: 634 return 0; 635 } 636 } 637 638 static int 639 xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 640 { 641 switch (attr) { 642 case hwmon_energy_input: 643 xe_hwmon_energy_get(hwmon, channel, val); 644 return 0; 645 default: 646 return -EOPNOTSUPP; 647 } 648 } 649 650 static umode_t 651 xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type, 652 u32 attr, int channel) 653 { 654 struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata; 655 int ret; 656 657 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 658 659 switch (type) { 660 case hwmon_power: 661 ret = xe_hwmon_power_is_visible(hwmon, attr, channel); 662 break; 663 case hwmon_curr: 664 ret = xe_hwmon_curr_is_visible(hwmon, attr, channel); 665 break; 666 case hwmon_in: 667 ret = xe_hwmon_in_is_visible(hwmon, attr, channel); 668 break; 669 case hwmon_energy: 670 ret = xe_hwmon_energy_is_visible(hwmon, attr, channel); 671 break; 672 default: 673 ret = 0; 674 break; 675 } 676 677 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 678 679 return ret; 680 } 681 682 static int 683 xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, 684 int channel, long *val) 685 { 686 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 687 int ret; 688 689 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 690 691 switch (type) { 692 case hwmon_power: 693 ret = xe_hwmon_power_read(hwmon, attr, channel, val); 694 break; 695 case hwmon_curr: 696 ret = xe_hwmon_curr_read(hwmon, attr, channel, val); 697 break; 698 case hwmon_in: 699 ret = xe_hwmon_in_read(hwmon, attr, channel, val); 700 break; 701 case hwmon_energy: 702 ret = xe_hwmon_energy_read(hwmon, attr, channel, val); 703 break; 704 default: 705 ret = -EOPNOTSUPP; 706 break; 707 } 708 709 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 710 711 return ret; 712 } 713 714 static int 715 xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, 716 int channel, long val) 717 { 718 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 719 int ret; 720 721 xe_pm_runtime_get(gt_to_xe(hwmon->gt)); 722 723 switch (type) { 724 case hwmon_power: 725 ret = xe_hwmon_power_write(hwmon, attr, channel, val); 726 break; 727 case hwmon_curr: 728 ret = xe_hwmon_curr_write(hwmon, attr, channel, val); 729 break; 730 default: 731 ret = -EOPNOTSUPP; 732 break; 733 } 734 735 xe_pm_runtime_put(gt_to_xe(hwmon->gt)); 736 737 return ret; 738 } 739 740 static int xe_hwmon_read_label(struct device *dev, 741 enum hwmon_sensor_types type, 742 u32 attr, int channel, const char **str) 743 { 744 switch (type) { 745 case hwmon_power: 746 case hwmon_energy: 747 case hwmon_curr: 748 case hwmon_in: 749 if (channel == CHANNEL_CARD) 750 *str = "card"; 751 else if (channel == CHANNEL_PKG) 752 *str = "pkg"; 753 return 0; 754 default: 755 return -EOPNOTSUPP; 756 } 757 } 758 759 static const struct hwmon_ops hwmon_ops = { 760 .is_visible = xe_hwmon_is_visible, 761 .read = xe_hwmon_read, 762 .write = xe_hwmon_write, 763 .read_string = xe_hwmon_read_label, 764 }; 765 766 static const struct hwmon_chip_info hwmon_chip_info = { 767 .ops = &hwmon_ops, 768 .info = hwmon_info, 769 }; 770 771 static void 772 xe_hwmon_get_preregistration_info(struct xe_device *xe) 773 { 774 struct xe_hwmon *hwmon = xe->hwmon; 775 long energy; 776 u64 val_sku_unit = 0; 777 int channel; 778 struct xe_reg pkg_power_sku_unit; 779 780 /* 781 * The contents of register PKG_POWER_SKU_UNIT do not change, 782 * so read it once and store the shift values. 783 */ 784 pkg_power_sku_unit = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 0); 785 if (xe_reg_is_valid(pkg_power_sku_unit)) { 786 val_sku_unit = xe_mmio_read32(hwmon->gt, pkg_power_sku_unit); 787 hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); 788 hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit); 789 hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit); 790 } 791 792 /* 793 * Initialize 'struct xe_hwmon_energy_info', i.e. set fields to the 794 * first value of the energy register read 795 */ 796 for (channel = 0; channel < CHANNEL_MAX; channel++) 797 if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, channel)) 798 xe_hwmon_energy_get(hwmon, channel, &energy); 799 } 800 801 static void xe_hwmon_mutex_destroy(void *arg) 802 { 803 struct xe_hwmon *hwmon = arg; 804 805 mutex_destroy(&hwmon->hwmon_lock); 806 } 807 808 void xe_hwmon_register(struct xe_device *xe) 809 { 810 struct device *dev = xe->drm.dev; 811 struct xe_hwmon *hwmon; 812 813 /* hwmon is available only for dGfx */ 814 if (!IS_DGFX(xe)) 815 return; 816 817 /* hwmon is not available on VFs */ 818 if (IS_SRIOV_VF(xe)) 819 return; 820 821 hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL); 822 if (!hwmon) 823 return; 824 825 xe->hwmon = hwmon; 826 827 mutex_init(&hwmon->hwmon_lock); 828 if (devm_add_action_or_reset(dev, xe_hwmon_mutex_destroy, hwmon)) 829 return; 830 831 /* primary GT to access device level properties */ 832 hwmon->gt = xe->tiles[0].primary_gt; 833 834 xe_hwmon_get_preregistration_info(xe); 835 836 drm_dbg(&xe->drm, "Register xe hwmon interface\n"); 837 838 /* hwmon_dev points to device hwmon<i> */ 839 hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe", hwmon, 840 &hwmon_chip_info, 841 hwmon_groups); 842 843 if (IS_ERR(hwmon->hwmon_dev)) { 844 drm_warn(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev); 845 xe->hwmon = NULL; 846 return; 847 } 848 } 849 850