1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/hwmon-sysfs.h> 7 #include <linux/hwmon.h> 8 #include <linux/jiffies.h> 9 #include <linux/types.h> 10 #include <linux/units.h> 11 12 #include <drm/drm_managed.h> 13 #include "regs/xe_gt_regs.h" 14 #include "regs/xe_mchbar_regs.h" 15 #include "regs/xe_pcode_regs.h" 16 #include "xe_device.h" 17 #include "xe_hwmon.h" 18 #include "xe_mmio.h" 19 #include "xe_pcode.h" 20 #include "xe_pcode_api.h" 21 #include "xe_sriov.h" 22 #include "xe_pm.h" 23 24 enum xe_hwmon_reg { 25 REG_TEMP, 26 REG_PKG_RAPL_LIMIT, 27 REG_PKG_POWER_SKU, 28 REG_PKG_POWER_SKU_UNIT, 29 REG_GT_PERF_STATUS, 30 REG_PKG_ENERGY_STATUS, 31 REG_FAN_SPEED, 32 }; 33 34 enum xe_hwmon_reg_operation { 35 REG_READ32, 36 REG_RMW32, 37 REG_READ64, 38 }; 39 40 enum xe_hwmon_channel { 41 CHANNEL_CARD, 42 CHANNEL_PKG, 43 CHANNEL_VRAM, 44 CHANNEL_MAX, 45 }; 46 47 enum xe_fan_channel { 48 FAN_1, 49 FAN_2, 50 FAN_3, 51 FAN_MAX, 52 }; 53 54 /* 55 * For platforms that support mailbox commands for power limits, REG_PKG_POWER_SKU_UNIT is 56 * not supported and below are SKU units to be used. 57 */ 58 #define PWR_UNIT 0x3 59 #define ENERGY_UNIT 0xe 60 #define TIME_UNIT 0xa 61 62 /* 63 * SF_* - scale factors for particular quantities according to hwmon spec. 64 */ 65 #define SF_POWER 1000000 /* microwatts */ 66 #define SF_CURR 1000 /* milliamperes */ 67 #define SF_VOLTAGE 1000 /* millivolts */ 68 #define SF_ENERGY 1000000 /* microjoules */ 69 #define SF_TIME 1000 /* milliseconds */ 70 71 /* 72 * PL*_HWMON_ATTR - mapping of hardware power limits to corresponding hwmon power attribute. 73 */ 74 #define PL1_HWMON_ATTR hwmon_power_max 75 76 #define PWR_ATTR_TO_STR(attr) (((attr) == hwmon_power_max) ? "PL1" : "Invalid") 77 78 /* 79 * Timeout for power limit write mailbox command. 80 */ 81 #define PL_WRITE_MBX_TIMEOUT_MS (1) 82 83 /** 84 * struct xe_hwmon_energy_info - to accumulate energy 85 */ 86 struct xe_hwmon_energy_info { 87 /** @reg_val_prev: previous energy reg val */ 88 u32 reg_val_prev; 89 /** @accum_energy: accumulated energy */ 90 long accum_energy; 91 }; 92 93 /** 94 * struct xe_hwmon_fan_info - to cache previous fan reading 95 */ 96 struct xe_hwmon_fan_info { 97 /** @reg_val_prev: previous fan reg val */ 98 u32 reg_val_prev; 99 /** @time_prev: previous timestamp */ 100 u64 time_prev; 101 }; 102 103 /** 104 * struct xe_hwmon - xe hwmon data structure 105 */ 106 struct xe_hwmon { 107 /** @hwmon_dev: hwmon device for xe */ 108 struct device *hwmon_dev; 109 /** @xe: Xe device */ 110 struct xe_device *xe; 111 /** @hwmon_lock: lock for rw attributes*/ 112 struct mutex hwmon_lock; 113 /** @scl_shift_power: pkg power unit */ 114 int scl_shift_power; 115 /** @scl_shift_energy: pkg energy unit */ 116 int scl_shift_energy; 117 /** @scl_shift_time: pkg time unit */ 118 int scl_shift_time; 119 /** @ei: Energy info for energyN_input */ 120 struct xe_hwmon_energy_info ei[CHANNEL_MAX]; 121 /** @fi: Fan info for fanN_input */ 122 struct xe_hwmon_fan_info fi[FAN_MAX]; 123 /** @boot_power_limit_read: is boot power limits read */ 124 bool boot_power_limit_read; 125 /** @pl1_on_boot: power limit PL1 on boot */ 126 u32 pl1_on_boot[CHANNEL_MAX]; 127 }; 128 129 static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel, 130 u32 *uval) 131 { 132 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 133 u32 val0 = 0, val1 = 0; 134 int ret = 0; 135 136 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 137 (channel == CHANNEL_CARD) ? 138 READ_PSYSGPU_POWER_LIMIT : 139 READ_PACKAGE_POWER_LIMIT, 140 hwmon->boot_power_limit_read ? 141 READ_PL_FROM_PCODE : READ_PL_FROM_FW), 142 &val0, &val1); 143 144 if (ret) { 145 drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 146 channel, val0, val1, ret); 147 *uval = 0; 148 return ret; 149 } 150 151 /* return the value only if limit is enabled */ 152 if (attr == PL1_HWMON_ATTR) 153 *uval = (val0 & PWR_LIM_EN) ? val0 : 0; 154 else if (attr == hwmon_power_label) 155 *uval = (val0 & PWR_LIM_EN) ? 1 : 0; 156 else 157 *uval = 0; 158 159 return ret; 160 } 161 162 static int xe_hwmon_pcode_write_power_limit(const struct xe_hwmon *hwmon, u32 attr, u8 channel, 163 u32 uval) 164 { 165 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 166 u32 val0, val1; 167 int ret = 0; 168 169 ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 170 (channel == CHANNEL_CARD) ? 171 READ_PSYSGPU_POWER_LIMIT : 172 READ_PACKAGE_POWER_LIMIT, 173 hwmon->boot_power_limit_read ? 174 READ_PL_FROM_PCODE : READ_PL_FROM_FW), 175 &val0, &val1); 176 177 if (ret) 178 drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 179 channel, val0, val1, ret); 180 181 if (attr == PL1_HWMON_ATTR) 182 val0 = uval; 183 else 184 return -EIO; 185 186 ret = xe_pcode_write64_timeout(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 187 (channel == CHANNEL_CARD) ? 188 WRITE_PSYSGPU_POWER_LIMIT : 189 WRITE_PACKAGE_POWER_LIMIT, 0), 190 val0, val1, PL_WRITE_MBX_TIMEOUT_MS); 191 if (ret) 192 drm_dbg(&hwmon->xe->drm, "write failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n", 193 channel, val0, val1, ret); 194 return ret; 195 } 196 197 static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg hwmon_reg, 198 int channel) 199 { 200 struct xe_device *xe = hwmon->xe; 201 202 switch (hwmon_reg) { 203 case REG_TEMP: 204 if (xe->info.platform == XE_BATTLEMAGE) { 205 if (channel == CHANNEL_PKG) 206 return BMG_PACKAGE_TEMPERATURE; 207 else if (channel == CHANNEL_VRAM) 208 return BMG_VRAM_TEMPERATURE; 209 } else if (xe->info.platform == XE_DG2) { 210 if (channel == CHANNEL_PKG) 211 return PCU_CR_PACKAGE_TEMPERATURE; 212 else if (channel == CHANNEL_VRAM) 213 return BMG_VRAM_TEMPERATURE; 214 } 215 break; 216 case REG_PKG_RAPL_LIMIT: 217 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) 218 return PVC_GT0_PACKAGE_RAPL_LIMIT; 219 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) 220 return PCU_CR_PACKAGE_RAPL_LIMIT; 221 break; 222 case REG_PKG_POWER_SKU: 223 if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) 224 return PVC_GT0_PACKAGE_POWER_SKU; 225 else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) 226 return PCU_CR_PACKAGE_POWER_SKU; 227 break; 228 case REG_PKG_POWER_SKU_UNIT: 229 if (xe->info.platform == XE_PVC) 230 return PVC_GT0_PACKAGE_POWER_SKU_UNIT; 231 else if (xe->info.platform == XE_DG2) 232 return PCU_CR_PACKAGE_POWER_SKU_UNIT; 233 break; 234 case REG_GT_PERF_STATUS: 235 if (xe->info.platform == XE_DG2 && channel == CHANNEL_PKG) 236 return GT_PERF_STATUS; 237 break; 238 case REG_PKG_ENERGY_STATUS: 239 if (xe->info.platform == XE_BATTLEMAGE) { 240 if (channel == CHANNEL_PKG) 241 return BMG_PACKAGE_ENERGY_STATUS; 242 else 243 return BMG_PLATFORM_ENERGY_STATUS; 244 } else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) { 245 return PVC_GT0_PLATFORM_ENERGY_STATUS; 246 } else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) { 247 return PCU_CR_PACKAGE_ENERGY_STATUS; 248 } 249 break; 250 case REG_FAN_SPEED: 251 if (channel == FAN_1) 252 return BMG_FAN_1_SPEED; 253 else if (channel == FAN_2) 254 return BMG_FAN_2_SPEED; 255 else if (channel == FAN_3) 256 return BMG_FAN_3_SPEED; 257 break; 258 default: 259 drm_warn(&xe->drm, "Unknown xe hwmon reg id: %d\n", hwmon_reg); 260 break; 261 } 262 263 return XE_REG(0); 264 } 265 266 #define PL_DISABLE 0 267 268 /* 269 * HW allows arbitrary PL1 limits to be set but silently clamps these values to 270 * "typical but not guaranteed" min/max values in REG_PKG_POWER_SKU. Follow the 271 * same pattern for sysfs, allow arbitrary PL1 limits to be set but display 272 * clamped values when read. 273 */ 274 static void xe_hwmon_power_max_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *value) 275 { 276 u64 reg_val, min, max; 277 struct xe_device *xe = hwmon->xe; 278 struct xe_reg rapl_limit, pkg_power_sku; 279 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 280 281 mutex_lock(&hwmon->hwmon_lock); 282 283 if (hwmon->xe->info.has_mbx_power_limits) { 284 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, (u32 *)®_val); 285 } else { 286 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 287 pkg_power_sku = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 288 289 /* 290 * Valid check of REG_PKG_RAPL_LIMIT is already done in xe_hwmon_power_is_visible. 291 * So not checking it again here. 292 */ 293 if (!xe_reg_is_valid(pkg_power_sku)) { 294 drm_warn(&xe->drm, "pkg_power_sku invalid\n"); 295 *value = 0; 296 goto unlock; 297 } 298 reg_val = xe_mmio_read32(mmio, rapl_limit); 299 } 300 301 /* Check if PL limits are disabled. */ 302 if (!(reg_val & PWR_LIM_EN)) { 303 *value = PL_DISABLE; 304 drm_info(&hwmon->xe->drm, "%s disabled for channel %d, val 0x%016llx\n", 305 PWR_ATTR_TO_STR(attr), channel, reg_val); 306 goto unlock; 307 } 308 309 reg_val = REG_FIELD_GET(PWR_LIM_VAL, reg_val); 310 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power); 311 312 /* For platforms with mailbox power limit support clamping would be done by pcode. */ 313 if (!hwmon->xe->info.has_mbx_power_limits) { 314 reg_val = xe_mmio_read64_2x32(mmio, pkg_power_sku); 315 min = REG_FIELD_GET(PKG_MIN_PWR, reg_val); 316 max = REG_FIELD_GET(PKG_MAX_PWR, reg_val); 317 min = mul_u64_u32_shr(min, SF_POWER, hwmon->scl_shift_power); 318 max = mul_u64_u32_shr(max, SF_POWER, hwmon->scl_shift_power); 319 if (min && max) 320 *value = clamp_t(u64, *value, min, max); 321 } 322 unlock: 323 mutex_unlock(&hwmon->hwmon_lock); 324 } 325 326 static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, u32 attr, int channel, long value) 327 { 328 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 329 int ret = 0; 330 u32 reg_val; 331 struct xe_reg rapl_limit; 332 333 mutex_lock(&hwmon->hwmon_lock); 334 335 rapl_limit = xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel); 336 337 /* Disable Power Limit and verify, as limit cannot be disabled on all platforms. */ 338 if (value == PL_DISABLE) { 339 if (hwmon->xe->info.has_mbx_power_limits) { 340 drm_dbg(&hwmon->xe->drm, "disabling %s on channel %d\n", 341 PWR_ATTR_TO_STR(attr), channel); 342 xe_hwmon_pcode_write_power_limit(hwmon, attr, channel, 0); 343 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, ®_val); 344 } else { 345 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN, 0); 346 reg_val = xe_mmio_read32(mmio, rapl_limit); 347 } 348 349 if (reg_val & PWR_LIM_EN) { 350 drm_warn(&hwmon->xe->drm, "Power limit disable is not supported!\n"); 351 ret = -EOPNOTSUPP; 352 } 353 goto unlock; 354 } 355 356 /* Computation in 64-bits to avoid overflow. Round to nearest. */ 357 reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER); 358 reg_val = PWR_LIM_EN | REG_FIELD_PREP(PWR_LIM_VAL, reg_val); 359 360 /* 361 * Clamp power limit to card-firmware default as maximum, as an additional protection to 362 * pcode clamp. 363 */ 364 if (hwmon->xe->info.has_mbx_power_limits) { 365 if (reg_val > REG_FIELD_GET(PWR_LIM_VAL, hwmon->pl1_on_boot[channel])) { 366 reg_val = REG_FIELD_GET(PWR_LIM_VAL, hwmon->pl1_on_boot[channel]); 367 drm_dbg(&hwmon->xe->drm, "Clamping power limit to firmware default 0x%x\n", 368 reg_val); 369 } 370 } 371 372 if (hwmon->xe->info.has_mbx_power_limits) 373 ret = xe_hwmon_pcode_write_power_limit(hwmon, attr, channel, reg_val); 374 else 375 reg_val = xe_mmio_rmw32(mmio, rapl_limit, PWR_LIM_EN | PWR_LIM_VAL, 376 reg_val); 377 unlock: 378 mutex_unlock(&hwmon->hwmon_lock); 379 return ret; 380 } 381 382 static void xe_hwmon_power_rated_max_read(struct xe_hwmon *hwmon, u32 attr, int channel, 383 long *value) 384 { 385 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 386 u32 reg_val; 387 388 if (hwmon->xe->info.has_mbx_power_limits) { 389 /* PL1 is rated max if supported. */ 390 xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, channel, ®_val); 391 } else { 392 /* 393 * This sysfs file won't be visible if REG_PKG_POWER_SKU is invalid, so valid check 394 * for this register can be skipped. 395 * See xe_hwmon_power_is_visible. 396 */ 397 struct xe_reg reg = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, channel); 398 399 reg_val = xe_mmio_read32(mmio, reg); 400 } 401 402 reg_val = REG_FIELD_GET(PKG_TDP, reg_val); 403 *value = mul_u64_u32_shr(reg_val, SF_POWER, hwmon->scl_shift_power); 404 } 405 406 /* 407 * xe_hwmon_energy_get - Obtain energy value 408 * 409 * The underlying energy hardware register is 32-bits and is subject to 410 * overflow. How long before overflow? For example, with an example 411 * scaling bit shift of 14 bits (see register *PACKAGE_POWER_SKU_UNIT) and 412 * a power draw of 1000 watts, the 32-bit counter will overflow in 413 * approximately 4.36 minutes. 414 * 415 * Examples: 416 * 1 watt: (2^32 >> 14) / 1 W / (60 * 60 * 24) secs/day -> 3 days 417 * 1000 watts: (2^32 >> 14) / 1000 W / 60 secs/min -> 4.36 minutes 418 * 419 * The function significantly increases overflow duration (from 4.36 420 * minutes) by accumulating the energy register into a 'long' as allowed by 421 * the hwmon API. Using x86_64 128 bit arithmetic (see mul_u64_u32_shr()), 422 * a 'long' of 63 bits, SF_ENERGY of 1e6 (~20 bits) and 423 * hwmon->scl_shift_energy of 14 bits we have 57 (63 - 20 + 14) bits before 424 * energyN_input overflows. This at 1000 W is an overflow duration of 278 years. 425 */ 426 static void 427 xe_hwmon_energy_get(struct xe_hwmon *hwmon, int channel, long *energy) 428 { 429 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 430 struct xe_hwmon_energy_info *ei = &hwmon->ei[channel]; 431 u64 reg_val; 432 433 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, 434 channel)); 435 436 if (reg_val >= ei->reg_val_prev) 437 ei->accum_energy += reg_val - ei->reg_val_prev; 438 else 439 ei->accum_energy += UINT_MAX - ei->reg_val_prev + reg_val; 440 441 ei->reg_val_prev = reg_val; 442 443 *energy = mul_u64_u32_shr(ei->accum_energy, SF_ENERGY, 444 hwmon->scl_shift_energy); 445 } 446 447 static ssize_t 448 xe_hwmon_power_max_interval_show(struct device *dev, struct device_attribute *attr, 449 char *buf) 450 { 451 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 452 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 453 u32 x, y, x_w = 2; /* 2 bits */ 454 u64 r, tau4, out; 455 int channel = to_sensor_dev_attr(attr)->index; 456 u32 power_attr = PL1_HWMON_ATTR; 457 int ret = 0; 458 459 xe_pm_runtime_get(hwmon->xe); 460 461 mutex_lock(&hwmon->hwmon_lock); 462 463 if (hwmon->xe->info.has_mbx_power_limits) { 464 ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, (u32 *)&r); 465 if (ret) { 466 drm_err(&hwmon->xe->drm, 467 "power interval read fail, ch %d, attr %d, r 0%llx, ret %d\n", 468 channel, power_attr, r, ret); 469 r = 0; 470 } 471 } else { 472 r = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel)); 473 } 474 475 mutex_unlock(&hwmon->hwmon_lock); 476 477 xe_pm_runtime_put(hwmon->xe); 478 479 x = REG_FIELD_GET(PWR_LIM_TIME_X, r); 480 y = REG_FIELD_GET(PWR_LIM_TIME_Y, r); 481 482 /* 483 * tau = (1 + (x / 4)) * power(2,y), x = bits(23:22), y = bits(21:17) 484 * = (4 | x) << (y - 2) 485 * 486 * Here (y - 2) ensures a 1.x fixed point representation of 1.x 487 * As x is 2 bits so 1.x can be 1.0, 1.25, 1.50, 1.75 488 * 489 * As y can be < 2, we compute tau4 = (4 | x) << y 490 * and then add 2 when doing the final right shift to account for units 491 */ 492 tau4 = (u64)((1 << x_w) | x) << y; 493 494 /* val in hwmon interface units (millisec) */ 495 out = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 496 497 return sysfs_emit(buf, "%llu\n", out); 498 } 499 500 static ssize_t 501 xe_hwmon_power_max_interval_store(struct device *dev, struct device_attribute *attr, 502 const char *buf, size_t count) 503 { 504 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 505 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 506 u32 x, y, rxy, x_w = 2; /* 2 bits */ 507 u64 tau4, r, max_win; 508 unsigned long val; 509 int ret; 510 int channel = to_sensor_dev_attr(attr)->index; 511 u32 power_attr = PL1_HWMON_ATTR; 512 513 ret = kstrtoul(buf, 0, &val); 514 if (ret) 515 return ret; 516 517 /* 518 * Max HW supported tau in '(1 + (x / 4)) * power(2,y)' format, x = 0, y = 0x12. 519 * The hwmon->scl_shift_time default of 0xa results in a max tau of 256 seconds. 520 * 521 * The ideal scenario is for PKG_MAX_WIN to be read from the PKG_PWR_SKU register. 522 * However, it is observed that existing discrete GPUs does not provide correct 523 * PKG_MAX_WIN value, therefore a using default constant value. For future discrete GPUs 524 * this may get resolved, in which case PKG_MAX_WIN should be obtained from PKG_PWR_SKU. 525 */ 526 #define PKG_MAX_WIN_DEFAULT 0x12ull 527 528 /* 529 * val must be < max in hwmon interface units. The steps below are 530 * explained in xe_hwmon_power_max_interval_show() 531 */ 532 r = FIELD_PREP(PKG_MAX_WIN, PKG_MAX_WIN_DEFAULT); 533 x = REG_FIELD_GET(PKG_MAX_WIN_X, r); 534 y = REG_FIELD_GET(PKG_MAX_WIN_Y, r); 535 tau4 = (u64)((1 << x_w) | x) << y; 536 max_win = mul_u64_u32_shr(tau4, SF_TIME, hwmon->scl_shift_time + x_w); 537 538 if (val > max_win) { 539 drm_warn(&hwmon->xe->drm, "power_interval invalid val 0x%lx\n", val); 540 return -EINVAL; 541 } 542 543 /* val in hw units */ 544 val = DIV_ROUND_CLOSEST_ULL((u64)val << hwmon->scl_shift_time, SF_TIME) + 1; 545 546 /* 547 * Convert val to 1.x * power(2,y) 548 * y = ilog2(val) 549 * x = (val - (1 << y)) >> (y - 2) 550 */ 551 if (!val) { 552 y = 0; 553 x = 0; 554 } else { 555 y = ilog2(val); 556 x = (val - (1ul << y)) << x_w >> y; 557 } 558 559 rxy = REG_FIELD_PREP(PWR_LIM_TIME_X, x) | 560 REG_FIELD_PREP(PWR_LIM_TIME_Y, y); 561 562 xe_pm_runtime_get(hwmon->xe); 563 564 mutex_lock(&hwmon->hwmon_lock); 565 566 if (hwmon->xe->info.has_mbx_power_limits) { 567 ret = xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, (u32 *)&r); 568 r = (r & ~PWR_LIM_TIME) | rxy; 569 xe_hwmon_pcode_write_power_limit(hwmon, power_attr, channel, r); 570 } else { 571 r = xe_mmio_rmw32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, channel), 572 PWR_LIM_TIME, rxy); 573 } 574 575 mutex_unlock(&hwmon->hwmon_lock); 576 577 xe_pm_runtime_put(hwmon->xe); 578 579 return count; 580 } 581 582 /* PSYS PL1 */ 583 static SENSOR_DEVICE_ATTR(power1_max_interval, 0664, 584 xe_hwmon_power_max_interval_show, 585 xe_hwmon_power_max_interval_store, CHANNEL_CARD); 586 587 static SENSOR_DEVICE_ATTR(power2_max_interval, 0664, 588 xe_hwmon_power_max_interval_show, 589 xe_hwmon_power_max_interval_store, CHANNEL_PKG); 590 591 static struct attribute *hwmon_attributes[] = { 592 &sensor_dev_attr_power1_max_interval.dev_attr.attr, 593 &sensor_dev_attr_power2_max_interval.dev_attr.attr, 594 NULL 595 }; 596 597 static umode_t xe_hwmon_attributes_visible(struct kobject *kobj, 598 struct attribute *attr, int index) 599 { 600 struct device *dev = kobj_to_dev(kobj); 601 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 602 int ret = 0; 603 int channel = index ? CHANNEL_PKG : CHANNEL_CARD; 604 u32 power_attr = PL1_HWMON_ATTR; 605 u32 uval; 606 607 xe_pm_runtime_get(hwmon->xe); 608 609 if (hwmon->xe->info.has_mbx_power_limits) { 610 xe_hwmon_pcode_read_power_limit(hwmon, power_attr, channel, &uval); 611 ret = (uval & PWR_LIM_EN) ? attr->mode : 0; 612 } else { 613 ret = xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, 614 channel)) ? attr->mode : 0; 615 } 616 617 xe_pm_runtime_put(hwmon->xe); 618 619 return ret; 620 } 621 622 static const struct attribute_group hwmon_attrgroup = { 623 .attrs = hwmon_attributes, 624 .is_visible = xe_hwmon_attributes_visible, 625 }; 626 627 static const struct attribute_group *hwmon_groups[] = { 628 &hwmon_attrgroup, 629 NULL 630 }; 631 632 static const struct hwmon_channel_info * const hwmon_info[] = { 633 HWMON_CHANNEL_INFO(temp, HWMON_T_LABEL, HWMON_T_INPUT | HWMON_T_LABEL, 634 HWMON_T_INPUT | HWMON_T_LABEL), 635 HWMON_CHANNEL_INFO(power, HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL | HWMON_P_CRIT, 636 HWMON_P_MAX | HWMON_P_RATED_MAX | HWMON_P_LABEL), 637 HWMON_CHANNEL_INFO(curr, HWMON_C_LABEL, HWMON_C_CRIT | HWMON_C_LABEL), 638 HWMON_CHANNEL_INFO(in, HWMON_I_INPUT | HWMON_I_LABEL, HWMON_I_INPUT | HWMON_I_LABEL), 639 HWMON_CHANNEL_INFO(energy, HWMON_E_INPUT | HWMON_E_LABEL, HWMON_E_INPUT | HWMON_E_LABEL), 640 HWMON_CHANNEL_INFO(fan, HWMON_F_INPUT, HWMON_F_INPUT, HWMON_F_INPUT), 641 NULL 642 }; 643 644 /* I1 is exposed as power_crit or as curr_crit depending on bit 31 */ 645 static int xe_hwmon_pcode_read_i1(const struct xe_hwmon *hwmon, u32 *uval) 646 { 647 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 648 649 /* Avoid Illegal Subcommand error */ 650 if (hwmon->xe->info.platform == XE_DG2) 651 return -ENXIO; 652 653 return xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 654 POWER_SETUP_SUBCOMMAND_READ_I1, 0), 655 uval, NULL); 656 } 657 658 static int xe_hwmon_pcode_write_i1(const struct xe_hwmon *hwmon, u32 uval) 659 { 660 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 661 662 return xe_pcode_write(root_tile, PCODE_MBOX(PCODE_POWER_SETUP, 663 POWER_SETUP_SUBCOMMAND_WRITE_I1, 0), 664 (uval & POWER_SETUP_I1_DATA_MASK)); 665 } 666 667 static int xe_hwmon_pcode_read_fan_control(const struct xe_hwmon *hwmon, u32 subcmd, u32 *uval) 668 { 669 struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); 670 671 /* Platforms that don't return correct value */ 672 if (hwmon->xe->info.platform == XE_DG2 && subcmd == FSC_READ_NUM_FANS) { 673 *uval = 2; 674 return 0; 675 } 676 677 return xe_pcode_read(root_tile, PCODE_MBOX(FAN_SPEED_CONTROL, subcmd, 0), uval, NULL); 678 } 679 680 static int xe_hwmon_power_curr_crit_read(struct xe_hwmon *hwmon, int channel, 681 long *value, u32 scale_factor) 682 { 683 int ret; 684 u32 uval; 685 686 mutex_lock(&hwmon->hwmon_lock); 687 688 ret = xe_hwmon_pcode_read_i1(hwmon, &uval); 689 if (ret) 690 goto unlock; 691 692 *value = mul_u64_u32_shr(REG_FIELD_GET(POWER_SETUP_I1_DATA_MASK, uval), 693 scale_factor, POWER_SETUP_I1_SHIFT); 694 unlock: 695 mutex_unlock(&hwmon->hwmon_lock); 696 return ret; 697 } 698 699 static int xe_hwmon_power_curr_crit_write(struct xe_hwmon *hwmon, int channel, 700 long value, u32 scale_factor) 701 { 702 int ret; 703 u32 uval; 704 705 mutex_lock(&hwmon->hwmon_lock); 706 707 uval = DIV_ROUND_CLOSEST_ULL(value << POWER_SETUP_I1_SHIFT, scale_factor); 708 ret = xe_hwmon_pcode_write_i1(hwmon, uval); 709 710 mutex_unlock(&hwmon->hwmon_lock); 711 return ret; 712 } 713 714 static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *value) 715 { 716 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 717 u64 reg_val; 718 719 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, channel)); 720 /* HW register value in units of 2.5 millivolt */ 721 *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE); 722 } 723 724 static umode_t 725 xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 726 { 727 switch (attr) { 728 case hwmon_temp_input: 729 case hwmon_temp_label: 730 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_TEMP, channel)) ? 0444 : 0; 731 default: 732 return 0; 733 } 734 } 735 736 static int 737 xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 738 { 739 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 740 u64 reg_val; 741 742 switch (attr) { 743 case hwmon_temp_input: 744 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel)); 745 746 /* HW register value is in degrees Celsius, convert to millidegrees. */ 747 *val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE; 748 return 0; 749 default: 750 return -EOPNOTSUPP; 751 } 752 } 753 754 static umode_t 755 xe_hwmon_power_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 756 { 757 u32 uval; 758 759 switch (attr) { 760 case hwmon_power_max: 761 if (hwmon->xe->info.has_mbx_power_limits) { 762 xe_hwmon_pcode_read_power_limit(hwmon, attr, channel, &uval); 763 return (uval) ? 0664 : 0; 764 } else { 765 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, 766 channel)) ? 0664 : 0; 767 } 768 case hwmon_power_rated_max: 769 if (hwmon->xe->info.has_mbx_power_limits) 770 return 0; 771 else 772 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU, 773 channel)) ? 0444 : 0; 774 case hwmon_power_crit: 775 case hwmon_power_label: 776 if (channel == CHANNEL_CARD) { 777 xe_hwmon_pcode_read_i1(hwmon, &uval); 778 return (uval & POWER_SETUP_I1_WATTS) ? (attr == hwmon_power_label) ? 779 0444 : 0644 : 0; 780 } 781 break; 782 default: 783 return 0; 784 } 785 return 0; 786 } 787 788 static int 789 xe_hwmon_power_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 790 { 791 switch (attr) { 792 case hwmon_power_max: 793 xe_hwmon_power_max_read(hwmon, attr, channel, val); 794 return 0; 795 case hwmon_power_rated_max: 796 xe_hwmon_power_rated_max_read(hwmon, attr, channel, val); 797 return 0; 798 case hwmon_power_crit: 799 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_POWER); 800 default: 801 return -EOPNOTSUPP; 802 } 803 } 804 805 static int 806 xe_hwmon_power_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 807 { 808 switch (attr) { 809 case hwmon_power_max: 810 return xe_hwmon_power_max_write(hwmon, attr, channel, val); 811 case hwmon_power_crit: 812 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_POWER); 813 default: 814 return -EOPNOTSUPP; 815 } 816 } 817 818 static umode_t 819 xe_hwmon_curr_is_visible(const struct xe_hwmon *hwmon, u32 attr, int channel) 820 { 821 u32 uval; 822 823 /* hwmon sysfs attribute of current available only for package */ 824 if (channel != CHANNEL_PKG) 825 return 0; 826 827 switch (attr) { 828 case hwmon_curr_crit: 829 return (xe_hwmon_pcode_read_i1(hwmon, &uval) || 830 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0644; 831 case hwmon_curr_label: 832 return (xe_hwmon_pcode_read_i1(hwmon, &uval) || 833 (uval & POWER_SETUP_I1_WATTS)) ? 0 : 0444; 834 break; 835 default: 836 return 0; 837 } 838 return 0; 839 } 840 841 static int 842 xe_hwmon_curr_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 843 { 844 switch (attr) { 845 case hwmon_curr_crit: 846 return xe_hwmon_power_curr_crit_read(hwmon, channel, val, SF_CURR); 847 default: 848 return -EOPNOTSUPP; 849 } 850 } 851 852 static int 853 xe_hwmon_curr_write(struct xe_hwmon *hwmon, u32 attr, int channel, long val) 854 { 855 switch (attr) { 856 case hwmon_curr_crit: 857 return xe_hwmon_power_curr_crit_write(hwmon, channel, val, SF_CURR); 858 default: 859 return -EOPNOTSUPP; 860 } 861 } 862 863 static umode_t 864 xe_hwmon_in_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 865 { 866 switch (attr) { 867 case hwmon_in_input: 868 case hwmon_in_label: 869 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, 870 channel)) ? 0444 : 0; 871 default: 872 return 0; 873 } 874 } 875 876 static int 877 xe_hwmon_in_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 878 { 879 switch (attr) { 880 case hwmon_in_input: 881 xe_hwmon_get_voltage(hwmon, channel, val); 882 return 0; 883 default: 884 return -EOPNOTSUPP; 885 } 886 } 887 888 static umode_t 889 xe_hwmon_energy_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 890 { 891 switch (attr) { 892 case hwmon_energy_input: 893 case hwmon_energy_label: 894 return xe_reg_is_valid(xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, 895 channel)) ? 0444 : 0; 896 default: 897 return 0; 898 } 899 } 900 901 static int 902 xe_hwmon_energy_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 903 { 904 switch (attr) { 905 case hwmon_energy_input: 906 xe_hwmon_energy_get(hwmon, channel, val); 907 return 0; 908 default: 909 return -EOPNOTSUPP; 910 } 911 } 912 913 static umode_t 914 xe_hwmon_fan_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) 915 { 916 u32 uval; 917 918 if (!hwmon->xe->info.has_fan_control) 919 return 0; 920 921 switch (attr) { 922 case hwmon_fan_input: 923 if (xe_hwmon_pcode_read_fan_control(hwmon, FSC_READ_NUM_FANS, &uval)) 924 return 0; 925 926 return channel < uval ? 0444 : 0; 927 default: 928 return 0; 929 } 930 } 931 932 static int 933 xe_hwmon_fan_input_read(struct xe_hwmon *hwmon, int channel, long *val) 934 { 935 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 936 struct xe_hwmon_fan_info *fi = &hwmon->fi[channel]; 937 u64 rotations, time_now, time; 938 u32 reg_val; 939 int ret = 0; 940 941 mutex_lock(&hwmon->hwmon_lock); 942 943 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_FAN_SPEED, channel)); 944 time_now = get_jiffies_64(); 945 946 /* 947 * HW register value is accumulated count of pulses from PWM fan with the scale 948 * of 2 pulses per rotation. 949 */ 950 rotations = (reg_val - fi->reg_val_prev) / 2; 951 952 time = jiffies_delta_to_msecs(time_now - fi->time_prev); 953 if (unlikely(!time)) { 954 ret = -EAGAIN; 955 goto unlock; 956 } 957 958 /* 959 * Calculate fan speed in RPM by time averaging two subsequent readings in minutes. 960 * RPM = number of rotations * msecs per minute / time in msecs 961 */ 962 *val = DIV_ROUND_UP_ULL(rotations * (MSEC_PER_SEC * 60), time); 963 964 fi->reg_val_prev = reg_val; 965 fi->time_prev = time_now; 966 unlock: 967 mutex_unlock(&hwmon->hwmon_lock); 968 return ret; 969 } 970 971 static int 972 xe_hwmon_fan_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) 973 { 974 switch (attr) { 975 case hwmon_fan_input: 976 return xe_hwmon_fan_input_read(hwmon, channel, val); 977 default: 978 return -EOPNOTSUPP; 979 } 980 } 981 982 static umode_t 983 xe_hwmon_is_visible(const void *drvdata, enum hwmon_sensor_types type, 984 u32 attr, int channel) 985 { 986 struct xe_hwmon *hwmon = (struct xe_hwmon *)drvdata; 987 int ret; 988 989 xe_pm_runtime_get(hwmon->xe); 990 991 switch (type) { 992 case hwmon_temp: 993 ret = xe_hwmon_temp_is_visible(hwmon, attr, channel); 994 break; 995 case hwmon_power: 996 ret = xe_hwmon_power_is_visible(hwmon, attr, channel); 997 break; 998 case hwmon_curr: 999 ret = xe_hwmon_curr_is_visible(hwmon, attr, channel); 1000 break; 1001 case hwmon_in: 1002 ret = xe_hwmon_in_is_visible(hwmon, attr, channel); 1003 break; 1004 case hwmon_energy: 1005 ret = xe_hwmon_energy_is_visible(hwmon, attr, channel); 1006 break; 1007 case hwmon_fan: 1008 ret = xe_hwmon_fan_is_visible(hwmon, attr, channel); 1009 break; 1010 default: 1011 ret = 0; 1012 break; 1013 } 1014 1015 xe_pm_runtime_put(hwmon->xe); 1016 1017 return ret; 1018 } 1019 1020 static int 1021 xe_hwmon_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, 1022 int channel, long *val) 1023 { 1024 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 1025 int ret; 1026 1027 xe_pm_runtime_get(hwmon->xe); 1028 1029 switch (type) { 1030 case hwmon_temp: 1031 ret = xe_hwmon_temp_read(hwmon, attr, channel, val); 1032 break; 1033 case hwmon_power: 1034 ret = xe_hwmon_power_read(hwmon, attr, channel, val); 1035 break; 1036 case hwmon_curr: 1037 ret = xe_hwmon_curr_read(hwmon, attr, channel, val); 1038 break; 1039 case hwmon_in: 1040 ret = xe_hwmon_in_read(hwmon, attr, channel, val); 1041 break; 1042 case hwmon_energy: 1043 ret = xe_hwmon_energy_read(hwmon, attr, channel, val); 1044 break; 1045 case hwmon_fan: 1046 ret = xe_hwmon_fan_read(hwmon, attr, channel, val); 1047 break; 1048 default: 1049 ret = -EOPNOTSUPP; 1050 break; 1051 } 1052 1053 xe_pm_runtime_put(hwmon->xe); 1054 1055 return ret; 1056 } 1057 1058 static int 1059 xe_hwmon_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, 1060 int channel, long val) 1061 { 1062 struct xe_hwmon *hwmon = dev_get_drvdata(dev); 1063 int ret; 1064 1065 xe_pm_runtime_get(hwmon->xe); 1066 1067 switch (type) { 1068 case hwmon_power: 1069 ret = xe_hwmon_power_write(hwmon, attr, channel, val); 1070 break; 1071 case hwmon_curr: 1072 ret = xe_hwmon_curr_write(hwmon, attr, channel, val); 1073 break; 1074 default: 1075 ret = -EOPNOTSUPP; 1076 break; 1077 } 1078 1079 xe_pm_runtime_put(hwmon->xe); 1080 1081 return ret; 1082 } 1083 1084 static int xe_hwmon_read_label(struct device *dev, 1085 enum hwmon_sensor_types type, 1086 u32 attr, int channel, const char **str) 1087 { 1088 switch (type) { 1089 case hwmon_temp: 1090 if (channel == CHANNEL_PKG) 1091 *str = "pkg"; 1092 else if (channel == CHANNEL_VRAM) 1093 *str = "vram"; 1094 return 0; 1095 case hwmon_power: 1096 case hwmon_energy: 1097 case hwmon_curr: 1098 case hwmon_in: 1099 if (channel == CHANNEL_CARD) 1100 *str = "card"; 1101 else if (channel == CHANNEL_PKG) 1102 *str = "pkg"; 1103 return 0; 1104 default: 1105 return -EOPNOTSUPP; 1106 } 1107 } 1108 1109 static const struct hwmon_ops hwmon_ops = { 1110 .is_visible = xe_hwmon_is_visible, 1111 .read = xe_hwmon_read, 1112 .write = xe_hwmon_write, 1113 .read_string = xe_hwmon_read_label, 1114 }; 1115 1116 static const struct hwmon_chip_info hwmon_chip_info = { 1117 .ops = &hwmon_ops, 1118 .info = hwmon_info, 1119 }; 1120 1121 static void 1122 xe_hwmon_get_preregistration_info(struct xe_hwmon *hwmon) 1123 { 1124 struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); 1125 long energy, fan_speed; 1126 u64 val_sku_unit = 0; 1127 int channel; 1128 struct xe_reg pkg_power_sku_unit; 1129 1130 if (hwmon->xe->info.has_mbx_power_limits) { 1131 /* Check if card firmware support mailbox power limits commands. */ 1132 if (xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_CARD, 1133 &hwmon->pl1_on_boot[CHANNEL_CARD]) | 1134 xe_hwmon_pcode_read_power_limit(hwmon, PL1_HWMON_ATTR, CHANNEL_PKG, 1135 &hwmon->pl1_on_boot[CHANNEL_PKG])) { 1136 drm_warn(&hwmon->xe->drm, 1137 "Failed to read power limits, check card firmware !\n"); 1138 } else { 1139 drm_info(&hwmon->xe->drm, "Using mailbox commands for power limits\n"); 1140 /* Write default limits to read from pcode from now on. */ 1141 xe_hwmon_pcode_write_power_limit(hwmon, PL1_HWMON_ATTR, 1142 CHANNEL_CARD, 1143 hwmon->pl1_on_boot[CHANNEL_CARD]); 1144 xe_hwmon_pcode_write_power_limit(hwmon, PL1_HWMON_ATTR, 1145 CHANNEL_PKG, 1146 hwmon->pl1_on_boot[CHANNEL_PKG]); 1147 hwmon->scl_shift_power = PWR_UNIT; 1148 hwmon->scl_shift_energy = ENERGY_UNIT; 1149 hwmon->scl_shift_time = TIME_UNIT; 1150 hwmon->boot_power_limit_read = true; 1151 } 1152 } else { 1153 drm_info(&hwmon->xe->drm, "Using register for power limits\n"); 1154 /* 1155 * The contents of register PKG_POWER_SKU_UNIT do not change, 1156 * so read it once and store the shift values. 1157 */ 1158 pkg_power_sku_unit = xe_hwmon_get_reg(hwmon, REG_PKG_POWER_SKU_UNIT, 0); 1159 if (xe_reg_is_valid(pkg_power_sku_unit)) { 1160 val_sku_unit = xe_mmio_read32(mmio, pkg_power_sku_unit); 1161 hwmon->scl_shift_power = REG_FIELD_GET(PKG_PWR_UNIT, val_sku_unit); 1162 hwmon->scl_shift_energy = REG_FIELD_GET(PKG_ENERGY_UNIT, val_sku_unit); 1163 hwmon->scl_shift_time = REG_FIELD_GET(PKG_TIME_UNIT, val_sku_unit); 1164 } 1165 } 1166 /* 1167 * Initialize 'struct xe_hwmon_energy_info', i.e. set fields to the 1168 * first value of the energy register read 1169 */ 1170 for (channel = 0; channel < CHANNEL_MAX; channel++) 1171 if (xe_hwmon_is_visible(hwmon, hwmon_energy, hwmon_energy_input, channel)) 1172 xe_hwmon_energy_get(hwmon, channel, &energy); 1173 1174 /* Initialize 'struct xe_hwmon_fan_info' with initial fan register reading. */ 1175 for (channel = 0; channel < FAN_MAX; channel++) 1176 if (xe_hwmon_is_visible(hwmon, hwmon_fan, hwmon_fan_input, channel)) 1177 xe_hwmon_fan_input_read(hwmon, channel, &fan_speed); 1178 } 1179 1180 static void xe_hwmon_mutex_destroy(void *arg) 1181 { 1182 struct xe_hwmon *hwmon = arg; 1183 1184 mutex_destroy(&hwmon->hwmon_lock); 1185 } 1186 1187 int xe_hwmon_register(struct xe_device *xe) 1188 { 1189 struct device *dev = xe->drm.dev; 1190 struct xe_hwmon *hwmon; 1191 int ret; 1192 1193 /* hwmon is available only for dGfx */ 1194 if (!IS_DGFX(xe)) 1195 return 0; 1196 1197 /* hwmon is not available on VFs */ 1198 if (IS_SRIOV_VF(xe)) 1199 return 0; 1200 1201 hwmon = devm_kzalloc(dev, sizeof(*hwmon), GFP_KERNEL); 1202 if (!hwmon) 1203 return -ENOMEM; 1204 1205 mutex_init(&hwmon->hwmon_lock); 1206 ret = devm_add_action_or_reset(dev, xe_hwmon_mutex_destroy, hwmon); 1207 if (ret) 1208 return ret; 1209 1210 /* There's only one instance of hwmon per device */ 1211 hwmon->xe = xe; 1212 xe->hwmon = hwmon; 1213 1214 xe_hwmon_get_preregistration_info(hwmon); 1215 1216 drm_dbg(&xe->drm, "Register xe hwmon interface\n"); 1217 1218 /* hwmon_dev points to device hwmon<i> */ 1219 hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev, "xe", hwmon, 1220 &hwmon_chip_info, 1221 hwmon_groups); 1222 if (IS_ERR(hwmon->hwmon_dev)) { 1223 drm_err(&xe->drm, "Failed to register xe hwmon (%pe)\n", hwmon->hwmon_dev); 1224 xe->hwmon = NULL; 1225 return PTR_ERR(hwmon->hwmon_dev); 1226 } 1227 1228 return 0; 1229 } 1230 1231