1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_hw_engine.h" 7 8 #include <linux/nospec.h> 9 10 #include <drm/drm_managed.h> 11 #include <drm/drm_print.h> 12 #include <uapi/drm/xe_drm.h> 13 #include <generated/xe_wa_oob.h> 14 15 #include "regs/xe_engine_regs.h" 16 #include "regs/xe_gt_regs.h" 17 #include "regs/xe_irq_regs.h" 18 #include "xe_assert.h" 19 #include "xe_bo.h" 20 #include "xe_configfs.h" 21 #include "xe_device.h" 22 #include "xe_execlist.h" 23 #include "xe_force_wake.h" 24 #include "xe_gsc.h" 25 #include "xe_gt.h" 26 #include "xe_gt_ccs_mode.h" 27 #include "xe_gt_clock.h" 28 #include "xe_gt_printk.h" 29 #include "xe_gt_mcr.h" 30 #include "xe_gt_topology.h" 31 #include "xe_guc_capture.h" 32 #include "xe_hw_engine_group.h" 33 #include "xe_hw_fence.h" 34 #include "xe_irq.h" 35 #include "xe_lrc.h" 36 #include "xe_mmio.h" 37 #include "xe_reg_sr.h" 38 #include "xe_reg_whitelist.h" 39 #include "xe_rtp.h" 40 #include "xe_sched_job.h" 41 #include "xe_sriov.h" 42 #include "xe_tuning.h" 43 #include "xe_uc_fw.h" 44 #include "xe_wa.h" 45 46 #define MAX_MMIO_BASES 3 47 struct engine_info { 48 const char *name; 49 unsigned int class : 8; 50 unsigned int instance : 8; 51 unsigned int irq_offset : 8; 52 enum xe_force_wake_domains domain; 53 u32 mmio_base; 54 }; 55 56 static const struct engine_info engine_infos[] = { 57 [XE_HW_ENGINE_RCS0] = { 58 .name = "rcs0", 59 .class = XE_ENGINE_CLASS_RENDER, 60 .instance = 0, 61 .irq_offset = ilog2(INTR_RCS0), 62 .domain = XE_FW_RENDER, 63 .mmio_base = RENDER_RING_BASE, 64 }, 65 [XE_HW_ENGINE_BCS0] = { 66 .name = "bcs0", 67 .class = XE_ENGINE_CLASS_COPY, 68 .instance = 0, 69 .irq_offset = ilog2(INTR_BCS(0)), 70 .domain = XE_FW_GT, 71 .mmio_base = BLT_RING_BASE, 72 }, 73 [XE_HW_ENGINE_BCS1] = { 74 .name = "bcs1", 75 .class = XE_ENGINE_CLASS_COPY, 76 .instance = 1, 77 .irq_offset = ilog2(INTR_BCS(1)), 78 .domain = XE_FW_GT, 79 .mmio_base = XEHPC_BCS1_RING_BASE, 80 }, 81 [XE_HW_ENGINE_BCS2] = { 82 .name = "bcs2", 83 .class = XE_ENGINE_CLASS_COPY, 84 .instance = 2, 85 .irq_offset = ilog2(INTR_BCS(2)), 86 .domain = XE_FW_GT, 87 .mmio_base = XEHPC_BCS2_RING_BASE, 88 }, 89 [XE_HW_ENGINE_BCS3] = { 90 .name = "bcs3", 91 .class = XE_ENGINE_CLASS_COPY, 92 .instance = 3, 93 .irq_offset = ilog2(INTR_BCS(3)), 94 .domain = XE_FW_GT, 95 .mmio_base = XEHPC_BCS3_RING_BASE, 96 }, 97 [XE_HW_ENGINE_BCS4] = { 98 .name = "bcs4", 99 .class = XE_ENGINE_CLASS_COPY, 100 .instance = 4, 101 .irq_offset = ilog2(INTR_BCS(4)), 102 .domain = XE_FW_GT, 103 .mmio_base = XEHPC_BCS4_RING_BASE, 104 }, 105 [XE_HW_ENGINE_BCS5] = { 106 .name = "bcs5", 107 .class = XE_ENGINE_CLASS_COPY, 108 .instance = 5, 109 .irq_offset = ilog2(INTR_BCS(5)), 110 .domain = XE_FW_GT, 111 .mmio_base = XEHPC_BCS5_RING_BASE, 112 }, 113 [XE_HW_ENGINE_BCS6] = { 114 .name = "bcs6", 115 .class = XE_ENGINE_CLASS_COPY, 116 .instance = 6, 117 .irq_offset = ilog2(INTR_BCS(6)), 118 .domain = XE_FW_GT, 119 .mmio_base = XEHPC_BCS6_RING_BASE, 120 }, 121 [XE_HW_ENGINE_BCS7] = { 122 .name = "bcs7", 123 .class = XE_ENGINE_CLASS_COPY, 124 .irq_offset = ilog2(INTR_BCS(7)), 125 .instance = 7, 126 .domain = XE_FW_GT, 127 .mmio_base = XEHPC_BCS7_RING_BASE, 128 }, 129 [XE_HW_ENGINE_BCS8] = { 130 .name = "bcs8", 131 .class = XE_ENGINE_CLASS_COPY, 132 .instance = 8, 133 .irq_offset = ilog2(INTR_BCS8), 134 .domain = XE_FW_GT, 135 .mmio_base = XEHPC_BCS8_RING_BASE, 136 }, 137 138 [XE_HW_ENGINE_VCS0] = { 139 .name = "vcs0", 140 .class = XE_ENGINE_CLASS_VIDEO_DECODE, 141 .instance = 0, 142 .irq_offset = 32 + ilog2(INTR_VCS(0)), 143 .domain = XE_FW_MEDIA_VDBOX0, 144 .mmio_base = BSD_RING_BASE, 145 }, 146 [XE_HW_ENGINE_VCS1] = { 147 .name = "vcs1", 148 .class = XE_ENGINE_CLASS_VIDEO_DECODE, 149 .instance = 1, 150 .irq_offset = 32 + ilog2(INTR_VCS(1)), 151 .domain = XE_FW_MEDIA_VDBOX1, 152 .mmio_base = BSD2_RING_BASE, 153 }, 154 [XE_HW_ENGINE_VCS2] = { 155 .name = "vcs2", 156 .class = XE_ENGINE_CLASS_VIDEO_DECODE, 157 .instance = 2, 158 .irq_offset = 32 + ilog2(INTR_VCS(2)), 159 .domain = XE_FW_MEDIA_VDBOX2, 160 .mmio_base = BSD3_RING_BASE, 161 }, 162 [XE_HW_ENGINE_VCS3] = { 163 .name = "vcs3", 164 .class = XE_ENGINE_CLASS_VIDEO_DECODE, 165 .instance = 3, 166 .irq_offset = 32 + ilog2(INTR_VCS(3)), 167 .domain = XE_FW_MEDIA_VDBOX3, 168 .mmio_base = BSD4_RING_BASE, 169 }, 170 [XE_HW_ENGINE_VCS4] = { 171 .name = "vcs4", 172 .class = XE_ENGINE_CLASS_VIDEO_DECODE, 173 .instance = 4, 174 .irq_offset = 32 + ilog2(INTR_VCS(4)), 175 .domain = XE_FW_MEDIA_VDBOX4, 176 .mmio_base = XEHP_BSD5_RING_BASE, 177 }, 178 [XE_HW_ENGINE_VCS5] = { 179 .name = "vcs5", 180 .class = XE_ENGINE_CLASS_VIDEO_DECODE, 181 .instance = 5, 182 .irq_offset = 32 + ilog2(INTR_VCS(5)), 183 .domain = XE_FW_MEDIA_VDBOX5, 184 .mmio_base = XEHP_BSD6_RING_BASE, 185 }, 186 [XE_HW_ENGINE_VCS6] = { 187 .name = "vcs6", 188 .class = XE_ENGINE_CLASS_VIDEO_DECODE, 189 .instance = 6, 190 .irq_offset = 32 + ilog2(INTR_VCS(6)), 191 .domain = XE_FW_MEDIA_VDBOX6, 192 .mmio_base = XEHP_BSD7_RING_BASE, 193 }, 194 [XE_HW_ENGINE_VCS7] = { 195 .name = "vcs7", 196 .class = XE_ENGINE_CLASS_VIDEO_DECODE, 197 .instance = 7, 198 .irq_offset = 32 + ilog2(INTR_VCS(7)), 199 .domain = XE_FW_MEDIA_VDBOX7, 200 .mmio_base = XEHP_BSD8_RING_BASE, 201 }, 202 [XE_HW_ENGINE_VECS0] = { 203 .name = "vecs0", 204 .class = XE_ENGINE_CLASS_VIDEO_ENHANCE, 205 .instance = 0, 206 .irq_offset = 32 + ilog2(INTR_VECS(0)), 207 .domain = XE_FW_MEDIA_VEBOX0, 208 .mmio_base = VEBOX_RING_BASE, 209 }, 210 [XE_HW_ENGINE_VECS1] = { 211 .name = "vecs1", 212 .class = XE_ENGINE_CLASS_VIDEO_ENHANCE, 213 .instance = 1, 214 .irq_offset = 32 + ilog2(INTR_VECS(1)), 215 .domain = XE_FW_MEDIA_VEBOX1, 216 .mmio_base = VEBOX2_RING_BASE, 217 }, 218 [XE_HW_ENGINE_VECS2] = { 219 .name = "vecs2", 220 .class = XE_ENGINE_CLASS_VIDEO_ENHANCE, 221 .instance = 2, 222 .irq_offset = 32 + ilog2(INTR_VECS(2)), 223 .domain = XE_FW_MEDIA_VEBOX2, 224 .mmio_base = XEHP_VEBOX3_RING_BASE, 225 }, 226 [XE_HW_ENGINE_VECS3] = { 227 .name = "vecs3", 228 .class = XE_ENGINE_CLASS_VIDEO_ENHANCE, 229 .instance = 3, 230 .irq_offset = 32 + ilog2(INTR_VECS(3)), 231 .domain = XE_FW_MEDIA_VEBOX3, 232 .mmio_base = XEHP_VEBOX4_RING_BASE, 233 }, 234 [XE_HW_ENGINE_CCS0] = { 235 .name = "ccs0", 236 .class = XE_ENGINE_CLASS_COMPUTE, 237 .instance = 0, 238 .irq_offset = ilog2(INTR_CCS(0)), 239 .domain = XE_FW_RENDER, 240 .mmio_base = COMPUTE0_RING_BASE, 241 }, 242 [XE_HW_ENGINE_CCS1] = { 243 .name = "ccs1", 244 .class = XE_ENGINE_CLASS_COMPUTE, 245 .instance = 1, 246 .irq_offset = ilog2(INTR_CCS(1)), 247 .domain = XE_FW_RENDER, 248 .mmio_base = COMPUTE1_RING_BASE, 249 }, 250 [XE_HW_ENGINE_CCS2] = { 251 .name = "ccs2", 252 .class = XE_ENGINE_CLASS_COMPUTE, 253 .instance = 2, 254 .irq_offset = ilog2(INTR_CCS(2)), 255 .domain = XE_FW_RENDER, 256 .mmio_base = COMPUTE2_RING_BASE, 257 }, 258 [XE_HW_ENGINE_CCS3] = { 259 .name = "ccs3", 260 .class = XE_ENGINE_CLASS_COMPUTE, 261 .instance = 3, 262 .irq_offset = ilog2(INTR_CCS(3)), 263 .domain = XE_FW_RENDER, 264 .mmio_base = COMPUTE3_RING_BASE, 265 }, 266 [XE_HW_ENGINE_GSCCS0] = { 267 .name = "gsccs0", 268 .class = XE_ENGINE_CLASS_OTHER, 269 .instance = OTHER_GSC_INSTANCE, 270 .domain = XE_FW_GSC, 271 .mmio_base = GSCCS_RING_BASE, 272 }, 273 }; 274 275 static void hw_engine_fini(void *arg) 276 { 277 struct xe_hw_engine *hwe = arg; 278 279 if (hwe->exl_port) 280 xe_execlist_port_destroy(hwe->exl_port); 281 282 hwe->gt = NULL; 283 } 284 285 /** 286 * xe_hw_engine_mmio_read32() - Read engine register 287 * @hwe: engine 288 * @reg: register to read from 289 * 290 * This function will read from an engine specific register. 291 * Forcewake must be held by the caller. 292 * 293 * Return: value of the 32-bit register. 294 */ 295 u32 xe_hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg) 296 { 297 xe_gt_assert(hwe->gt, !(reg.addr & hwe->mmio_base)); 298 xe_force_wake_assert_held(gt_to_fw(hwe->gt), hwe->domain); 299 300 reg.addr += hwe->mmio_base; 301 302 return xe_mmio_read32(&hwe->gt->mmio, reg); 303 } 304 305 void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe) 306 { 307 xe_mmio_write32(&hwe->gt->mmio, RING_HWS_PGA(hwe->mmio_base), 308 xe_bo_ggtt_addr(hwe->hwsp)); 309 } 310 311 static bool xe_hw_engine_match_fixed_cslice_mode(const struct xe_device *xe, 312 const struct xe_gt *gt, 313 const struct xe_hw_engine *hwe) 314 { 315 /* 316 * Xe3p no longer supports load balance mode, so "fixed cslice" mode 317 * is automatic and no RCU_MODE programming is required. 318 */ 319 if (GRAPHICS_VER(gt_to_xe(gt)) >= 35) 320 return false; 321 322 return xe_gt_ccs_mode_enabled(gt) && 323 xe_rtp_match_first_render_or_compute(xe, gt, hwe); 324 } 325 326 static bool xe_rtp_cfeg_wmtp_disabled(const struct xe_device *xe, 327 const struct xe_gt *gt, 328 const struct xe_hw_engine *hwe) 329 { 330 if (GRAPHICS_VER(xe) < 20) 331 return false; 332 333 if (hwe->class != XE_ENGINE_CLASS_COMPUTE && 334 hwe->class != XE_ENGINE_CLASS_RENDER) 335 return false; 336 337 return xe_mmio_read32(&hwe->gt->mmio, XEHP_FUSE4) & CFEG_WMTP_DISABLE; 338 } 339 340 void 341 xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe) 342 { 343 struct xe_gt *gt = hwe->gt; 344 const u8 mocs_write_idx = gt->mocs.uc_index; 345 const u8 mocs_read_idx = gt->mocs.uc_index; 346 u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) | 347 REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx); 348 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 349 const struct xe_rtp_entry_sr lrc_setup[] = { 350 /* 351 * Some blitter commands do not have a field for MOCS, those 352 * commands will use MOCS index pointed by BLIT_CCTL. 353 * BLIT_CCTL registers are needed to be programmed to un-cached. 354 */ 355 { XE_RTP_NAME("BLIT_CCTL_default_MOCS"), 356 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274), 357 ENGINE_CLASS(COPY)), 358 XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0), 359 BLIT_CCTL_DST_MOCS_MASK | 360 BLIT_CCTL_SRC_MOCS_MASK, 361 blit_cctl_val, 362 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 363 }, 364 /* Disable WMTP if HW doesn't support it */ 365 { XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"), 366 XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)), 367 XE_RTP_ACTIONS(FIELD_SET(CS_CHICKEN1(0), 368 PREEMPT_GPGPU_LEVEL_MASK, 369 PREEMPT_GPGPU_THREAD_GROUP_LEVEL)), 370 XE_RTP_ENTRY_FLAG(FOREACH_ENGINE) 371 }, 372 }; 373 374 xe_rtp_process_to_sr(&ctx, lrc_setup, ARRAY_SIZE(lrc_setup), 375 &hwe->reg_lrc, true); 376 } 377 378 static void 379 hw_engine_setup_default_state(struct xe_hw_engine *hwe) 380 { 381 struct xe_gt *gt = hwe->gt; 382 struct xe_device *xe = gt_to_xe(gt); 383 /* 384 * RING_CMD_CCTL specifies the default MOCS entry that will be 385 * used by the command streamer when executing commands that 386 * don't have a way to explicitly specify a MOCS setting. 387 * The default should usually reference whichever MOCS entry 388 * corresponds to uncached behavior, although use of a WB cached 389 * entry is recommended by the spec in certain circumstances on 390 * specific platforms. 391 * Bspec: 72161 392 */ 393 const u8 mocs_write_idx = gt->mocs.uc_index; 394 const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) && 395 (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ? 396 gt->mocs.wb_index : gt->mocs.uc_index; 397 u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) | 398 REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx); 399 struct xe_rtp_process_ctx ctx = XE_RTP_PROCESS_CTX_INITIALIZER(hwe); 400 const struct xe_rtp_entry_sr engine_entries[] = { 401 { XE_RTP_NAME("RING_CMD_CCTL_default_MOCS"), 402 XE_RTP_RULES(FUNC(xe_rtp_match_always)), 403 XE_RTP_ACTIONS(FIELD_SET(RING_CMD_CCTL(0), 404 CMD_CCTL_WRITE_OVERRIDE_MASK | 405 CMD_CCTL_READ_OVERRIDE_MASK, 406 ring_cmd_cctl_val, 407 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 408 }, 409 { XE_RTP_NAME("Disable HW status page updates for interrupts"), 410 XE_RTP_RULES(FUNC(xe_rtp_match_always)), 411 XE_RTP_ACTIONS(SET(RING_HWSTAM(0), ~0x0, 412 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 413 }, 414 { XE_RTP_NAME("Disable engine 'legacy' mode"), 415 XE_RTP_RULES(FUNC(xe_rtp_match_always)), 416 XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_DISABLE_LEGACY_MODE, 417 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 418 }, 419 /* 420 * To allow the GSC engine to go idle on MTL we need to enable 421 * idle messaging and set the hysteresis value (we use 0xA=5us 422 * as recommended in spec). On platforms after MTL this is 423 * enabled by default. 424 */ 425 { XE_RTP_NAME("MTL GSCCS IDLE MSG enable"), 426 XE_RTP_RULES(MEDIA_VERSION(1300), ENGINE_CLASS(OTHER)), 427 XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0), 428 IDLE_MSG_DISABLE, 429 XE_RTP_ACTION_FLAG(ENGINE_BASE)), 430 FIELD_SET(RING_PWRCTX_MAXCNT(0), 431 IDLE_WAIT_TIME, 432 0xA, 433 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 434 }, 435 /* Enable Priority Mem Read */ 436 { XE_RTP_NAME("Priority_Mem_Read"), 437 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), 438 XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ, 439 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 440 }, 441 { XE_RTP_NAME("Enable CCS Engine(s)"), 442 XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1255, XE_RTP_END_VERSION_UNDEFINED), 443 FUNC(xe_rtp_match_first_render_or_compute)), 444 XE_RTP_ACTIONS(SET(RCU_MODE, RCU_MODE_CCS_ENABLE)) 445 }, 446 /* Use Fixed slice CCS mode */ 447 { XE_RTP_NAME("RCU_MODE_FIXED_SLICE_CCS_MODE"), 448 XE_RTP_RULES(FUNC(xe_hw_engine_match_fixed_cslice_mode)), 449 XE_RTP_ACTIONS(FIELD_SET(RCU_MODE, RCU_MODE_FIXED_SLICE_CCS_MODE, 450 RCU_MODE_FIXED_SLICE_CCS_MODE)) 451 }, 452 { XE_RTP_NAME("Enable MSI-X interrupt support"), 453 XE_RTP_RULES(FUNC(xe_rtp_match_has_msix)), 454 XE_RTP_ACTIONS(SET(GFX_MODE(0), GFX_MSIX_INTERRUPT_ENABLE, 455 XE_RTP_ACTION_FLAG(ENGINE_BASE))) 456 }, 457 }; 458 459 xe_rtp_process_to_sr(&ctx, engine_entries, ARRAY_SIZE(engine_entries), 460 &hwe->reg_sr, false); 461 } 462 463 static const struct engine_info *find_engine_info(enum xe_engine_class class, int instance) 464 { 465 const struct engine_info *info; 466 enum xe_hw_engine_id id; 467 468 for (id = 0; id < XE_NUM_HW_ENGINES; ++id) { 469 info = &engine_infos[id]; 470 if (info->class == class && info->instance == instance) 471 return info; 472 } 473 474 return NULL; 475 } 476 477 static u16 get_msix_irq_offset(struct xe_gt *gt, enum xe_engine_class class) 478 { 479 /* For MSI-X, hw engines report to offset of engine instance zero */ 480 const struct engine_info *info = find_engine_info(class, 0); 481 482 xe_gt_assert(gt, info); 483 484 return info ? info->irq_offset : 0; 485 } 486 487 static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe, 488 enum xe_hw_engine_id id) 489 { 490 const struct engine_info *info; 491 492 if (WARN_ON(id >= ARRAY_SIZE(engine_infos) || !engine_infos[id].name)) 493 return; 494 495 if (!(gt->info.engine_mask & BIT(id))) 496 return; 497 498 info = &engine_infos[id]; 499 500 xe_gt_assert(gt, !hwe->gt); 501 502 hwe->gt = gt; 503 hwe->class = info->class; 504 hwe->instance = info->instance; 505 hwe->mmio_base = info->mmio_base; 506 hwe->irq_offset = xe_device_has_msix(gt_to_xe(gt)) ? 507 get_msix_irq_offset(gt, info->class) : 508 info->irq_offset; 509 hwe->domain = info->domain; 510 hwe->name = info->name; 511 hwe->fence_irq = >->fence_irq[info->class]; 512 hwe->engine_id = id; 513 514 hwe->eclass = >->eclass[hwe->class]; 515 if (!hwe->eclass->sched_props.job_timeout_ms) { 516 hwe->eclass->sched_props.job_timeout_ms = 5 * 1000; 517 hwe->eclass->sched_props.job_timeout_min = XE_HW_ENGINE_JOB_TIMEOUT_MIN; 518 hwe->eclass->sched_props.job_timeout_max = XE_HW_ENGINE_JOB_TIMEOUT_MAX; 519 hwe->eclass->sched_props.timeslice_us = 1 * 1000; 520 hwe->eclass->sched_props.timeslice_min = XE_HW_ENGINE_TIMESLICE_MIN; 521 hwe->eclass->sched_props.timeslice_max = XE_HW_ENGINE_TIMESLICE_MAX; 522 hwe->eclass->sched_props.preempt_timeout_us = XE_HW_ENGINE_PREEMPT_TIMEOUT; 523 hwe->eclass->sched_props.preempt_timeout_min = XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN; 524 hwe->eclass->sched_props.preempt_timeout_max = XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX; 525 526 /* 527 * The GSC engine can accept submissions while the GSC shim is 528 * being reset, during which time the submission is stalled. In 529 * the worst case, the shim reset can take up to the maximum GSC 530 * command execution time (250ms), so the request start can be 531 * delayed by that much; the request itself can take that long 532 * without being preemptible, which means worst case it can 533 * theoretically take up to 500ms for a preemption to go through 534 * on the GSC engine. Adding to that an extra 100ms as a safety 535 * margin, we get a minimum recommended timeout of 600ms. 536 * The preempt_timeout value can't be tuned for OTHER_CLASS 537 * because the class is reserved for kernel usage, so we just 538 * need to make sure that the starting value is above that 539 * threshold; since our default value (640ms) is greater than 540 * 600ms, the only way we can go below is via a kconfig setting. 541 * If that happens, log it in dmesg and update the value. 542 */ 543 if (hwe->class == XE_ENGINE_CLASS_OTHER) { 544 const u32 min_preempt_timeout = 600 * 1000; 545 if (hwe->eclass->sched_props.preempt_timeout_us < min_preempt_timeout) { 546 hwe->eclass->sched_props.preempt_timeout_us = min_preempt_timeout; 547 xe_gt_notice(gt, "Increasing preempt_timeout for GSC to 600ms\n"); 548 } 549 } 550 551 /* Record default props */ 552 hwe->eclass->defaults = hwe->eclass->sched_props; 553 } 554 555 xe_reg_sr_init(&hwe->reg_sr, hwe->name, gt_to_xe(gt)); 556 xe_tuning_process_engine(hwe); 557 xe_wa_process_engine(hwe); 558 hw_engine_setup_default_state(hwe); 559 560 xe_reg_sr_init(&hwe->reg_whitelist, hwe->name, gt_to_xe(gt)); 561 xe_reg_whitelist_process_engine(hwe); 562 } 563 564 static void adjust_idledly(struct xe_hw_engine *hwe) 565 { 566 struct xe_gt *gt = hwe->gt; 567 u32 idledly, maxcnt; 568 u32 idledly_units_ps = 8 * gt->info.timestamp_base; 569 u32 maxcnt_units_ns = 640; 570 bool inhibit_switch = 0; 571 572 if (!IS_SRIOV_VF(gt_to_xe(hwe->gt)) && XE_GT_WA(gt, 16023105232)) { 573 idledly = xe_mmio_read32(>->mmio, RING_IDLEDLY(hwe->mmio_base)); 574 maxcnt = xe_mmio_read32(>->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base)); 575 576 inhibit_switch = idledly & INHIBIT_SWITCH_UNTIL_PREEMPTED; 577 idledly = REG_FIELD_GET(IDLE_DELAY, idledly); 578 idledly = DIV_ROUND_CLOSEST(idledly * idledly_units_ps, 1000); 579 maxcnt = REG_FIELD_GET(IDLE_WAIT_TIME, maxcnt); 580 maxcnt *= maxcnt_units_ns; 581 582 if (xe_gt_WARN_ON(gt, idledly >= maxcnt || inhibit_switch)) { 583 idledly = DIV_ROUND_CLOSEST(((maxcnt - 1) * 1000), 584 idledly_units_ps); 585 xe_mmio_write32(>->mmio, RING_IDLEDLY(hwe->mmio_base), idledly); 586 } 587 } 588 } 589 590 static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe, 591 enum xe_hw_engine_id id) 592 { 593 struct xe_device *xe = gt_to_xe(gt); 594 struct xe_tile *tile = gt_to_tile(gt); 595 int err; 596 597 xe_gt_assert(gt, id < ARRAY_SIZE(engine_infos) && engine_infos[id].name); 598 xe_gt_assert(gt, gt->info.engine_mask & BIT(id)); 599 600 xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); 601 602 hwe->hwsp = xe_managed_bo_create_pin_map(xe, tile, SZ_4K, 603 XE_BO_FLAG_VRAM_IF_DGFX(tile) | 604 XE_BO_FLAG_GGTT | 605 XE_BO_FLAG_GGTT_INVALIDATE); 606 if (IS_ERR(hwe->hwsp)) { 607 err = PTR_ERR(hwe->hwsp); 608 goto err_name; 609 } 610 611 if (!xe_device_uc_enabled(xe)) { 612 hwe->exl_port = xe_execlist_port_create(xe, hwe); 613 if (IS_ERR(hwe->exl_port)) { 614 err = PTR_ERR(hwe->exl_port); 615 goto err_hwsp; 616 } 617 } else { 618 /* GSCCS has a special interrupt for reset */ 619 if (hwe->class == XE_ENGINE_CLASS_OTHER) 620 hwe->irq_handler = xe_gsc_hwe_irq_handler; 621 622 if (!IS_SRIOV_VF(xe)) 623 xe_hw_engine_enable_ring(hwe); 624 } 625 626 /* We reserve the highest BCS instance for USM */ 627 if (xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY) 628 gt->usm.reserved_bcs_instance = hwe->instance; 629 630 /* Ensure IDLEDLY is lower than MAXCNT */ 631 adjust_idledly(hwe); 632 633 return devm_add_action_or_reset(xe->drm.dev, hw_engine_fini, hwe); 634 635 err_hwsp: 636 xe_bo_unpin_map_no_vm(hwe->hwsp); 637 err_name: 638 hwe->name = NULL; 639 640 return err; 641 } 642 643 static void hw_engine_setup_logical_mapping(struct xe_gt *gt) 644 { 645 int class; 646 647 /* FIXME: Doing a simple logical mapping that works for most hardware */ 648 for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) { 649 struct xe_hw_engine *hwe; 650 enum xe_hw_engine_id id; 651 int logical_instance = 0; 652 653 for_each_hw_engine(hwe, gt, id) 654 if (hwe->class == class) 655 hwe->logical_instance = logical_instance++; 656 } 657 } 658 659 static void read_media_fuses(struct xe_gt *gt) 660 { 661 struct xe_device *xe = gt_to_xe(gt); 662 u32 media_fuse; 663 u16 vdbox_mask; 664 u16 vebox_mask; 665 int i, j; 666 667 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 668 669 media_fuse = xe_mmio_read32(>->mmio, GT_VEBOX_VDBOX_DISABLE); 670 671 /* 672 * Pre-Xe_HP platforms had register bits representing absent engines, 673 * whereas Xe_HP and beyond have bits representing present engines. 674 * Invert the polarity on old platforms so that we can use common 675 * handling below. 676 */ 677 if (GRAPHICS_VERx100(xe) < 1250) 678 media_fuse = ~media_fuse; 679 680 vdbox_mask = REG_FIELD_GET(GT_VDBOX_DISABLE_MASK, media_fuse); 681 vebox_mask = REG_FIELD_GET(GT_VEBOX_DISABLE_MASK, media_fuse); 682 683 for (i = XE_HW_ENGINE_VCS0, j = 0; i <= XE_HW_ENGINE_VCS7; ++i, ++j) { 684 if (!(gt->info.engine_mask & BIT(i))) 685 continue; 686 687 if (!(BIT(j) & vdbox_mask)) { 688 gt->info.engine_mask &= ~BIT(i); 689 xe_gt_info(gt, "vcs%u fused off\n", j); 690 } 691 } 692 693 for (i = XE_HW_ENGINE_VECS0, j = 0; i <= XE_HW_ENGINE_VECS3; ++i, ++j) { 694 if (!(gt->info.engine_mask & BIT(i))) 695 continue; 696 697 if (!(BIT(j) & vebox_mask)) { 698 gt->info.engine_mask &= ~BIT(i); 699 xe_gt_info(gt, "vecs%u fused off\n", j); 700 } 701 } 702 } 703 704 static u32 infer_svccopy_from_meml3(struct xe_gt *gt) 705 { 706 u32 meml3 = REG_FIELD_GET(MEML3_EN_MASK, 707 xe_mmio_read32(>->mmio, MIRROR_FUSE3)); 708 u32 svccopy_mask = 0; 709 710 /* 711 * Each of the four meml3 bits determines the fusing of two service 712 * copy engines. 713 */ 714 for (int i = 0; i < 4; i++) 715 svccopy_mask |= (meml3 & BIT(i)) ? 0b11 << 2 * i : 0; 716 717 return svccopy_mask; 718 } 719 720 static u32 read_svccopy_fuses(struct xe_gt *gt) 721 { 722 return REG_FIELD_GET(FUSE_SERVICE_COPY_ENABLE_MASK, 723 xe_mmio_read32(>->mmio, SERVICE_COPY_ENABLE)); 724 } 725 726 static void read_copy_fuses(struct xe_gt *gt) 727 { 728 struct xe_device *xe = gt_to_xe(gt); 729 u32 bcs_mask; 730 731 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 732 733 if (GRAPHICS_VER(xe) >= 35) 734 bcs_mask = read_svccopy_fuses(gt); 735 else if (GRAPHICS_VERx100(xe) == 1260) 736 bcs_mask = infer_svccopy_from_meml3(gt); 737 else 738 return; 739 740 /* Only BCS1-BCS8 may be fused off */ 741 bcs_mask <<= XE_HW_ENGINE_BCS1; 742 for (int i = XE_HW_ENGINE_BCS1; i <= XE_HW_ENGINE_BCS8; ++i) { 743 if (!(gt->info.engine_mask & BIT(i))) 744 continue; 745 746 if (!(bcs_mask & BIT(i))) { 747 gt->info.engine_mask &= ~BIT(i); 748 xe_gt_info(gt, "bcs%u fused off\n", 749 i - XE_HW_ENGINE_BCS0); 750 } 751 } 752 } 753 754 static void read_compute_fuses_from_dss(struct xe_gt *gt) 755 { 756 /* 757 * CCS fusing based on DSS masks only applies to platforms that can 758 * have more than one CCS. 759 */ 760 if (hweight64(gt->info.engine_mask & 761 GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)) <= 1) 762 return; 763 764 /* 765 * CCS availability on Xe_HP is inferred from the presence of DSS in 766 * each quadrant. 767 */ 768 for (int i = XE_HW_ENGINE_CCS0, j = 0; i <= XE_HW_ENGINE_CCS3; ++i, ++j) { 769 if (!(gt->info.engine_mask & BIT(i))) 770 continue; 771 772 if (!xe_gt_topology_has_dss_in_quadrant(gt, j)) { 773 gt->info.engine_mask &= ~BIT(i); 774 xe_gt_info(gt, "ccs%u fused off\n", j); 775 } 776 } 777 } 778 779 static void read_compute_fuses_from_reg(struct xe_gt *gt) 780 { 781 u32 ccs_mask; 782 783 ccs_mask = xe_mmio_read32(>->mmio, XEHP_FUSE4); 784 ccs_mask = REG_FIELD_GET(CCS_EN_MASK, ccs_mask); 785 786 for (int i = XE_HW_ENGINE_CCS0, j = 0; i <= XE_HW_ENGINE_CCS3; ++i, ++j) { 787 if (!(gt->info.engine_mask & BIT(i))) 788 continue; 789 790 if ((ccs_mask & BIT(j)) == 0) { 791 gt->info.engine_mask &= ~BIT(i); 792 xe_gt_info(gt, "ccs%u fused off\n", j); 793 } 794 } 795 } 796 797 static void read_compute_fuses(struct xe_gt *gt) 798 { 799 if (GRAPHICS_VER(gt_to_xe(gt)) >= 20) 800 read_compute_fuses_from_reg(gt); 801 else 802 read_compute_fuses_from_dss(gt); 803 } 804 805 static void check_gsc_availability(struct xe_gt *gt) 806 { 807 if (!(gt->info.engine_mask & BIT(XE_HW_ENGINE_GSCCS0))) 808 return; 809 810 /* 811 * The GSCCS is only used to communicate with the GSC FW, so if we don't 812 * have the FW there is nothing we need the engine for and can therefore 813 * skip its initialization. 814 */ 815 if (!xe_uc_fw_is_available(>->uc.gsc.fw)) { 816 gt->info.engine_mask &= ~BIT(XE_HW_ENGINE_GSCCS0); 817 818 /* interrupts where previously enabled, so turn them off */ 819 xe_mmio_write32(>->mmio, GUNIT_GSC_INTR_ENABLE, 0); 820 xe_mmio_write32(>->mmio, GUNIT_GSC_INTR_MASK, ~0); 821 822 xe_gt_dbg(gt, "GSC FW not used, disabling gsccs\n"); 823 } 824 } 825 826 static void check_sw_disable(struct xe_gt *gt) 827 { 828 struct xe_device *xe = gt_to_xe(gt); 829 u64 sw_allowed = xe_configfs_get_engines_allowed(to_pci_dev(xe->drm.dev)); 830 enum xe_hw_engine_id id; 831 832 for (id = 0; id < XE_NUM_HW_ENGINES; ++id) { 833 if (!(gt->info.engine_mask & BIT(id))) 834 continue; 835 836 if (!(sw_allowed & BIT(id))) { 837 gt->info.engine_mask &= ~BIT(id); 838 xe_gt_info(gt, "%s disabled via configfs\n", 839 engine_infos[id].name); 840 } 841 } 842 } 843 844 int xe_hw_engines_init_early(struct xe_gt *gt) 845 { 846 int i; 847 848 read_media_fuses(gt); 849 read_copy_fuses(gt); 850 read_compute_fuses(gt); 851 check_gsc_availability(gt); 852 check_sw_disable(gt); 853 854 BUILD_BUG_ON(XE_HW_ENGINE_PREEMPT_TIMEOUT < XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN); 855 BUILD_BUG_ON(XE_HW_ENGINE_PREEMPT_TIMEOUT > XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX); 856 857 for (i = 0; i < ARRAY_SIZE(gt->hw_engines); i++) 858 hw_engine_init_early(gt, >->hw_engines[i], i); 859 860 return 0; 861 } 862 863 int xe_hw_engines_init(struct xe_gt *gt) 864 { 865 int err; 866 struct xe_hw_engine *hwe; 867 enum xe_hw_engine_id id; 868 869 for_each_hw_engine(hwe, gt, id) { 870 err = hw_engine_init(gt, hwe, id); 871 if (err) 872 return err; 873 } 874 875 hw_engine_setup_logical_mapping(gt); 876 err = xe_hw_engine_setup_groups(gt); 877 if (err) 878 return err; 879 880 return 0; 881 } 882 883 void xe_hw_engine_handle_irq(struct xe_hw_engine *hwe, u16 intr_vec) 884 { 885 wake_up_all(>_to_xe(hwe->gt)->ufence_wq); 886 887 if (hwe->irq_handler) 888 hwe->irq_handler(hwe, intr_vec); 889 890 if (intr_vec & GT_MI_USER_INTERRUPT) 891 xe_hw_fence_irq_run(hwe->fence_irq); 892 } 893 894 /** 895 * xe_hw_engine_snapshot_capture - Take a quick snapshot of the HW Engine. 896 * @hwe: Xe HW Engine. 897 * @q: The exec queue object. 898 * 899 * This can be printed out in a later stage like during dev_coredump 900 * analysis. 901 * 902 * Returns: a Xe HW Engine snapshot object that must be freed by the 903 * caller, using `xe_hw_engine_snapshot_free`. 904 */ 905 struct xe_hw_engine_snapshot * 906 xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe, struct xe_exec_queue *q) 907 { 908 struct xe_hw_engine_snapshot *snapshot; 909 struct __guc_capture_parsed_output *node; 910 911 if (!xe_hw_engine_is_valid(hwe)) 912 return NULL; 913 914 snapshot = kzalloc_obj(*snapshot, GFP_ATOMIC); 915 916 if (!snapshot) 917 return NULL; 918 919 snapshot->name = kstrdup(hwe->name, GFP_ATOMIC); 920 snapshot->hwe = hwe; 921 snapshot->logical_instance = hwe->logical_instance; 922 snapshot->forcewake.domain = hwe->domain; 923 snapshot->forcewake.ref = xe_force_wake_ref(gt_to_fw(hwe->gt), 924 hwe->domain); 925 snapshot->mmio_base = hwe->mmio_base; 926 snapshot->kernel_reserved = xe_hw_engine_is_reserved(hwe); 927 928 /* no more VF accessible data below this point */ 929 if (IS_SRIOV_VF(gt_to_xe(hwe->gt))) 930 return snapshot; 931 932 if (q) { 933 /* If got guc capture, set source to GuC */ 934 node = xe_guc_capture_get_matching_and_lock(q); 935 if (node) { 936 struct xe_device *xe = gt_to_xe(hwe->gt); 937 struct xe_devcoredump *coredump = &xe->devcoredump; 938 939 coredump->snapshot.matched_node = node; 940 xe_gt_dbg(hwe->gt, "Found and locked GuC-err-capture node"); 941 return snapshot; 942 } 943 } 944 945 /* otherwise, do manual capture */ 946 xe_engine_manual_capture(hwe, snapshot); 947 xe_gt_dbg(hwe->gt, "Proceeding with manual engine snapshot"); 948 949 return snapshot; 950 } 951 952 /** 953 * xe_hw_engine_snapshot_free - Free all allocated objects for a given snapshot. 954 * @snapshot: Xe HW Engine snapshot object. 955 * 956 * This function free all the memory that needed to be allocated at capture 957 * time. 958 */ 959 void xe_hw_engine_snapshot_free(struct xe_hw_engine_snapshot *snapshot) 960 { 961 struct xe_gt *gt; 962 if (!snapshot) 963 return; 964 965 gt = snapshot->hwe->gt; 966 /* 967 * xe_guc_capture_put_matched_nodes is called here and from 968 * xe_devcoredump_snapshot_free, to cover the 2 calling paths 969 * of hw_engines - debugfs and devcoredump free. 970 */ 971 xe_guc_capture_put_matched_nodes(>->uc.guc); 972 973 kfree(snapshot->name); 974 kfree(snapshot); 975 } 976 977 /** 978 * xe_hw_engine_print - Xe HW Engine Print. 979 * @hwe: Hardware Engine. 980 * @p: drm_printer. 981 * 982 * This function quickly capture a snapshot and immediately print it out. 983 */ 984 void xe_hw_engine_print(struct xe_hw_engine *hwe, struct drm_printer *p) 985 { 986 struct xe_hw_engine_snapshot *snapshot; 987 988 snapshot = xe_hw_engine_snapshot_capture(hwe, NULL); 989 xe_engine_snapshot_print(snapshot, p); 990 xe_hw_engine_snapshot_free(snapshot); 991 } 992 993 u32 xe_hw_engine_mask_per_class(struct xe_gt *gt, 994 enum xe_engine_class engine_class) 995 { 996 u32 mask = 0; 997 enum xe_hw_engine_id id; 998 999 for (id = 0; id < XE_NUM_HW_ENGINES; ++id) { 1000 if (engine_infos[id].class == engine_class && 1001 gt->info.engine_mask & BIT(id)) 1002 mask |= BIT(engine_infos[id].instance); 1003 } 1004 return mask; 1005 } 1006 1007 bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe) 1008 { 1009 struct xe_gt *gt = hwe->gt; 1010 struct xe_device *xe = gt_to_xe(gt); 1011 1012 if (xe_device_is_admin_only(xe)) 1013 return true; 1014 1015 if (hwe->class == XE_ENGINE_CLASS_OTHER) 1016 return true; 1017 1018 /* Check for engines disabled by ccs_mode setting */ 1019 if (xe_gt_ccs_mode_enabled(gt) && 1020 hwe->class == XE_ENGINE_CLASS_COMPUTE && 1021 hwe->logical_instance >= gt->ccs_mode) 1022 return true; 1023 1024 return xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY && 1025 hwe->instance == gt->usm.reserved_bcs_instance; 1026 } 1027 1028 const char *xe_hw_engine_class_to_str(enum xe_engine_class class) 1029 { 1030 switch (class) { 1031 case XE_ENGINE_CLASS_RENDER: 1032 return "rcs"; 1033 case XE_ENGINE_CLASS_VIDEO_DECODE: 1034 return "vcs"; 1035 case XE_ENGINE_CLASS_VIDEO_ENHANCE: 1036 return "vecs"; 1037 case XE_ENGINE_CLASS_COPY: 1038 return "bcs"; 1039 case XE_ENGINE_CLASS_OTHER: 1040 return "other"; 1041 case XE_ENGINE_CLASS_COMPUTE: 1042 return "ccs"; 1043 case XE_ENGINE_CLASS_MAX: 1044 break; 1045 } 1046 1047 return NULL; 1048 } 1049 1050 u64 xe_hw_engine_read_timestamp(struct xe_hw_engine *hwe) 1051 { 1052 return xe_mmio_read64_2x32(&hwe->gt->mmio, RING_TIMESTAMP(hwe->mmio_base)); 1053 } 1054 1055 enum xe_force_wake_domains xe_hw_engine_to_fw_domain(struct xe_hw_engine *hwe) 1056 { 1057 return engine_infos[hwe->engine_id].domain; 1058 } 1059 1060 static const enum xe_engine_class user_to_xe_engine_class[] = { 1061 [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, 1062 [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, 1063 [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, 1064 [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, 1065 [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, 1066 }; 1067 1068 /** 1069 * xe_hw_engine_lookup() - Lookup hardware engine for class:instance 1070 * @xe: xe device 1071 * @eci: engine class and instance 1072 * 1073 * This function will find a hardware engine for given engine 1074 * class and instance. 1075 * 1076 * Return: If found xe_hw_engine pointer, NULL otherwise. 1077 */ 1078 struct xe_hw_engine * 1079 xe_hw_engine_lookup(struct xe_device *xe, 1080 struct drm_xe_engine_class_instance eci) 1081 { 1082 struct xe_gt *gt = xe_device_get_gt(xe, eci.gt_id); 1083 unsigned int idx; 1084 1085 if (eci.engine_class >= ARRAY_SIZE(user_to_xe_engine_class)) 1086 return NULL; 1087 1088 if (!gt) 1089 return NULL; 1090 1091 idx = array_index_nospec(eci.engine_class, 1092 ARRAY_SIZE(user_to_xe_engine_class)); 1093 1094 return xe_gt_hw_engine(xe_device_get_gt(xe, eci.gt_id), 1095 user_to_xe_engine_class[idx], 1096 eci.engine_instance, true); 1097 } 1098