xref: /linux/drivers/gpu/drm/xe/xe_guc_submit.c (revision f12b363887c706c40611fba645265527a8415832)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #include "xe_guc_submit.h"
7 
8 #include <linux/bitfield.h>
9 #include <linux/bitmap.h>
10 #include <linux/circ_buf.h>
11 #include <linux/delay.h>
12 #include <linux/dma-fence-array.h>
13 #include <linux/math64.h>
14 
15 #include <drm/drm_managed.h>
16 
17 #include "abi/guc_actions_abi.h"
18 #include "abi/guc_klvs_abi.h"
19 #include "regs/xe_lrc_layout.h"
20 #include "xe_assert.h"
21 #include "xe_devcoredump.h"
22 #include "xe_device.h"
23 #include "xe_exec_queue.h"
24 #include "xe_force_wake.h"
25 #include "xe_gpu_scheduler.h"
26 #include "xe_gt.h"
27 #include "xe_gt_clock.h"
28 #include "xe_gt_printk.h"
29 #include "xe_guc.h"
30 #include "xe_guc_ct.h"
31 #include "xe_guc_exec_queue_types.h"
32 #include "xe_guc_id_mgr.h"
33 #include "xe_guc_submit_types.h"
34 #include "xe_hw_engine.h"
35 #include "xe_hw_fence.h"
36 #include "xe_lrc.h"
37 #include "xe_macros.h"
38 #include "xe_map.h"
39 #include "xe_mocs.h"
40 #include "xe_pm.h"
41 #include "xe_ring_ops_types.h"
42 #include "xe_sched_job.h"
43 #include "xe_trace.h"
44 #include "xe_vm.h"
45 
46 static struct xe_guc *
47 exec_queue_to_guc(struct xe_exec_queue *q)
48 {
49 	return &q->gt->uc.guc;
50 }
51 
52 /*
53  * Helpers for engine state, using an atomic as some of the bits can transition
54  * as the same time (e.g. a suspend can be happning at the same time as schedule
55  * engine done being processed).
56  */
57 #define EXEC_QUEUE_STATE_REGISTERED		(1 << 0)
58 #define EXEC_QUEUE_STATE_ENABLED		(1 << 1)
59 #define EXEC_QUEUE_STATE_PENDING_ENABLE		(1 << 2)
60 #define EXEC_QUEUE_STATE_PENDING_DISABLE	(1 << 3)
61 #define EXEC_QUEUE_STATE_DESTROYED		(1 << 4)
62 #define EXEC_QUEUE_STATE_SUSPENDED		(1 << 5)
63 #define EXEC_QUEUE_STATE_RESET			(1 << 6)
64 #define EXEC_QUEUE_STATE_KILLED			(1 << 7)
65 #define EXEC_QUEUE_STATE_WEDGED			(1 << 8)
66 #define EXEC_QUEUE_STATE_BANNED			(1 << 9)
67 #define EXEC_QUEUE_STATE_CHECK_TIMEOUT		(1 << 10)
68 #define EXEC_QUEUE_STATE_EXTRA_REF		(1 << 11)
69 
70 static bool exec_queue_registered(struct xe_exec_queue *q)
71 {
72 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_REGISTERED;
73 }
74 
75 static void set_exec_queue_registered(struct xe_exec_queue *q)
76 {
77 	atomic_or(EXEC_QUEUE_STATE_REGISTERED, &q->guc->state);
78 }
79 
80 static void clear_exec_queue_registered(struct xe_exec_queue *q)
81 {
82 	atomic_and(~EXEC_QUEUE_STATE_REGISTERED, &q->guc->state);
83 }
84 
85 static bool exec_queue_enabled(struct xe_exec_queue *q)
86 {
87 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_ENABLED;
88 }
89 
90 static void set_exec_queue_enabled(struct xe_exec_queue *q)
91 {
92 	atomic_or(EXEC_QUEUE_STATE_ENABLED, &q->guc->state);
93 }
94 
95 static void clear_exec_queue_enabled(struct xe_exec_queue *q)
96 {
97 	atomic_and(~EXEC_QUEUE_STATE_ENABLED, &q->guc->state);
98 }
99 
100 static bool exec_queue_pending_enable(struct xe_exec_queue *q)
101 {
102 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_ENABLE;
103 }
104 
105 static void set_exec_queue_pending_enable(struct xe_exec_queue *q)
106 {
107 	atomic_or(EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state);
108 }
109 
110 static void clear_exec_queue_pending_enable(struct xe_exec_queue *q)
111 {
112 	atomic_and(~EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state);
113 }
114 
115 static bool exec_queue_pending_disable(struct xe_exec_queue *q)
116 {
117 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_DISABLE;
118 }
119 
120 static void set_exec_queue_pending_disable(struct xe_exec_queue *q)
121 {
122 	atomic_or(EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state);
123 }
124 
125 static void clear_exec_queue_pending_disable(struct xe_exec_queue *q)
126 {
127 	atomic_and(~EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state);
128 }
129 
130 static bool exec_queue_destroyed(struct xe_exec_queue *q)
131 {
132 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_DESTROYED;
133 }
134 
135 static void set_exec_queue_destroyed(struct xe_exec_queue *q)
136 {
137 	atomic_or(EXEC_QUEUE_STATE_DESTROYED, &q->guc->state);
138 }
139 
140 static bool exec_queue_banned(struct xe_exec_queue *q)
141 {
142 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_BANNED;
143 }
144 
145 static void set_exec_queue_banned(struct xe_exec_queue *q)
146 {
147 	atomic_or(EXEC_QUEUE_STATE_BANNED, &q->guc->state);
148 }
149 
150 static bool exec_queue_suspended(struct xe_exec_queue *q)
151 {
152 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_SUSPENDED;
153 }
154 
155 static void set_exec_queue_suspended(struct xe_exec_queue *q)
156 {
157 	atomic_or(EXEC_QUEUE_STATE_SUSPENDED, &q->guc->state);
158 }
159 
160 static void clear_exec_queue_suspended(struct xe_exec_queue *q)
161 {
162 	atomic_and(~EXEC_QUEUE_STATE_SUSPENDED, &q->guc->state);
163 }
164 
165 static bool exec_queue_reset(struct xe_exec_queue *q)
166 {
167 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_RESET;
168 }
169 
170 static void set_exec_queue_reset(struct xe_exec_queue *q)
171 {
172 	atomic_or(EXEC_QUEUE_STATE_RESET, &q->guc->state);
173 }
174 
175 static bool exec_queue_killed(struct xe_exec_queue *q)
176 {
177 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_KILLED;
178 }
179 
180 static void set_exec_queue_killed(struct xe_exec_queue *q)
181 {
182 	atomic_or(EXEC_QUEUE_STATE_KILLED, &q->guc->state);
183 }
184 
185 static bool exec_queue_wedged(struct xe_exec_queue *q)
186 {
187 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_WEDGED;
188 }
189 
190 static void set_exec_queue_wedged(struct xe_exec_queue *q)
191 {
192 	atomic_or(EXEC_QUEUE_STATE_WEDGED, &q->guc->state);
193 }
194 
195 static bool exec_queue_check_timeout(struct xe_exec_queue *q)
196 {
197 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_CHECK_TIMEOUT;
198 }
199 
200 static void set_exec_queue_check_timeout(struct xe_exec_queue *q)
201 {
202 	atomic_or(EXEC_QUEUE_STATE_CHECK_TIMEOUT, &q->guc->state);
203 }
204 
205 static void clear_exec_queue_check_timeout(struct xe_exec_queue *q)
206 {
207 	atomic_and(~EXEC_QUEUE_STATE_CHECK_TIMEOUT, &q->guc->state);
208 }
209 
210 static bool exec_queue_extra_ref(struct xe_exec_queue *q)
211 {
212 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_EXTRA_REF;
213 }
214 
215 static void set_exec_queue_extra_ref(struct xe_exec_queue *q)
216 {
217 	atomic_or(EXEC_QUEUE_STATE_EXTRA_REF, &q->guc->state);
218 }
219 
220 static bool exec_queue_killed_or_banned_or_wedged(struct xe_exec_queue *q)
221 {
222 	return (atomic_read(&q->guc->state) &
223 		(EXEC_QUEUE_STATE_WEDGED | EXEC_QUEUE_STATE_KILLED |
224 		 EXEC_QUEUE_STATE_BANNED));
225 }
226 
227 static void guc_submit_fini(struct drm_device *drm, void *arg)
228 {
229 	struct xe_guc *guc = arg;
230 
231 	xa_destroy(&guc->submission_state.exec_queue_lookup);
232 }
233 
234 static void guc_submit_wedged_fini(void *arg)
235 {
236 	struct xe_guc *guc = arg;
237 	struct xe_exec_queue *q;
238 	unsigned long index;
239 
240 	mutex_lock(&guc->submission_state.lock);
241 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) {
242 		if (exec_queue_wedged(q)) {
243 			mutex_unlock(&guc->submission_state.lock);
244 			xe_exec_queue_put(q);
245 			mutex_lock(&guc->submission_state.lock);
246 		}
247 	}
248 	mutex_unlock(&guc->submission_state.lock);
249 }
250 
251 static const struct xe_exec_queue_ops guc_exec_queue_ops;
252 
253 static void primelockdep(struct xe_guc *guc)
254 {
255 	if (!IS_ENABLED(CONFIG_LOCKDEP))
256 		return;
257 
258 	fs_reclaim_acquire(GFP_KERNEL);
259 
260 	mutex_lock(&guc->submission_state.lock);
261 	mutex_unlock(&guc->submission_state.lock);
262 
263 	fs_reclaim_release(GFP_KERNEL);
264 }
265 
266 /**
267  * xe_guc_submit_init() - Initialize GuC submission.
268  * @guc: the &xe_guc to initialize
269  * @num_ids: number of GuC context IDs to use
270  *
271  * The bare-metal or PF driver can pass ~0 as &num_ids to indicate that all
272  * GuC context IDs supported by the GuC firmware should be used for submission.
273  *
274  * Only VF drivers will have to provide explicit number of GuC context IDs
275  * that they can use for submission.
276  *
277  * Return: 0 on success or a negative error code on failure.
278  */
279 int xe_guc_submit_init(struct xe_guc *guc, unsigned int num_ids)
280 {
281 	struct xe_device *xe = guc_to_xe(guc);
282 	struct xe_gt *gt = guc_to_gt(guc);
283 	int err;
284 
285 	err = drmm_mutex_init(&xe->drm, &guc->submission_state.lock);
286 	if (err)
287 		return err;
288 
289 	err = xe_guc_id_mgr_init(&guc->submission_state.idm, num_ids);
290 	if (err)
291 		return err;
292 
293 	gt->exec_queue_ops = &guc_exec_queue_ops;
294 
295 	xa_init(&guc->submission_state.exec_queue_lookup);
296 
297 	init_waitqueue_head(&guc->submission_state.fini_wq);
298 
299 	primelockdep(guc);
300 
301 	return drmm_add_action_or_reset(&xe->drm, guc_submit_fini, guc);
302 }
303 
304 static void __release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q, u32 xa_count)
305 {
306 	int i;
307 
308 	lockdep_assert_held(&guc->submission_state.lock);
309 
310 	for (i = 0; i < xa_count; ++i)
311 		xa_erase(&guc->submission_state.exec_queue_lookup, q->guc->id + i);
312 
313 	xe_guc_id_mgr_release_locked(&guc->submission_state.idm,
314 				     q->guc->id, q->width);
315 
316 	if (xa_empty(&guc->submission_state.exec_queue_lookup))
317 		wake_up(&guc->submission_state.fini_wq);
318 }
319 
320 static int alloc_guc_id(struct xe_guc *guc, struct xe_exec_queue *q)
321 {
322 	int ret;
323 	int i;
324 
325 	/*
326 	 * Must use GFP_NOWAIT as this lock is in the dma fence signalling path,
327 	 * worse case user gets -ENOMEM on engine create and has to try again.
328 	 *
329 	 * FIXME: Have caller pre-alloc or post-alloc /w GFP_KERNEL to prevent
330 	 * failure.
331 	 */
332 	lockdep_assert_held(&guc->submission_state.lock);
333 
334 	ret = xe_guc_id_mgr_reserve_locked(&guc->submission_state.idm,
335 					   q->width);
336 	if (ret < 0)
337 		return ret;
338 
339 	q->guc->id = ret;
340 
341 	for (i = 0; i < q->width; ++i) {
342 		ret = xa_err(xa_store(&guc->submission_state.exec_queue_lookup,
343 				      q->guc->id + i, q, GFP_NOWAIT));
344 		if (ret)
345 			goto err_release;
346 	}
347 
348 	return 0;
349 
350 err_release:
351 	__release_guc_id(guc, q, i);
352 
353 	return ret;
354 }
355 
356 static void release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q)
357 {
358 	mutex_lock(&guc->submission_state.lock);
359 	__release_guc_id(guc, q, q->width);
360 	mutex_unlock(&guc->submission_state.lock);
361 }
362 
363 struct exec_queue_policy {
364 	u32 count;
365 	struct guc_update_exec_queue_policy h2g;
366 };
367 
368 static u32 __guc_exec_queue_policy_action_size(struct exec_queue_policy *policy)
369 {
370 	size_t bytes = sizeof(policy->h2g.header) +
371 		       (sizeof(policy->h2g.klv[0]) * policy->count);
372 
373 	return bytes / sizeof(u32);
374 }
375 
376 static void __guc_exec_queue_policy_start_klv(struct exec_queue_policy *policy,
377 					      u16 guc_id)
378 {
379 	policy->h2g.header.action =
380 		XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES;
381 	policy->h2g.header.guc_id = guc_id;
382 	policy->count = 0;
383 }
384 
385 #define MAKE_EXEC_QUEUE_POLICY_ADD(func, id) \
386 static void __guc_exec_queue_policy_add_##func(struct exec_queue_policy *policy, \
387 					   u32 data) \
388 { \
389 	XE_WARN_ON(policy->count >= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \
390 \
391 	policy->h2g.klv[policy->count].kl = \
392 		FIELD_PREP(GUC_KLV_0_KEY, \
393 			   GUC_CONTEXT_POLICIES_KLV_ID_##id) | \
394 		FIELD_PREP(GUC_KLV_0_LEN, 1); \
395 	policy->h2g.klv[policy->count].value = data; \
396 	policy->count++; \
397 }
398 
399 MAKE_EXEC_QUEUE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM)
400 MAKE_EXEC_QUEUE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT)
401 MAKE_EXEC_QUEUE_POLICY_ADD(priority, SCHEDULING_PRIORITY)
402 #undef MAKE_EXEC_QUEUE_POLICY_ADD
403 
404 static const int xe_exec_queue_prio_to_guc[] = {
405 	[XE_EXEC_QUEUE_PRIORITY_LOW] = GUC_CLIENT_PRIORITY_NORMAL,
406 	[XE_EXEC_QUEUE_PRIORITY_NORMAL] = GUC_CLIENT_PRIORITY_KMD_NORMAL,
407 	[XE_EXEC_QUEUE_PRIORITY_HIGH] = GUC_CLIENT_PRIORITY_HIGH,
408 	[XE_EXEC_QUEUE_PRIORITY_KERNEL] = GUC_CLIENT_PRIORITY_KMD_HIGH,
409 };
410 
411 static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q)
412 {
413 	struct exec_queue_policy policy;
414 	struct xe_device *xe = guc_to_xe(guc);
415 	enum xe_exec_queue_priority prio = q->sched_props.priority;
416 	u32 timeslice_us = q->sched_props.timeslice_us;
417 	u32 preempt_timeout_us = q->sched_props.preempt_timeout_us;
418 
419 	xe_assert(xe, exec_queue_registered(q));
420 
421 	__guc_exec_queue_policy_start_klv(&policy, q->guc->id);
422 	__guc_exec_queue_policy_add_priority(&policy, xe_exec_queue_prio_to_guc[prio]);
423 	__guc_exec_queue_policy_add_execution_quantum(&policy, timeslice_us);
424 	__guc_exec_queue_policy_add_preemption_timeout(&policy, preempt_timeout_us);
425 
426 	xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g,
427 		       __guc_exec_queue_policy_action_size(&policy), 0, 0);
428 }
429 
430 static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue *q)
431 {
432 	struct exec_queue_policy policy;
433 
434 	__guc_exec_queue_policy_start_klv(&policy, q->guc->id);
435 	__guc_exec_queue_policy_add_preemption_timeout(&policy, 1);
436 
437 	xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g,
438 		       __guc_exec_queue_policy_action_size(&policy), 0, 0);
439 }
440 
441 #define parallel_read(xe_, map_, field_) \
442 	xe_map_rd_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \
443 			field_)
444 #define parallel_write(xe_, map_, field_, val_) \
445 	xe_map_wr_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \
446 			field_, val_)
447 
448 static void __register_mlrc_exec_queue(struct xe_guc *guc,
449 				       struct xe_exec_queue *q,
450 				       struct guc_ctxt_registration_info *info)
451 {
452 #define MAX_MLRC_REG_SIZE      (13 + XE_HW_ENGINE_MAX_INSTANCE * 2)
453 	struct xe_device *xe = guc_to_xe(guc);
454 	u32 action[MAX_MLRC_REG_SIZE];
455 	int len = 0;
456 	int i;
457 
458 	xe_assert(xe, xe_exec_queue_is_parallel(q));
459 
460 	action[len++] = XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC;
461 	action[len++] = info->flags;
462 	action[len++] = info->context_idx;
463 	action[len++] = info->engine_class;
464 	action[len++] = info->engine_submit_mask;
465 	action[len++] = info->wq_desc_lo;
466 	action[len++] = info->wq_desc_hi;
467 	action[len++] = info->wq_base_lo;
468 	action[len++] = info->wq_base_hi;
469 	action[len++] = info->wq_size;
470 	action[len++] = q->width;
471 	action[len++] = info->hwlrca_lo;
472 	action[len++] = info->hwlrca_hi;
473 
474 	for (i = 1; i < q->width; ++i) {
475 		struct xe_lrc *lrc = q->lrc[i];
476 
477 		action[len++] = lower_32_bits(xe_lrc_descriptor(lrc));
478 		action[len++] = upper_32_bits(xe_lrc_descriptor(lrc));
479 	}
480 
481 	xe_assert(xe, len <= MAX_MLRC_REG_SIZE);
482 #undef MAX_MLRC_REG_SIZE
483 
484 	xe_guc_ct_send(&guc->ct, action, len, 0, 0);
485 }
486 
487 static void __register_exec_queue(struct xe_guc *guc,
488 				  struct guc_ctxt_registration_info *info)
489 {
490 	u32 action[] = {
491 		XE_GUC_ACTION_REGISTER_CONTEXT,
492 		info->flags,
493 		info->context_idx,
494 		info->engine_class,
495 		info->engine_submit_mask,
496 		info->wq_desc_lo,
497 		info->wq_desc_hi,
498 		info->wq_base_lo,
499 		info->wq_base_hi,
500 		info->wq_size,
501 		info->hwlrca_lo,
502 		info->hwlrca_hi,
503 	};
504 
505 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
506 }
507 
508 static void register_exec_queue(struct xe_exec_queue *q)
509 {
510 	struct xe_guc *guc = exec_queue_to_guc(q);
511 	struct xe_device *xe = guc_to_xe(guc);
512 	struct xe_lrc *lrc = q->lrc[0];
513 	struct guc_ctxt_registration_info info;
514 
515 	xe_assert(xe, !exec_queue_registered(q));
516 
517 	memset(&info, 0, sizeof(info));
518 	info.context_idx = q->guc->id;
519 	info.engine_class = xe_engine_class_to_guc_class(q->class);
520 	info.engine_submit_mask = q->logical_mask;
521 	info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc));
522 	info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc));
523 	info.flags = CONTEXT_REGISTRATION_FLAG_KMD;
524 
525 	if (xe_exec_queue_is_parallel(q)) {
526 		u64 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc);
527 		struct iosys_map map = xe_lrc_parallel_map(lrc);
528 
529 		info.wq_desc_lo = lower_32_bits(ggtt_addr +
530 			offsetof(struct guc_submit_parallel_scratch, wq_desc));
531 		info.wq_desc_hi = upper_32_bits(ggtt_addr +
532 			offsetof(struct guc_submit_parallel_scratch, wq_desc));
533 		info.wq_base_lo = lower_32_bits(ggtt_addr +
534 			offsetof(struct guc_submit_parallel_scratch, wq[0]));
535 		info.wq_base_hi = upper_32_bits(ggtt_addr +
536 			offsetof(struct guc_submit_parallel_scratch, wq[0]));
537 		info.wq_size = WQ_SIZE;
538 
539 		q->guc->wqi_head = 0;
540 		q->guc->wqi_tail = 0;
541 		xe_map_memset(xe, &map, 0, 0, PARALLEL_SCRATCH_SIZE - WQ_SIZE);
542 		parallel_write(xe, map, wq_desc.wq_status, WQ_STATUS_ACTIVE);
543 	}
544 
545 	/*
546 	 * We must keep a reference for LR engines if engine is registered with
547 	 * the GuC as jobs signal immediately and can't destroy an engine if the
548 	 * GuC has a reference to it.
549 	 */
550 	if (xe_exec_queue_is_lr(q))
551 		xe_exec_queue_get(q);
552 
553 	set_exec_queue_registered(q);
554 	trace_xe_exec_queue_register(q);
555 	if (xe_exec_queue_is_parallel(q))
556 		__register_mlrc_exec_queue(guc, q, &info);
557 	else
558 		__register_exec_queue(guc, &info);
559 	init_policies(guc, q);
560 }
561 
562 static u32 wq_space_until_wrap(struct xe_exec_queue *q)
563 {
564 	return (WQ_SIZE - q->guc->wqi_tail);
565 }
566 
567 static int wq_wait_for_space(struct xe_exec_queue *q, u32 wqi_size)
568 {
569 	struct xe_guc *guc = exec_queue_to_guc(q);
570 	struct xe_device *xe = guc_to_xe(guc);
571 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
572 	unsigned int sleep_period_ms = 1;
573 
574 #define AVAILABLE_SPACE \
575 	CIRC_SPACE(q->guc->wqi_tail, q->guc->wqi_head, WQ_SIZE)
576 	if (wqi_size > AVAILABLE_SPACE) {
577 try_again:
578 		q->guc->wqi_head = parallel_read(xe, map, wq_desc.head);
579 		if (wqi_size > AVAILABLE_SPACE) {
580 			if (sleep_period_ms == 1024) {
581 				xe_gt_reset_async(q->gt);
582 				return -ENODEV;
583 			}
584 
585 			msleep(sleep_period_ms);
586 			sleep_period_ms <<= 1;
587 			goto try_again;
588 		}
589 	}
590 #undef AVAILABLE_SPACE
591 
592 	return 0;
593 }
594 
595 static int wq_noop_append(struct xe_exec_queue *q)
596 {
597 	struct xe_guc *guc = exec_queue_to_guc(q);
598 	struct xe_device *xe = guc_to_xe(guc);
599 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
600 	u32 len_dw = wq_space_until_wrap(q) / sizeof(u32) - 1;
601 
602 	if (wq_wait_for_space(q, wq_space_until_wrap(q)))
603 		return -ENODEV;
604 
605 	xe_assert(xe, FIELD_FIT(WQ_LEN_MASK, len_dw));
606 
607 	parallel_write(xe, map, wq[q->guc->wqi_tail / sizeof(u32)],
608 		       FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_NOOP) |
609 		       FIELD_PREP(WQ_LEN_MASK, len_dw));
610 	q->guc->wqi_tail = 0;
611 
612 	return 0;
613 }
614 
615 static void wq_item_append(struct xe_exec_queue *q)
616 {
617 	struct xe_guc *guc = exec_queue_to_guc(q);
618 	struct xe_device *xe = guc_to_xe(guc);
619 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
620 #define WQ_HEADER_SIZE	4	/* Includes 1 LRC address too */
621 	u32 wqi[XE_HW_ENGINE_MAX_INSTANCE + (WQ_HEADER_SIZE - 1)];
622 	u32 wqi_size = (q->width + (WQ_HEADER_SIZE - 1)) * sizeof(u32);
623 	u32 len_dw = (wqi_size / sizeof(u32)) - 1;
624 	int i = 0, j;
625 
626 	if (wqi_size > wq_space_until_wrap(q)) {
627 		if (wq_noop_append(q))
628 			return;
629 	}
630 	if (wq_wait_for_space(q, wqi_size))
631 		return;
632 
633 	wqi[i++] = FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_MULTI_LRC) |
634 		FIELD_PREP(WQ_LEN_MASK, len_dw);
635 	wqi[i++] = xe_lrc_descriptor(q->lrc[0]);
636 	wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, q->guc->id) |
637 		FIELD_PREP(WQ_RING_TAIL_MASK, q->lrc[0]->ring.tail / sizeof(u64));
638 	wqi[i++] = 0;
639 	for (j = 1; j < q->width; ++j) {
640 		struct xe_lrc *lrc = q->lrc[j];
641 
642 		wqi[i++] = lrc->ring.tail / sizeof(u64);
643 	}
644 
645 	xe_assert(xe, i == wqi_size / sizeof(u32));
646 
647 	iosys_map_incr(&map, offsetof(struct guc_submit_parallel_scratch,
648 				      wq[q->guc->wqi_tail / sizeof(u32)]));
649 	xe_map_memcpy_to(xe, &map, 0, wqi, wqi_size);
650 	q->guc->wqi_tail += wqi_size;
651 	xe_assert(xe, q->guc->wqi_tail <= WQ_SIZE);
652 
653 	xe_device_wmb(xe);
654 
655 	map = xe_lrc_parallel_map(q->lrc[0]);
656 	parallel_write(xe, map, wq_desc.tail, q->guc->wqi_tail);
657 }
658 
659 #define RESUME_PENDING	~0x0ull
660 static void submit_exec_queue(struct xe_exec_queue *q)
661 {
662 	struct xe_guc *guc = exec_queue_to_guc(q);
663 	struct xe_device *xe = guc_to_xe(guc);
664 	struct xe_lrc *lrc = q->lrc[0];
665 	u32 action[3];
666 	u32 g2h_len = 0;
667 	u32 num_g2h = 0;
668 	int len = 0;
669 	bool extra_submit = false;
670 
671 	xe_assert(xe, exec_queue_registered(q));
672 
673 	if (xe_exec_queue_is_parallel(q))
674 		wq_item_append(q);
675 	else
676 		xe_lrc_set_ring_tail(lrc, lrc->ring.tail);
677 
678 	if (exec_queue_suspended(q) && !xe_exec_queue_is_parallel(q))
679 		return;
680 
681 	if (!exec_queue_enabled(q) && !exec_queue_suspended(q)) {
682 		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET;
683 		action[len++] = q->guc->id;
684 		action[len++] = GUC_CONTEXT_ENABLE;
685 		g2h_len = G2H_LEN_DW_SCHED_CONTEXT_MODE_SET;
686 		num_g2h = 1;
687 		if (xe_exec_queue_is_parallel(q))
688 			extra_submit = true;
689 
690 		q->guc->resume_time = RESUME_PENDING;
691 		set_exec_queue_pending_enable(q);
692 		set_exec_queue_enabled(q);
693 		trace_xe_exec_queue_scheduling_enable(q);
694 	} else {
695 		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT;
696 		action[len++] = q->guc->id;
697 		trace_xe_exec_queue_submit(q);
698 	}
699 
700 	xe_guc_ct_send(&guc->ct, action, len, g2h_len, num_g2h);
701 
702 	if (extra_submit) {
703 		len = 0;
704 		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT;
705 		action[len++] = q->guc->id;
706 		trace_xe_exec_queue_submit(q);
707 
708 		xe_guc_ct_send(&guc->ct, action, len, 0, 0);
709 	}
710 }
711 
712 static struct dma_fence *
713 guc_exec_queue_run_job(struct drm_sched_job *drm_job)
714 {
715 	struct xe_sched_job *job = to_xe_sched_job(drm_job);
716 	struct xe_exec_queue *q = job->q;
717 	struct xe_guc *guc = exec_queue_to_guc(q);
718 	struct xe_device *xe = guc_to_xe(guc);
719 	bool lr = xe_exec_queue_is_lr(q);
720 
721 	xe_assert(xe, !(exec_queue_destroyed(q) || exec_queue_pending_disable(q)) ||
722 		  exec_queue_banned(q) || exec_queue_suspended(q));
723 
724 	trace_xe_sched_job_run(job);
725 
726 	if (!exec_queue_killed_or_banned_or_wedged(q) && !xe_sched_job_is_error(job)) {
727 		if (!exec_queue_registered(q))
728 			register_exec_queue(q);
729 		if (!lr)	/* LR jobs are emitted in the exec IOCTL */
730 			q->ring_ops->emit_job(job);
731 		submit_exec_queue(q);
732 	}
733 
734 	if (lr) {
735 		xe_sched_job_set_error(job, -EOPNOTSUPP);
736 		return NULL;
737 	} else if (test_and_set_bit(JOB_FLAG_SUBMIT, &job->fence->flags)) {
738 		return job->fence;
739 	} else {
740 		return dma_fence_get(job->fence);
741 	}
742 }
743 
744 static void guc_exec_queue_free_job(struct drm_sched_job *drm_job)
745 {
746 	struct xe_sched_job *job = to_xe_sched_job(drm_job);
747 
748 	xe_exec_queue_update_run_ticks(job->q);
749 
750 	trace_xe_sched_job_free(job);
751 	xe_sched_job_put(job);
752 }
753 
754 static int guc_read_stopped(struct xe_guc *guc)
755 {
756 	return atomic_read(&guc->submission_state.stopped);
757 }
758 
759 #define MAKE_SCHED_CONTEXT_ACTION(q, enable_disable)			\
760 	u32 action[] = {						\
761 		XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET,			\
762 		q->guc->id,						\
763 		GUC_CONTEXT_##enable_disable,				\
764 	}
765 
766 static void disable_scheduling_deregister(struct xe_guc *guc,
767 					  struct xe_exec_queue *q)
768 {
769 	MAKE_SCHED_CONTEXT_ACTION(q, DISABLE);
770 	struct xe_device *xe = guc_to_xe(guc);
771 	int ret;
772 
773 	set_min_preemption_timeout(guc, q);
774 	smp_rmb();
775 	ret = wait_event_timeout(guc->ct.wq, !exec_queue_pending_enable(q) ||
776 				 guc_read_stopped(guc), HZ * 5);
777 	if (!ret) {
778 		struct xe_gpu_scheduler *sched = &q->guc->sched;
779 
780 		drm_warn(&xe->drm, "Pending enable failed to respond");
781 		xe_sched_submission_start(sched);
782 		xe_gt_reset_async(q->gt);
783 		xe_sched_tdr_queue_imm(sched);
784 		return;
785 	}
786 
787 	clear_exec_queue_enabled(q);
788 	set_exec_queue_pending_disable(q);
789 	set_exec_queue_destroyed(q);
790 	trace_xe_exec_queue_scheduling_disable(q);
791 
792 	/*
793 	 * Reserve space for both G2H here as the 2nd G2H is sent from a G2H
794 	 * handler and we are not allowed to reserved G2H space in handlers.
795 	 */
796 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
797 		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
798 		       G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
799 }
800 
801 static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q)
802 {
803 	struct xe_guc *guc = exec_queue_to_guc(q);
804 	struct xe_device *xe = guc_to_xe(guc);
805 
806 	/** to wakeup xe_wait_user_fence ioctl if exec queue is reset */
807 	wake_up_all(&xe->ufence_wq);
808 
809 	if (xe_exec_queue_is_lr(q))
810 		queue_work(guc_to_gt(guc)->ordered_wq, &q->guc->lr_tdr);
811 	else
812 		xe_sched_tdr_queue_imm(&q->guc->sched);
813 }
814 
815 /**
816  * xe_guc_submit_wedge() - Wedge GuC submission
817  * @guc: the GuC object
818  *
819  * Save exec queue's registered with GuC state by taking a ref to each queue.
820  * Register a DRMM handler to drop refs upon driver unload.
821  */
822 void xe_guc_submit_wedge(struct xe_guc *guc)
823 {
824 	struct xe_device *xe = guc_to_xe(guc);
825 	struct xe_exec_queue *q;
826 	unsigned long index;
827 	int err;
828 
829 	xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode);
830 
831 	err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev,
832 				       guc_submit_wedged_fini, guc);
833 	if (err) {
834 		drm_err(&xe->drm, "Failed to register xe_guc_submit clean-up on wedged.mode=2. Although device is wedged.\n");
835 		return;
836 	}
837 
838 	mutex_lock(&guc->submission_state.lock);
839 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
840 		if (xe_exec_queue_get_unless_zero(q))
841 			set_exec_queue_wedged(q);
842 	mutex_unlock(&guc->submission_state.lock);
843 }
844 
845 static bool guc_submit_hint_wedged(struct xe_guc *guc)
846 {
847 	struct xe_device *xe = guc_to_xe(guc);
848 
849 	if (xe->wedged.mode != 2)
850 		return false;
851 
852 	if (xe_device_wedged(xe))
853 		return true;
854 
855 	xe_device_declare_wedged(xe);
856 
857 	return true;
858 }
859 
860 static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w)
861 {
862 	struct xe_guc_exec_queue *ge =
863 		container_of(w, struct xe_guc_exec_queue, lr_tdr);
864 	struct xe_exec_queue *q = ge->q;
865 	struct xe_guc *guc = exec_queue_to_guc(q);
866 	struct xe_device *xe = guc_to_xe(guc);
867 	struct xe_gpu_scheduler *sched = &ge->sched;
868 	bool wedged;
869 
870 	xe_assert(xe, xe_exec_queue_is_lr(q));
871 	trace_xe_exec_queue_lr_cleanup(q);
872 
873 	wedged = guc_submit_hint_wedged(exec_queue_to_guc(q));
874 
875 	/* Kill the run_job / process_msg entry points */
876 	xe_sched_submission_stop(sched);
877 
878 	/*
879 	 * Engine state now mostly stable, disable scheduling / deregister if
880 	 * needed. This cleanup routine might be called multiple times, where
881 	 * the actual async engine deregister drops the final engine ref.
882 	 * Calling disable_scheduling_deregister will mark the engine as
883 	 * destroyed and fire off the CT requests to disable scheduling /
884 	 * deregister, which we only want to do once. We also don't want to mark
885 	 * the engine as pending_disable again as this may race with the
886 	 * xe_guc_deregister_done_handler() which treats it as an unexpected
887 	 * state.
888 	 */
889 	if (!wedged && exec_queue_registered(q) && !exec_queue_destroyed(q)) {
890 		struct xe_guc *guc = exec_queue_to_guc(q);
891 		int ret;
892 
893 		set_exec_queue_banned(q);
894 		disable_scheduling_deregister(guc, q);
895 
896 		/*
897 		 * Must wait for scheduling to be disabled before signalling
898 		 * any fences, if GT broken the GT reset code should signal us.
899 		 */
900 		ret = wait_event_timeout(guc->ct.wq,
901 					 !exec_queue_pending_disable(q) ||
902 					 guc_read_stopped(guc), HZ * 5);
903 		if (!ret) {
904 			drm_warn(&xe->drm, "Schedule disable failed to respond");
905 			xe_sched_submission_start(sched);
906 			xe_gt_reset_async(q->gt);
907 			return;
908 		}
909 	}
910 
911 	xe_sched_submission_start(sched);
912 }
913 
914 #define ADJUST_FIVE_PERCENT(__t)	mul_u64_u32_div(__t, 105, 100)
915 
916 static bool check_timeout(struct xe_exec_queue *q, struct xe_sched_job *job)
917 {
918 	struct xe_gt *gt = guc_to_gt(exec_queue_to_guc(q));
919 	u32 ctx_timestamp = xe_lrc_ctx_timestamp(q->lrc[0]);
920 	u32 ctx_job_timestamp = xe_lrc_ctx_job_timestamp(q->lrc[0]);
921 	u32 timeout_ms = q->sched_props.job_timeout_ms;
922 	u32 diff;
923 	u64 running_time_ms;
924 
925 	/*
926 	 * Counter wraps at ~223s at the usual 19.2MHz, be paranoid catch
927 	 * possible overflows with a high timeout.
928 	 */
929 	xe_gt_assert(gt, timeout_ms < 100 * MSEC_PER_SEC);
930 
931 	if (ctx_timestamp < ctx_job_timestamp)
932 		diff = ctx_timestamp + U32_MAX - ctx_job_timestamp;
933 	else
934 		diff = ctx_timestamp - ctx_job_timestamp;
935 
936 	/*
937 	 * Ensure timeout is within 5% to account for an GuC scheduling latency
938 	 */
939 	running_time_ms =
940 		ADJUST_FIVE_PERCENT(xe_gt_clock_interval_to_ms(gt, diff));
941 
942 	xe_gt_dbg(gt,
943 		  "Check job timeout: seqno=%u, lrc_seqno=%u, guc_id=%d, running_time_ms=%llu, timeout_ms=%u, diff=0x%08x",
944 		  xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job),
945 		  q->guc->id, running_time_ms, timeout_ms, diff);
946 
947 	return running_time_ms >= timeout_ms;
948 }
949 
950 static void enable_scheduling(struct xe_exec_queue *q)
951 {
952 	MAKE_SCHED_CONTEXT_ACTION(q, ENABLE);
953 	struct xe_guc *guc = exec_queue_to_guc(q);
954 	int ret;
955 
956 	xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q));
957 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
958 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
959 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q));
960 
961 	set_exec_queue_pending_enable(q);
962 	set_exec_queue_enabled(q);
963 	trace_xe_exec_queue_scheduling_enable(q);
964 
965 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
966 		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);
967 
968 	ret = wait_event_timeout(guc->ct.wq,
969 				 !exec_queue_pending_enable(q) ||
970 				 guc_read_stopped(guc), HZ * 5);
971 	if (!ret || guc_read_stopped(guc)) {
972 		xe_gt_warn(guc_to_gt(guc), "Schedule enable failed to respond");
973 		set_exec_queue_banned(q);
974 		xe_gt_reset_async(q->gt);
975 		xe_sched_tdr_queue_imm(&q->guc->sched);
976 	}
977 }
978 
979 static void disable_scheduling(struct xe_exec_queue *q, bool immediate)
980 {
981 	MAKE_SCHED_CONTEXT_ACTION(q, DISABLE);
982 	struct xe_guc *guc = exec_queue_to_guc(q);
983 
984 	xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q));
985 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
986 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
987 
988 	if (immediate)
989 		set_min_preemption_timeout(guc, q);
990 	clear_exec_queue_enabled(q);
991 	set_exec_queue_pending_disable(q);
992 	trace_xe_exec_queue_scheduling_disable(q);
993 
994 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
995 		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);
996 }
997 
998 static void __deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
999 {
1000 	u32 action[] = {
1001 		XE_GUC_ACTION_DEREGISTER_CONTEXT,
1002 		q->guc->id,
1003 	};
1004 
1005 	xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q));
1006 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
1007 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q));
1008 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
1009 
1010 	set_exec_queue_destroyed(q);
1011 	trace_xe_exec_queue_deregister(q);
1012 
1013 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
1014 		       G2H_LEN_DW_DEREGISTER_CONTEXT, 1);
1015 }
1016 
1017 static enum drm_gpu_sched_stat
1018 guc_exec_queue_timedout_job(struct drm_sched_job *drm_job)
1019 {
1020 	struct xe_sched_job *job = to_xe_sched_job(drm_job);
1021 	struct xe_sched_job *tmp_job;
1022 	struct xe_exec_queue *q = job->q;
1023 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1024 	struct xe_guc *guc = exec_queue_to_guc(q);
1025 	const char *process_name = "no process";
1026 	int err = -ETIME;
1027 	pid_t pid = -1;
1028 	int i = 0;
1029 	bool wedged, skip_timeout_check;
1030 
1031 	/*
1032 	 * TDR has fired before free job worker. Common if exec queue
1033 	 * immediately closed after last fence signaled. Add back to pending
1034 	 * list so job can be freed and kick scheduler ensuring free job is not
1035 	 * lost.
1036 	 */
1037 	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &job->fence->flags)) {
1038 		xe_sched_add_pending_job(sched, job);
1039 		xe_sched_submission_start(sched);
1040 
1041 		return DRM_GPU_SCHED_STAT_NOMINAL;
1042 	}
1043 
1044 	/* Kill the run_job entry point */
1045 	xe_sched_submission_stop(sched);
1046 
1047 	/* Must check all state after stopping scheduler */
1048 	skip_timeout_check = exec_queue_reset(q) ||
1049 		exec_queue_killed_or_banned_or_wedged(q) ||
1050 		exec_queue_destroyed(q);
1051 
1052 	/* Job hasn't started, can't be timed out */
1053 	if (!skip_timeout_check && !xe_sched_job_started(job))
1054 		goto rearm;
1055 
1056 	/*
1057 	 * XXX: Sampling timeout doesn't work in wedged mode as we have to
1058 	 * modify scheduling state to read timestamp. We could read the
1059 	 * timestamp from a register to accumulate current running time but this
1060 	 * doesn't work for SRIOV. For now assuming timeouts in wedged mode are
1061 	 * genuine timeouts.
1062 	 */
1063 	wedged = guc_submit_hint_wedged(exec_queue_to_guc(q));
1064 
1065 	/* Engine state now stable, disable scheduling to check timestamp */
1066 	if (!wedged && exec_queue_registered(q)) {
1067 		int ret;
1068 
1069 		if (exec_queue_reset(q))
1070 			err = -EIO;
1071 
1072 		if (!exec_queue_destroyed(q)) {
1073 			/*
1074 			 * Wait for any pending G2H to flush out before
1075 			 * modifying state
1076 			 */
1077 			ret = wait_event_timeout(guc->ct.wq,
1078 						 !exec_queue_pending_enable(q) ||
1079 						 guc_read_stopped(guc), HZ * 5);
1080 			if (!ret || guc_read_stopped(guc))
1081 				goto trigger_reset;
1082 
1083 			/*
1084 			 * Flag communicates to G2H handler that schedule
1085 			 * disable originated from a timeout check. The G2H then
1086 			 * avoid triggering cleanup or deregistering the exec
1087 			 * queue.
1088 			 */
1089 			set_exec_queue_check_timeout(q);
1090 			disable_scheduling(q, skip_timeout_check);
1091 		}
1092 
1093 		/*
1094 		 * Must wait for scheduling to be disabled before signalling
1095 		 * any fences, if GT broken the GT reset code should signal us.
1096 		 *
1097 		 * FIXME: Tests can generate a ton of 0x6000 (IOMMU CAT fault
1098 		 * error) messages which can cause the schedule disable to get
1099 		 * lost. If this occurs, trigger a GT reset to recover.
1100 		 */
1101 		smp_rmb();
1102 		ret = wait_event_timeout(guc->ct.wq,
1103 					 !exec_queue_pending_disable(q) ||
1104 					 guc_read_stopped(guc), HZ * 5);
1105 		if (!ret || guc_read_stopped(guc)) {
1106 trigger_reset:
1107 			if (!ret)
1108 				xe_gt_warn(guc_to_gt(guc), "Schedule disable failed to respond");
1109 			set_exec_queue_extra_ref(q);
1110 			xe_exec_queue_get(q);	/* GT reset owns this */
1111 			set_exec_queue_banned(q);
1112 			xe_gt_reset_async(q->gt);
1113 			xe_sched_tdr_queue_imm(sched);
1114 			goto rearm;
1115 		}
1116 	}
1117 
1118 	/*
1119 	 * Check if job is actually timed out, if so restart job execution and TDR
1120 	 */
1121 	if (!wedged && !skip_timeout_check && !check_timeout(q, job) &&
1122 	    !exec_queue_reset(q) && exec_queue_registered(q)) {
1123 		clear_exec_queue_check_timeout(q);
1124 		goto sched_enable;
1125 	}
1126 
1127 	if (q->vm && q->vm->xef) {
1128 		process_name = q->vm->xef->process_name;
1129 		pid = q->vm->xef->pid;
1130 	}
1131 	xe_gt_notice(guc_to_gt(guc), "Timedout job: seqno=%u, lrc_seqno=%u, guc_id=%d, flags=0x%lx in %s [%d]",
1132 		     xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job),
1133 		     q->guc->id, q->flags, process_name, pid);
1134 
1135 	trace_xe_sched_job_timedout(job);
1136 
1137 	if (!exec_queue_killed(q))
1138 		xe_devcoredump(job);
1139 
1140 	/*
1141 	 * Kernel jobs should never fail, nor should VM jobs if they do
1142 	 * somethings has gone wrong and the GT needs a reset
1143 	 */
1144 	xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_KERNEL,
1145 		   "Kernel-submitted job timed out\n");
1146 	xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q),
1147 		   "VM job timed out on non-killed execqueue\n");
1148 	if (!wedged && (q->flags & EXEC_QUEUE_FLAG_KERNEL ||
1149 			(q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q)))) {
1150 		if (!xe_sched_invalidate_job(job, 2)) {
1151 			clear_exec_queue_check_timeout(q);
1152 			xe_gt_reset_async(q->gt);
1153 			goto rearm;
1154 		}
1155 	}
1156 
1157 	/* Finish cleaning up exec queue via deregister */
1158 	set_exec_queue_banned(q);
1159 	if (!wedged && exec_queue_registered(q) && !exec_queue_destroyed(q)) {
1160 		set_exec_queue_extra_ref(q);
1161 		xe_exec_queue_get(q);
1162 		__deregister_exec_queue(guc, q);
1163 	}
1164 
1165 	/* Stop fence signaling */
1166 	xe_hw_fence_irq_stop(q->fence_irq);
1167 
1168 	/*
1169 	 * Fence state now stable, stop / start scheduler which cleans up any
1170 	 * fences that are complete
1171 	 */
1172 	xe_sched_add_pending_job(sched, job);
1173 	xe_sched_submission_start(sched);
1174 
1175 	xe_guc_exec_queue_trigger_cleanup(q);
1176 
1177 	/* Mark all outstanding jobs as bad, thus completing them */
1178 	spin_lock(&sched->base.job_list_lock);
1179 	list_for_each_entry(tmp_job, &sched->base.pending_list, drm.list)
1180 		xe_sched_job_set_error(tmp_job, !i++ ? err : -ECANCELED);
1181 	spin_unlock(&sched->base.job_list_lock);
1182 
1183 	/* Start fence signaling */
1184 	xe_hw_fence_irq_start(q->fence_irq);
1185 
1186 	return DRM_GPU_SCHED_STAT_NOMINAL;
1187 
1188 sched_enable:
1189 	enable_scheduling(q);
1190 rearm:
1191 	/*
1192 	 * XXX: Ideally want to adjust timeout based on current exection time
1193 	 * but there is not currently an easy way to do in DRM scheduler. With
1194 	 * some thought, do this in a follow up.
1195 	 */
1196 	xe_sched_add_pending_job(sched, job);
1197 	xe_sched_submission_start(sched);
1198 
1199 	return DRM_GPU_SCHED_STAT_NOMINAL;
1200 }
1201 
1202 static void __guc_exec_queue_fini_async(struct work_struct *w)
1203 {
1204 	struct xe_guc_exec_queue *ge =
1205 		container_of(w, struct xe_guc_exec_queue, fini_async);
1206 	struct xe_exec_queue *q = ge->q;
1207 	struct xe_guc *guc = exec_queue_to_guc(q);
1208 
1209 	xe_pm_runtime_get(guc_to_xe(guc));
1210 	trace_xe_exec_queue_destroy(q);
1211 
1212 	if (xe_exec_queue_is_lr(q))
1213 		cancel_work_sync(&ge->lr_tdr);
1214 	release_guc_id(guc, q);
1215 	xe_sched_entity_fini(&ge->entity);
1216 	xe_sched_fini(&ge->sched);
1217 
1218 	kfree(ge);
1219 	xe_exec_queue_fini(q);
1220 	xe_pm_runtime_put(guc_to_xe(guc));
1221 }
1222 
1223 static void guc_exec_queue_fini_async(struct xe_exec_queue *q)
1224 {
1225 	struct xe_guc *guc = exec_queue_to_guc(q);
1226 	struct xe_device *xe = guc_to_xe(guc);
1227 
1228 	INIT_WORK(&q->guc->fini_async, __guc_exec_queue_fini_async);
1229 
1230 	/* We must block on kernel engines so slabs are empty on driver unload */
1231 	if (q->flags & EXEC_QUEUE_FLAG_PERMANENT || exec_queue_wedged(q))
1232 		__guc_exec_queue_fini_async(&q->guc->fini_async);
1233 	else
1234 		queue_work(xe->destroy_wq, &q->guc->fini_async);
1235 }
1236 
1237 static void __guc_exec_queue_fini(struct xe_guc *guc, struct xe_exec_queue *q)
1238 {
1239 	/*
1240 	 * Might be done from within the GPU scheduler, need to do async as we
1241 	 * fini the scheduler when the engine is fini'd, the scheduler can't
1242 	 * complete fini within itself (circular dependency). Async resolves
1243 	 * this we and don't really care when everything is fini'd, just that it
1244 	 * is.
1245 	 */
1246 	guc_exec_queue_fini_async(q);
1247 }
1248 
1249 static void __guc_exec_queue_process_msg_cleanup(struct xe_sched_msg *msg)
1250 {
1251 	struct xe_exec_queue *q = msg->private_data;
1252 	struct xe_guc *guc = exec_queue_to_guc(q);
1253 	struct xe_device *xe = guc_to_xe(guc);
1254 
1255 	xe_assert(xe, !(q->flags & EXEC_QUEUE_FLAG_PERMANENT));
1256 	trace_xe_exec_queue_cleanup_entity(q);
1257 
1258 	if (exec_queue_registered(q))
1259 		disable_scheduling_deregister(guc, q);
1260 	else
1261 		__guc_exec_queue_fini(guc, q);
1262 }
1263 
1264 static bool guc_exec_queue_allowed_to_change_state(struct xe_exec_queue *q)
1265 {
1266 	return !exec_queue_killed_or_banned_or_wedged(q) && exec_queue_registered(q);
1267 }
1268 
1269 static void __guc_exec_queue_process_msg_set_sched_props(struct xe_sched_msg *msg)
1270 {
1271 	struct xe_exec_queue *q = msg->private_data;
1272 	struct xe_guc *guc = exec_queue_to_guc(q);
1273 
1274 	if (guc_exec_queue_allowed_to_change_state(q))
1275 		init_policies(guc, q);
1276 	kfree(msg);
1277 }
1278 
1279 static void __suspend_fence_signal(struct xe_exec_queue *q)
1280 {
1281 	if (!q->guc->suspend_pending)
1282 		return;
1283 
1284 	WRITE_ONCE(q->guc->suspend_pending, false);
1285 	wake_up(&q->guc->suspend_wait);
1286 }
1287 
1288 static void suspend_fence_signal(struct xe_exec_queue *q)
1289 {
1290 	struct xe_guc *guc = exec_queue_to_guc(q);
1291 	struct xe_device *xe = guc_to_xe(guc);
1292 
1293 	xe_assert(xe, exec_queue_suspended(q) || exec_queue_killed(q) ||
1294 		  guc_read_stopped(guc));
1295 	xe_assert(xe, q->guc->suspend_pending);
1296 
1297 	__suspend_fence_signal(q);
1298 }
1299 
1300 static void __guc_exec_queue_process_msg_suspend(struct xe_sched_msg *msg)
1301 {
1302 	struct xe_exec_queue *q = msg->private_data;
1303 	struct xe_guc *guc = exec_queue_to_guc(q);
1304 
1305 	if (guc_exec_queue_allowed_to_change_state(q) && !exec_queue_suspended(q) &&
1306 	    exec_queue_enabled(q)) {
1307 		wait_event(guc->ct.wq, q->guc->resume_time != RESUME_PENDING ||
1308 			   guc_read_stopped(guc));
1309 
1310 		if (!guc_read_stopped(guc)) {
1311 			s64 since_resume_ms =
1312 				ktime_ms_delta(ktime_get(),
1313 					       q->guc->resume_time);
1314 			s64 wait_ms = q->vm->preempt.min_run_period_ms -
1315 				since_resume_ms;
1316 
1317 			if (wait_ms > 0 && q->guc->resume_time)
1318 				msleep(wait_ms);
1319 
1320 			set_exec_queue_suspended(q);
1321 			disable_scheduling(q, false);
1322 		}
1323 	} else if (q->guc->suspend_pending) {
1324 		set_exec_queue_suspended(q);
1325 		suspend_fence_signal(q);
1326 	}
1327 }
1328 
1329 static void __guc_exec_queue_process_msg_resume(struct xe_sched_msg *msg)
1330 {
1331 	struct xe_exec_queue *q = msg->private_data;
1332 
1333 	if (guc_exec_queue_allowed_to_change_state(q)) {
1334 		clear_exec_queue_suspended(q);
1335 		if (!exec_queue_enabled(q)) {
1336 			q->guc->resume_time = RESUME_PENDING;
1337 			enable_scheduling(q);
1338 		}
1339 	} else {
1340 		clear_exec_queue_suspended(q);
1341 	}
1342 }
1343 
1344 #define CLEANUP		1	/* Non-zero values to catch uninitialized msg */
1345 #define SET_SCHED_PROPS	2
1346 #define SUSPEND		3
1347 #define RESUME		4
1348 #define OPCODE_MASK	0xf
1349 #define MSG_LOCKED	BIT(8)
1350 
1351 static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)
1352 {
1353 	struct xe_device *xe = guc_to_xe(exec_queue_to_guc(msg->private_data));
1354 
1355 	trace_xe_sched_msg_recv(msg);
1356 
1357 	switch (msg->opcode) {
1358 	case CLEANUP:
1359 		__guc_exec_queue_process_msg_cleanup(msg);
1360 		break;
1361 	case SET_SCHED_PROPS:
1362 		__guc_exec_queue_process_msg_set_sched_props(msg);
1363 		break;
1364 	case SUSPEND:
1365 		__guc_exec_queue_process_msg_suspend(msg);
1366 		break;
1367 	case RESUME:
1368 		__guc_exec_queue_process_msg_resume(msg);
1369 		break;
1370 	default:
1371 		XE_WARN_ON("Unknown message type");
1372 	}
1373 
1374 	xe_pm_runtime_put(xe);
1375 }
1376 
1377 static const struct drm_sched_backend_ops drm_sched_ops = {
1378 	.run_job = guc_exec_queue_run_job,
1379 	.free_job = guc_exec_queue_free_job,
1380 	.timedout_job = guc_exec_queue_timedout_job,
1381 };
1382 
1383 static const struct xe_sched_backend_ops xe_sched_ops = {
1384 	.process_msg = guc_exec_queue_process_msg,
1385 };
1386 
1387 static int guc_exec_queue_init(struct xe_exec_queue *q)
1388 {
1389 	struct xe_gpu_scheduler *sched;
1390 	struct xe_guc *guc = exec_queue_to_guc(q);
1391 	struct xe_device *xe = guc_to_xe(guc);
1392 	struct xe_guc_exec_queue *ge;
1393 	long timeout;
1394 	int err, i;
1395 
1396 	xe_assert(xe, xe_device_uc_enabled(guc_to_xe(guc)));
1397 
1398 	ge = kzalloc(sizeof(*ge), GFP_KERNEL);
1399 	if (!ge)
1400 		return -ENOMEM;
1401 
1402 	q->guc = ge;
1403 	ge->q = q;
1404 	init_waitqueue_head(&ge->suspend_wait);
1405 
1406 	for (i = 0; i < MAX_STATIC_MSG_TYPE; ++i)
1407 		INIT_LIST_HEAD(&ge->static_msgs[i].link);
1408 
1409 	timeout = (q->vm && xe_vm_in_lr_mode(q->vm)) ? MAX_SCHEDULE_TIMEOUT :
1410 		  msecs_to_jiffies(q->sched_props.job_timeout_ms);
1411 	err = xe_sched_init(&ge->sched, &drm_sched_ops, &xe_sched_ops,
1412 			    NULL, q->lrc[0]->ring.size / MAX_JOB_SIZE_BYTES, 64,
1413 			    timeout, guc_to_gt(guc)->ordered_wq, NULL,
1414 			    q->name, gt_to_xe(q->gt)->drm.dev);
1415 	if (err)
1416 		goto err_free;
1417 
1418 	sched = &ge->sched;
1419 	err = xe_sched_entity_init(&ge->entity, sched);
1420 	if (err)
1421 		goto err_sched;
1422 
1423 	if (xe_exec_queue_is_lr(q))
1424 		INIT_WORK(&q->guc->lr_tdr, xe_guc_exec_queue_lr_cleanup);
1425 
1426 	mutex_lock(&guc->submission_state.lock);
1427 
1428 	err = alloc_guc_id(guc, q);
1429 	if (err)
1430 		goto err_entity;
1431 
1432 	q->entity = &ge->entity;
1433 
1434 	if (guc_read_stopped(guc))
1435 		xe_sched_stop(sched);
1436 
1437 	mutex_unlock(&guc->submission_state.lock);
1438 
1439 	xe_exec_queue_assign_name(q, q->guc->id);
1440 
1441 	trace_xe_exec_queue_create(q);
1442 
1443 	return 0;
1444 
1445 err_entity:
1446 	mutex_unlock(&guc->submission_state.lock);
1447 	xe_sched_entity_fini(&ge->entity);
1448 err_sched:
1449 	xe_sched_fini(&ge->sched);
1450 err_free:
1451 	kfree(ge);
1452 
1453 	return err;
1454 }
1455 
1456 static void guc_exec_queue_kill(struct xe_exec_queue *q)
1457 {
1458 	trace_xe_exec_queue_kill(q);
1459 	set_exec_queue_killed(q);
1460 	__suspend_fence_signal(q);
1461 	xe_guc_exec_queue_trigger_cleanup(q);
1462 }
1463 
1464 static void guc_exec_queue_add_msg(struct xe_exec_queue *q, struct xe_sched_msg *msg,
1465 				   u32 opcode)
1466 {
1467 	xe_pm_runtime_get_noresume(guc_to_xe(exec_queue_to_guc(q)));
1468 
1469 	INIT_LIST_HEAD(&msg->link);
1470 	msg->opcode = opcode & OPCODE_MASK;
1471 	msg->private_data = q;
1472 
1473 	trace_xe_sched_msg_add(msg);
1474 	if (opcode & MSG_LOCKED)
1475 		xe_sched_add_msg_locked(&q->guc->sched, msg);
1476 	else
1477 		xe_sched_add_msg(&q->guc->sched, msg);
1478 }
1479 
1480 static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q,
1481 				       struct xe_sched_msg *msg,
1482 				       u32 opcode)
1483 {
1484 	if (!list_empty(&msg->link))
1485 		return false;
1486 
1487 	guc_exec_queue_add_msg(q, msg, opcode | MSG_LOCKED);
1488 
1489 	return true;
1490 }
1491 
1492 #define STATIC_MSG_CLEANUP	0
1493 #define STATIC_MSG_SUSPEND	1
1494 #define STATIC_MSG_RESUME	2
1495 static void guc_exec_queue_fini(struct xe_exec_queue *q)
1496 {
1497 	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP;
1498 
1499 	if (!(q->flags & EXEC_QUEUE_FLAG_PERMANENT) && !exec_queue_wedged(q))
1500 		guc_exec_queue_add_msg(q, msg, CLEANUP);
1501 	else
1502 		__guc_exec_queue_fini(exec_queue_to_guc(q), q);
1503 }
1504 
1505 static int guc_exec_queue_set_priority(struct xe_exec_queue *q,
1506 				       enum xe_exec_queue_priority priority)
1507 {
1508 	struct xe_sched_msg *msg;
1509 
1510 	if (q->sched_props.priority == priority ||
1511 	    exec_queue_killed_or_banned_or_wedged(q))
1512 		return 0;
1513 
1514 	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
1515 	if (!msg)
1516 		return -ENOMEM;
1517 
1518 	q->sched_props.priority = priority;
1519 	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);
1520 
1521 	return 0;
1522 }
1523 
1524 static int guc_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us)
1525 {
1526 	struct xe_sched_msg *msg;
1527 
1528 	if (q->sched_props.timeslice_us == timeslice_us ||
1529 	    exec_queue_killed_or_banned_or_wedged(q))
1530 		return 0;
1531 
1532 	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
1533 	if (!msg)
1534 		return -ENOMEM;
1535 
1536 	q->sched_props.timeslice_us = timeslice_us;
1537 	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);
1538 
1539 	return 0;
1540 }
1541 
1542 static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q,
1543 					      u32 preempt_timeout_us)
1544 {
1545 	struct xe_sched_msg *msg;
1546 
1547 	if (q->sched_props.preempt_timeout_us == preempt_timeout_us ||
1548 	    exec_queue_killed_or_banned_or_wedged(q))
1549 		return 0;
1550 
1551 	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
1552 	if (!msg)
1553 		return -ENOMEM;
1554 
1555 	q->sched_props.preempt_timeout_us = preempt_timeout_us;
1556 	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);
1557 
1558 	return 0;
1559 }
1560 
1561 static int guc_exec_queue_suspend(struct xe_exec_queue *q)
1562 {
1563 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1564 	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_SUSPEND;
1565 
1566 	if (exec_queue_killed_or_banned_or_wedged(q))
1567 		return -EINVAL;
1568 
1569 	xe_sched_msg_lock(sched);
1570 	if (guc_exec_queue_try_add_msg(q, msg, SUSPEND))
1571 		q->guc->suspend_pending = true;
1572 	xe_sched_msg_unlock(sched);
1573 
1574 	return 0;
1575 }
1576 
1577 static int guc_exec_queue_suspend_wait(struct xe_exec_queue *q)
1578 {
1579 	struct xe_guc *guc = exec_queue_to_guc(q);
1580 	int ret;
1581 
1582 	/*
1583 	 * Likely don't need to check exec_queue_killed() as we clear
1584 	 * suspend_pending upon kill but to be paranoid but races in which
1585 	 * suspend_pending is set after kill also check kill here.
1586 	 */
1587 	ret = wait_event_interruptible_timeout(q->guc->suspend_wait,
1588 					       !READ_ONCE(q->guc->suspend_pending) ||
1589 					       exec_queue_killed(q) ||
1590 					       guc_read_stopped(guc),
1591 					       HZ * 5);
1592 
1593 	if (!ret) {
1594 		xe_gt_warn(guc_to_gt(guc),
1595 			   "Suspend fence, guc_id=%d, failed to respond",
1596 			   q->guc->id);
1597 		/* XXX: Trigger GT reset? */
1598 		return -ETIME;
1599 	}
1600 
1601 	return ret < 0 ? ret : 0;
1602 }
1603 
1604 static void guc_exec_queue_resume(struct xe_exec_queue *q)
1605 {
1606 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1607 	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_RESUME;
1608 	struct xe_guc *guc = exec_queue_to_guc(q);
1609 	struct xe_device *xe = guc_to_xe(guc);
1610 
1611 	xe_assert(xe, !q->guc->suspend_pending);
1612 
1613 	xe_sched_msg_lock(sched);
1614 	guc_exec_queue_try_add_msg(q, msg, RESUME);
1615 	xe_sched_msg_unlock(sched);
1616 }
1617 
1618 static bool guc_exec_queue_reset_status(struct xe_exec_queue *q)
1619 {
1620 	return exec_queue_reset(q) || exec_queue_killed_or_banned_or_wedged(q);
1621 }
1622 
1623 /*
1624  * All of these functions are an abstraction layer which other parts of XE can
1625  * use to trap into the GuC backend. All of these functions, aside from init,
1626  * really shouldn't do much other than trap into the DRM scheduler which
1627  * synchronizes these operations.
1628  */
1629 static const struct xe_exec_queue_ops guc_exec_queue_ops = {
1630 	.init = guc_exec_queue_init,
1631 	.kill = guc_exec_queue_kill,
1632 	.fini = guc_exec_queue_fini,
1633 	.set_priority = guc_exec_queue_set_priority,
1634 	.set_timeslice = guc_exec_queue_set_timeslice,
1635 	.set_preempt_timeout = guc_exec_queue_set_preempt_timeout,
1636 	.suspend = guc_exec_queue_suspend,
1637 	.suspend_wait = guc_exec_queue_suspend_wait,
1638 	.resume = guc_exec_queue_resume,
1639 	.reset_status = guc_exec_queue_reset_status,
1640 };
1641 
1642 static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q)
1643 {
1644 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1645 
1646 	/* Stop scheduling + flush any DRM scheduler operations */
1647 	xe_sched_submission_stop(sched);
1648 
1649 	/* Clean up lost G2H + reset engine state */
1650 	if (exec_queue_registered(q)) {
1651 		if (exec_queue_extra_ref(q) || xe_exec_queue_is_lr(q))
1652 			xe_exec_queue_put(q);
1653 		else if (exec_queue_destroyed(q))
1654 			__guc_exec_queue_fini(guc, q);
1655 	}
1656 	if (q->guc->suspend_pending) {
1657 		set_exec_queue_suspended(q);
1658 		suspend_fence_signal(q);
1659 	}
1660 	atomic_and(EXEC_QUEUE_STATE_WEDGED | EXEC_QUEUE_STATE_BANNED |
1661 		   EXEC_QUEUE_STATE_KILLED | EXEC_QUEUE_STATE_DESTROYED |
1662 		   EXEC_QUEUE_STATE_SUSPENDED,
1663 		   &q->guc->state);
1664 	q->guc->resume_time = 0;
1665 	trace_xe_exec_queue_stop(q);
1666 
1667 	/*
1668 	 * Ban any engine (aside from kernel and engines used for VM ops) with a
1669 	 * started but not complete job or if a job has gone through a GT reset
1670 	 * more than twice.
1671 	 */
1672 	if (!(q->flags & (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM))) {
1673 		struct xe_sched_job *job = xe_sched_first_pending_job(sched);
1674 		bool ban = false;
1675 
1676 		if (job) {
1677 			if ((xe_sched_job_started(job) &&
1678 			    !xe_sched_job_completed(job)) ||
1679 			    xe_sched_invalidate_job(job, 2)) {
1680 				trace_xe_sched_job_ban(job);
1681 				ban = true;
1682 			}
1683 		} else if (xe_exec_queue_is_lr(q) &&
1684 			   (xe_lrc_ring_head(q->lrc[0]) != xe_lrc_ring_tail(q->lrc[0]))) {
1685 			ban = true;
1686 		}
1687 
1688 		if (ban) {
1689 			set_exec_queue_banned(q);
1690 			xe_guc_exec_queue_trigger_cleanup(q);
1691 		}
1692 	}
1693 }
1694 
1695 int xe_guc_submit_reset_prepare(struct xe_guc *guc)
1696 {
1697 	int ret;
1698 
1699 	/*
1700 	 * Using an atomic here rather than submission_state.lock as this
1701 	 * function can be called while holding the CT lock (engine reset
1702 	 * failure). submission_state.lock needs the CT lock to resubmit jobs.
1703 	 * Atomic is not ideal, but it works to prevent against concurrent reset
1704 	 * and releasing any TDRs waiting on guc->submission_state.stopped.
1705 	 */
1706 	ret = atomic_fetch_or(1, &guc->submission_state.stopped);
1707 	smp_wmb();
1708 	wake_up_all(&guc->ct.wq);
1709 
1710 	return ret;
1711 }
1712 
1713 void xe_guc_submit_reset_wait(struct xe_guc *guc)
1714 {
1715 	wait_event(guc->ct.wq, xe_device_wedged(guc_to_xe(guc)) ||
1716 		   !guc_read_stopped(guc));
1717 }
1718 
1719 void xe_guc_submit_stop(struct xe_guc *guc)
1720 {
1721 	struct xe_exec_queue *q;
1722 	unsigned long index;
1723 	struct xe_device *xe = guc_to_xe(guc);
1724 
1725 	xe_assert(xe, guc_read_stopped(guc) == 1);
1726 
1727 	mutex_lock(&guc->submission_state.lock);
1728 
1729 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) {
1730 		/* Prevent redundant attempts to stop parallel queues */
1731 		if (q->guc->id != index)
1732 			continue;
1733 
1734 		guc_exec_queue_stop(guc, q);
1735 	}
1736 
1737 	mutex_unlock(&guc->submission_state.lock);
1738 
1739 	/*
1740 	 * No one can enter the backend at this point, aside from new engine
1741 	 * creation which is protected by guc->submission_state.lock.
1742 	 */
1743 
1744 }
1745 
1746 static void guc_exec_queue_start(struct xe_exec_queue *q)
1747 {
1748 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1749 
1750 	if (!exec_queue_killed_or_banned_or_wedged(q)) {
1751 		int i;
1752 
1753 		trace_xe_exec_queue_resubmit(q);
1754 		for (i = 0; i < q->width; ++i)
1755 			xe_lrc_set_ring_head(q->lrc[i], q->lrc[i]->ring.tail);
1756 		xe_sched_resubmit_jobs(sched);
1757 	}
1758 
1759 	xe_sched_submission_start(sched);
1760 	xe_sched_submission_resume_tdr(sched);
1761 }
1762 
1763 int xe_guc_submit_start(struct xe_guc *guc)
1764 {
1765 	struct xe_exec_queue *q;
1766 	unsigned long index;
1767 	struct xe_device *xe = guc_to_xe(guc);
1768 
1769 	xe_assert(xe, guc_read_stopped(guc) == 1);
1770 
1771 	mutex_lock(&guc->submission_state.lock);
1772 	atomic_dec(&guc->submission_state.stopped);
1773 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) {
1774 		/* Prevent redundant attempts to start parallel queues */
1775 		if (q->guc->id != index)
1776 			continue;
1777 
1778 		guc_exec_queue_start(q);
1779 	}
1780 	mutex_unlock(&guc->submission_state.lock);
1781 
1782 	wake_up_all(&guc->ct.wq);
1783 
1784 	return 0;
1785 }
1786 
1787 static struct xe_exec_queue *
1788 g2h_exec_queue_lookup(struct xe_guc *guc, u32 guc_id)
1789 {
1790 	struct xe_device *xe = guc_to_xe(guc);
1791 	struct xe_exec_queue *q;
1792 
1793 	if (unlikely(guc_id >= GUC_ID_MAX)) {
1794 		drm_err(&xe->drm, "Invalid guc_id %u", guc_id);
1795 		return NULL;
1796 	}
1797 
1798 	q = xa_load(&guc->submission_state.exec_queue_lookup, guc_id);
1799 	if (unlikely(!q)) {
1800 		drm_err(&xe->drm, "Not engine present for guc_id %u", guc_id);
1801 		return NULL;
1802 	}
1803 
1804 	xe_assert(xe, guc_id >= q->guc->id);
1805 	xe_assert(xe, guc_id < (q->guc->id + q->width));
1806 
1807 	return q;
1808 }
1809 
1810 static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
1811 {
1812 	u32 action[] = {
1813 		XE_GUC_ACTION_DEREGISTER_CONTEXT,
1814 		q->guc->id,
1815 	};
1816 
1817 	xe_gt_assert(guc_to_gt(guc), exec_queue_destroyed(q));
1818 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
1819 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
1820 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q));
1821 
1822 	trace_xe_exec_queue_deregister(q);
1823 
1824 	xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action));
1825 }
1826 
1827 static void handle_sched_done(struct xe_guc *guc, struct xe_exec_queue *q,
1828 			      u32 runnable_state)
1829 {
1830 	trace_xe_exec_queue_scheduling_done(q);
1831 
1832 	if (runnable_state == 1) {
1833 		xe_gt_assert(guc_to_gt(guc), exec_queue_pending_enable(q));
1834 
1835 		q->guc->resume_time = ktime_get();
1836 		clear_exec_queue_pending_enable(q);
1837 		smp_wmb();
1838 		wake_up_all(&guc->ct.wq);
1839 	} else {
1840 		bool check_timeout = exec_queue_check_timeout(q);
1841 
1842 		xe_gt_assert(guc_to_gt(guc), runnable_state == 0);
1843 		xe_gt_assert(guc_to_gt(guc), exec_queue_pending_disable(q));
1844 
1845 		clear_exec_queue_pending_disable(q);
1846 		if (q->guc->suspend_pending) {
1847 			suspend_fence_signal(q);
1848 		} else {
1849 			if (exec_queue_banned(q) || check_timeout) {
1850 				smp_wmb();
1851 				wake_up_all(&guc->ct.wq);
1852 			}
1853 			if (!check_timeout)
1854 				deregister_exec_queue(guc, q);
1855 		}
1856 	}
1857 }
1858 
1859 int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
1860 {
1861 	struct xe_device *xe = guc_to_xe(guc);
1862 	struct xe_exec_queue *q;
1863 	u32 guc_id = msg[0];
1864 	u32 runnable_state = msg[1];
1865 
1866 	if (unlikely(len < 2)) {
1867 		drm_err(&xe->drm, "Invalid length %u", len);
1868 		return -EPROTO;
1869 	}
1870 
1871 	q = g2h_exec_queue_lookup(guc, guc_id);
1872 	if (unlikely(!q))
1873 		return -EPROTO;
1874 
1875 	if (unlikely(!exec_queue_pending_enable(q) &&
1876 		     !exec_queue_pending_disable(q))) {
1877 		xe_gt_err(guc_to_gt(guc),
1878 			  "SCHED_DONE: Unexpected engine state 0x%04x, guc_id=%d, runnable_state=%u",
1879 			  atomic_read(&q->guc->state), q->guc->id,
1880 			  runnable_state);
1881 		return -EPROTO;
1882 	}
1883 
1884 	handle_sched_done(guc, q, runnable_state);
1885 
1886 	return 0;
1887 }
1888 
1889 static void handle_deregister_done(struct xe_guc *guc, struct xe_exec_queue *q)
1890 {
1891 	trace_xe_exec_queue_deregister_done(q);
1892 
1893 	clear_exec_queue_registered(q);
1894 
1895 	if (exec_queue_extra_ref(q) || xe_exec_queue_is_lr(q))
1896 		xe_exec_queue_put(q);
1897 	else
1898 		__guc_exec_queue_fini(guc, q);
1899 }
1900 
1901 int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
1902 {
1903 	struct xe_device *xe = guc_to_xe(guc);
1904 	struct xe_exec_queue *q;
1905 	u32 guc_id = msg[0];
1906 
1907 	if (unlikely(len < 1)) {
1908 		drm_err(&xe->drm, "Invalid length %u", len);
1909 		return -EPROTO;
1910 	}
1911 
1912 	q = g2h_exec_queue_lookup(guc, guc_id);
1913 	if (unlikely(!q))
1914 		return -EPROTO;
1915 
1916 	if (!exec_queue_destroyed(q) || exec_queue_pending_disable(q) ||
1917 	    exec_queue_pending_enable(q) || exec_queue_enabled(q)) {
1918 		xe_gt_err(guc_to_gt(guc),
1919 			  "DEREGISTER_DONE: Unexpected engine state 0x%04x, guc_id=%d",
1920 			  atomic_read(&q->guc->state), q->guc->id);
1921 		return -EPROTO;
1922 	}
1923 
1924 	handle_deregister_done(guc, q);
1925 
1926 	return 0;
1927 }
1928 
1929 int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len)
1930 {
1931 	struct xe_gt *gt = guc_to_gt(guc);
1932 	struct xe_device *xe = guc_to_xe(guc);
1933 	struct xe_exec_queue *q;
1934 	u32 guc_id = msg[0];
1935 
1936 	if (unlikely(len < 1)) {
1937 		drm_err(&xe->drm, "Invalid length %u", len);
1938 		return -EPROTO;
1939 	}
1940 
1941 	q = g2h_exec_queue_lookup(guc, guc_id);
1942 	if (unlikely(!q))
1943 		return -EPROTO;
1944 
1945 	xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: 0x%x, guc_id=%d",
1946 		   xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id);
1947 
1948 	/* FIXME: Do error capture, most likely async */
1949 
1950 	trace_xe_exec_queue_reset(q);
1951 
1952 	/*
1953 	 * A banned engine is a NOP at this point (came from
1954 	 * guc_exec_queue_timedout_job). Otherwise, kick drm scheduler to cancel
1955 	 * jobs by setting timeout of the job to the minimum value kicking
1956 	 * guc_exec_queue_timedout_job.
1957 	 */
1958 	set_exec_queue_reset(q);
1959 	if (!exec_queue_banned(q) && !exec_queue_check_timeout(q))
1960 		xe_guc_exec_queue_trigger_cleanup(q);
1961 
1962 	return 0;
1963 }
1964 
1965 int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg,
1966 					       u32 len)
1967 {
1968 	struct xe_gt *gt = guc_to_gt(guc);
1969 	struct xe_device *xe = guc_to_xe(guc);
1970 	struct xe_exec_queue *q;
1971 	u32 guc_id = msg[0];
1972 
1973 	if (unlikely(len < 1)) {
1974 		drm_err(&xe->drm, "Invalid length %u", len);
1975 		return -EPROTO;
1976 	}
1977 
1978 	q = g2h_exec_queue_lookup(guc, guc_id);
1979 	if (unlikely(!q))
1980 		return -EPROTO;
1981 
1982 	xe_gt_dbg(gt, "Engine memory cat error: engine_class=%s, logical_mask: 0x%x, guc_id=%d",
1983 		  xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id);
1984 
1985 	trace_xe_exec_queue_memory_cat_error(q);
1986 
1987 	/* Treat the same as engine reset */
1988 	set_exec_queue_reset(q);
1989 	if (!exec_queue_banned(q) && !exec_queue_check_timeout(q))
1990 		xe_guc_exec_queue_trigger_cleanup(q);
1991 
1992 	return 0;
1993 }
1994 
1995 int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len)
1996 {
1997 	struct xe_device *xe = guc_to_xe(guc);
1998 	u8 guc_class, instance;
1999 	u32 reason;
2000 
2001 	if (unlikely(len != 3)) {
2002 		drm_err(&xe->drm, "Invalid length %u", len);
2003 		return -EPROTO;
2004 	}
2005 
2006 	guc_class = msg[0];
2007 	instance = msg[1];
2008 	reason = msg[2];
2009 
2010 	/* Unexpected failure of a hardware feature, log an actual error */
2011 	drm_err(&xe->drm, "GuC engine reset request failed on %d:%d because 0x%08X",
2012 		guc_class, instance, reason);
2013 
2014 	xe_gt_reset_async(guc_to_gt(guc));
2015 
2016 	return 0;
2017 }
2018 
2019 static void
2020 guc_exec_queue_wq_snapshot_capture(struct xe_exec_queue *q,
2021 				   struct xe_guc_submit_exec_queue_snapshot *snapshot)
2022 {
2023 	struct xe_guc *guc = exec_queue_to_guc(q);
2024 	struct xe_device *xe = guc_to_xe(guc);
2025 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
2026 	int i;
2027 
2028 	snapshot->guc.wqi_head = q->guc->wqi_head;
2029 	snapshot->guc.wqi_tail = q->guc->wqi_tail;
2030 	snapshot->parallel.wq_desc.head = parallel_read(xe, map, wq_desc.head);
2031 	snapshot->parallel.wq_desc.tail = parallel_read(xe, map, wq_desc.tail);
2032 	snapshot->parallel.wq_desc.status = parallel_read(xe, map,
2033 							  wq_desc.wq_status);
2034 
2035 	if (snapshot->parallel.wq_desc.head !=
2036 	    snapshot->parallel.wq_desc.tail) {
2037 		for (i = snapshot->parallel.wq_desc.head;
2038 		     i != snapshot->parallel.wq_desc.tail;
2039 		     i = (i + sizeof(u32)) % WQ_SIZE)
2040 			snapshot->parallel.wq[i / sizeof(u32)] =
2041 				parallel_read(xe, map, wq[i / sizeof(u32)]);
2042 	}
2043 }
2044 
2045 static void
2046 guc_exec_queue_wq_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot,
2047 				 struct drm_printer *p)
2048 {
2049 	int i;
2050 
2051 	drm_printf(p, "\tWQ head: %u (internal), %d (memory)\n",
2052 		   snapshot->guc.wqi_head, snapshot->parallel.wq_desc.head);
2053 	drm_printf(p, "\tWQ tail: %u (internal), %d (memory)\n",
2054 		   snapshot->guc.wqi_tail, snapshot->parallel.wq_desc.tail);
2055 	drm_printf(p, "\tWQ status: %u\n", snapshot->parallel.wq_desc.status);
2056 
2057 	if (snapshot->parallel.wq_desc.head !=
2058 	    snapshot->parallel.wq_desc.tail) {
2059 		for (i = snapshot->parallel.wq_desc.head;
2060 		     i != snapshot->parallel.wq_desc.tail;
2061 		     i = (i + sizeof(u32)) % WQ_SIZE)
2062 			drm_printf(p, "\tWQ[%zu]: 0x%08x\n", i / sizeof(u32),
2063 				   snapshot->parallel.wq[i / sizeof(u32)]);
2064 	}
2065 }
2066 
2067 /**
2068  * xe_guc_exec_queue_snapshot_capture - Take a quick snapshot of the GuC Engine.
2069  * @q: faulty exec queue
2070  *
2071  * This can be printed out in a later stage like during dev_coredump
2072  * analysis.
2073  *
2074  * Returns: a GuC Submit Engine snapshot object that must be freed by the
2075  * caller, using `xe_guc_exec_queue_snapshot_free`.
2076  */
2077 struct xe_guc_submit_exec_queue_snapshot *
2078 xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q)
2079 {
2080 	struct xe_gpu_scheduler *sched = &q->guc->sched;
2081 	struct xe_guc_submit_exec_queue_snapshot *snapshot;
2082 	int i;
2083 
2084 	snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC);
2085 
2086 	if (!snapshot)
2087 		return NULL;
2088 
2089 	snapshot->guc.id = q->guc->id;
2090 	memcpy(&snapshot->name, &q->name, sizeof(snapshot->name));
2091 	snapshot->class = q->class;
2092 	snapshot->logical_mask = q->logical_mask;
2093 	snapshot->width = q->width;
2094 	snapshot->refcount = kref_read(&q->refcount);
2095 	snapshot->sched_timeout = sched->base.timeout;
2096 	snapshot->sched_props.timeslice_us = q->sched_props.timeslice_us;
2097 	snapshot->sched_props.preempt_timeout_us =
2098 		q->sched_props.preempt_timeout_us;
2099 
2100 	snapshot->lrc = kmalloc_array(q->width, sizeof(struct xe_lrc_snapshot *),
2101 				      GFP_ATOMIC);
2102 
2103 	if (snapshot->lrc) {
2104 		for (i = 0; i < q->width; ++i) {
2105 			struct xe_lrc *lrc = q->lrc[i];
2106 
2107 			snapshot->lrc[i] = xe_lrc_snapshot_capture(lrc);
2108 		}
2109 	}
2110 
2111 	snapshot->schedule_state = atomic_read(&q->guc->state);
2112 	snapshot->exec_queue_flags = q->flags;
2113 
2114 	snapshot->parallel_execution = xe_exec_queue_is_parallel(q);
2115 	if (snapshot->parallel_execution)
2116 		guc_exec_queue_wq_snapshot_capture(q, snapshot);
2117 
2118 	spin_lock(&sched->base.job_list_lock);
2119 	snapshot->pending_list_size = list_count_nodes(&sched->base.pending_list);
2120 	snapshot->pending_list = kmalloc_array(snapshot->pending_list_size,
2121 					       sizeof(struct pending_list_snapshot),
2122 					       GFP_ATOMIC);
2123 
2124 	if (snapshot->pending_list) {
2125 		struct xe_sched_job *job_iter;
2126 
2127 		i = 0;
2128 		list_for_each_entry(job_iter, &sched->base.pending_list, drm.list) {
2129 			snapshot->pending_list[i].seqno =
2130 				xe_sched_job_seqno(job_iter);
2131 			snapshot->pending_list[i].fence =
2132 				dma_fence_is_signaled(job_iter->fence) ? 1 : 0;
2133 			snapshot->pending_list[i].finished =
2134 				dma_fence_is_signaled(&job_iter->drm.s_fence->finished)
2135 				? 1 : 0;
2136 			i++;
2137 		}
2138 	}
2139 
2140 	spin_unlock(&sched->base.job_list_lock);
2141 
2142 	return snapshot;
2143 }
2144 
2145 /**
2146  * xe_guc_exec_queue_snapshot_capture_delayed - Take delayed part of snapshot of the GuC Engine.
2147  * @snapshot: Previously captured snapshot of job.
2148  *
2149  * This captures some data that requires taking some locks, so it cannot be done in signaling path.
2150  */
2151 void
2152 xe_guc_exec_queue_snapshot_capture_delayed(struct xe_guc_submit_exec_queue_snapshot *snapshot)
2153 {
2154 	int i;
2155 
2156 	if (!snapshot || !snapshot->lrc)
2157 		return;
2158 
2159 	for (i = 0; i < snapshot->width; ++i)
2160 		xe_lrc_snapshot_capture_delayed(snapshot->lrc[i]);
2161 }
2162 
2163 /**
2164  * xe_guc_exec_queue_snapshot_print - Print out a given GuC Engine snapshot.
2165  * @snapshot: GuC Submit Engine snapshot object.
2166  * @p: drm_printer where it will be printed out.
2167  *
2168  * This function prints out a given GuC Submit Engine snapshot object.
2169  */
2170 void
2171 xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot,
2172 				 struct drm_printer *p)
2173 {
2174 	int i;
2175 
2176 	if (!snapshot)
2177 		return;
2178 
2179 	drm_printf(p, "\nGuC ID: %d\n", snapshot->guc.id);
2180 	drm_printf(p, "\tName: %s\n", snapshot->name);
2181 	drm_printf(p, "\tClass: %d\n", snapshot->class);
2182 	drm_printf(p, "\tLogical mask: 0x%x\n", snapshot->logical_mask);
2183 	drm_printf(p, "\tWidth: %d\n", snapshot->width);
2184 	drm_printf(p, "\tRef: %d\n", snapshot->refcount);
2185 	drm_printf(p, "\tTimeout: %ld (ms)\n", snapshot->sched_timeout);
2186 	drm_printf(p, "\tTimeslice: %u (us)\n",
2187 		   snapshot->sched_props.timeslice_us);
2188 	drm_printf(p, "\tPreempt timeout: %u (us)\n",
2189 		   snapshot->sched_props.preempt_timeout_us);
2190 
2191 	for (i = 0; snapshot->lrc && i < snapshot->width; ++i)
2192 		xe_lrc_snapshot_print(snapshot->lrc[i], p);
2193 
2194 	drm_printf(p, "\tSchedule State: 0x%x\n", snapshot->schedule_state);
2195 	drm_printf(p, "\tFlags: 0x%lx\n", snapshot->exec_queue_flags);
2196 
2197 	if (snapshot->parallel_execution)
2198 		guc_exec_queue_wq_snapshot_print(snapshot, p);
2199 
2200 	for (i = 0; snapshot->pending_list && i < snapshot->pending_list_size;
2201 	     i++)
2202 		drm_printf(p, "\tJob: seqno=%d, fence=%d, finished=%d\n",
2203 			   snapshot->pending_list[i].seqno,
2204 			   snapshot->pending_list[i].fence,
2205 			   snapshot->pending_list[i].finished);
2206 }
2207 
2208 /**
2209  * xe_guc_exec_queue_snapshot_free - Free all allocated objects for a given
2210  * snapshot.
2211  * @snapshot: GuC Submit Engine snapshot object.
2212  *
2213  * This function free all the memory that needed to be allocated at capture
2214  * time.
2215  */
2216 void xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot)
2217 {
2218 	int i;
2219 
2220 	if (!snapshot)
2221 		return;
2222 
2223 	if (snapshot->lrc) {
2224 		for (i = 0; i < snapshot->width; i++)
2225 			xe_lrc_snapshot_free(snapshot->lrc[i]);
2226 		kfree(snapshot->lrc);
2227 	}
2228 	kfree(snapshot->pending_list);
2229 	kfree(snapshot);
2230 }
2231 
2232 static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p)
2233 {
2234 	struct xe_guc_submit_exec_queue_snapshot *snapshot;
2235 
2236 	snapshot = xe_guc_exec_queue_snapshot_capture(q);
2237 	xe_guc_exec_queue_snapshot_print(snapshot, p);
2238 	xe_guc_exec_queue_snapshot_free(snapshot);
2239 }
2240 
2241 /**
2242  * xe_guc_submit_print - GuC Submit Print.
2243  * @guc: GuC.
2244  * @p: drm_printer where it will be printed out.
2245  *
2246  * This function capture and prints snapshots of **all** GuC Engines.
2247  */
2248 void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p)
2249 {
2250 	struct xe_exec_queue *q;
2251 	unsigned long index;
2252 
2253 	if (!xe_device_uc_enabled(guc_to_xe(guc)))
2254 		return;
2255 
2256 	mutex_lock(&guc->submission_state.lock);
2257 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
2258 		guc_exec_queue_print(q, p);
2259 	mutex_unlock(&guc->submission_state.lock);
2260 }
2261