1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc_submit.h" 7 8 #include <linux/bitfield.h> 9 #include <linux/bitmap.h> 10 #include <linux/circ_buf.h> 11 #include <linux/delay.h> 12 #include <linux/dma-fence-array.h> 13 #include <linux/math64.h> 14 15 #include <drm/drm_managed.h> 16 17 #include "abi/guc_actions_abi.h" 18 #include "abi/guc_actions_slpc_abi.h" 19 #include "abi/guc_klvs_abi.h" 20 #include "regs/xe_lrc_layout.h" 21 #include "xe_assert.h" 22 #include "xe_devcoredump.h" 23 #include "xe_device.h" 24 #include "xe_exec_queue.h" 25 #include "xe_force_wake.h" 26 #include "xe_gpu_scheduler.h" 27 #include "xe_gt.h" 28 #include "xe_gt_clock.h" 29 #include "xe_gt_printk.h" 30 #include "xe_guc.h" 31 #include "xe_guc_capture.h" 32 #include "xe_guc_ct.h" 33 #include "xe_guc_exec_queue_types.h" 34 #include "xe_guc_id_mgr.h" 35 #include "xe_guc_submit_types.h" 36 #include "xe_hw_engine.h" 37 #include "xe_hw_fence.h" 38 #include "xe_lrc.h" 39 #include "xe_macros.h" 40 #include "xe_map.h" 41 #include "xe_mocs.h" 42 #include "xe_pm.h" 43 #include "xe_ring_ops_types.h" 44 #include "xe_sched_job.h" 45 #include "xe_trace.h" 46 #include "xe_vm.h" 47 48 static struct xe_guc * 49 exec_queue_to_guc(struct xe_exec_queue *q) 50 { 51 return &q->gt->uc.guc; 52 } 53 54 /* 55 * Helpers for engine state, using an atomic as some of the bits can transition 56 * as the same time (e.g. a suspend can be happning at the same time as schedule 57 * engine done being processed). 58 */ 59 #define EXEC_QUEUE_STATE_REGISTERED (1 << 0) 60 #define EXEC_QUEUE_STATE_ENABLED (1 << 1) 61 #define EXEC_QUEUE_STATE_PENDING_ENABLE (1 << 2) 62 #define EXEC_QUEUE_STATE_PENDING_DISABLE (1 << 3) 63 #define EXEC_QUEUE_STATE_DESTROYED (1 << 4) 64 #define EXEC_QUEUE_STATE_SUSPENDED (1 << 5) 65 #define EXEC_QUEUE_STATE_RESET (1 << 6) 66 #define EXEC_QUEUE_STATE_KILLED (1 << 7) 67 #define EXEC_QUEUE_STATE_WEDGED (1 << 8) 68 #define EXEC_QUEUE_STATE_BANNED (1 << 9) 69 #define EXEC_QUEUE_STATE_CHECK_TIMEOUT (1 << 10) 70 #define EXEC_QUEUE_STATE_EXTRA_REF (1 << 11) 71 72 static bool exec_queue_registered(struct xe_exec_queue *q) 73 { 74 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_REGISTERED; 75 } 76 77 static void set_exec_queue_registered(struct xe_exec_queue *q) 78 { 79 atomic_or(EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); 80 } 81 82 static void clear_exec_queue_registered(struct xe_exec_queue *q) 83 { 84 atomic_and(~EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); 85 } 86 87 static bool exec_queue_enabled(struct xe_exec_queue *q) 88 { 89 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_ENABLED; 90 } 91 92 static void set_exec_queue_enabled(struct xe_exec_queue *q) 93 { 94 atomic_or(EXEC_QUEUE_STATE_ENABLED, &q->guc->state); 95 } 96 97 static void clear_exec_queue_enabled(struct xe_exec_queue *q) 98 { 99 atomic_and(~EXEC_QUEUE_STATE_ENABLED, &q->guc->state); 100 } 101 102 static bool exec_queue_pending_enable(struct xe_exec_queue *q) 103 { 104 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_ENABLE; 105 } 106 107 static void set_exec_queue_pending_enable(struct xe_exec_queue *q) 108 { 109 atomic_or(EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state); 110 } 111 112 static void clear_exec_queue_pending_enable(struct xe_exec_queue *q) 113 { 114 atomic_and(~EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state); 115 } 116 117 static bool exec_queue_pending_disable(struct xe_exec_queue *q) 118 { 119 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_DISABLE; 120 } 121 122 static void set_exec_queue_pending_disable(struct xe_exec_queue *q) 123 { 124 atomic_or(EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state); 125 } 126 127 static void clear_exec_queue_pending_disable(struct xe_exec_queue *q) 128 { 129 atomic_and(~EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state); 130 } 131 132 static bool exec_queue_destroyed(struct xe_exec_queue *q) 133 { 134 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_DESTROYED; 135 } 136 137 static void set_exec_queue_destroyed(struct xe_exec_queue *q) 138 { 139 atomic_or(EXEC_QUEUE_STATE_DESTROYED, &q->guc->state); 140 } 141 142 static bool exec_queue_banned(struct xe_exec_queue *q) 143 { 144 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_BANNED; 145 } 146 147 static void set_exec_queue_banned(struct xe_exec_queue *q) 148 { 149 atomic_or(EXEC_QUEUE_STATE_BANNED, &q->guc->state); 150 } 151 152 static bool exec_queue_suspended(struct xe_exec_queue *q) 153 { 154 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_SUSPENDED; 155 } 156 157 static void set_exec_queue_suspended(struct xe_exec_queue *q) 158 { 159 atomic_or(EXEC_QUEUE_STATE_SUSPENDED, &q->guc->state); 160 } 161 162 static void clear_exec_queue_suspended(struct xe_exec_queue *q) 163 { 164 atomic_and(~EXEC_QUEUE_STATE_SUSPENDED, &q->guc->state); 165 } 166 167 static bool exec_queue_reset(struct xe_exec_queue *q) 168 { 169 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_RESET; 170 } 171 172 static void set_exec_queue_reset(struct xe_exec_queue *q) 173 { 174 atomic_or(EXEC_QUEUE_STATE_RESET, &q->guc->state); 175 } 176 177 static bool exec_queue_killed(struct xe_exec_queue *q) 178 { 179 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_KILLED; 180 } 181 182 static void set_exec_queue_killed(struct xe_exec_queue *q) 183 { 184 atomic_or(EXEC_QUEUE_STATE_KILLED, &q->guc->state); 185 } 186 187 static bool exec_queue_wedged(struct xe_exec_queue *q) 188 { 189 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_WEDGED; 190 } 191 192 static void set_exec_queue_wedged(struct xe_exec_queue *q) 193 { 194 atomic_or(EXEC_QUEUE_STATE_WEDGED, &q->guc->state); 195 } 196 197 static bool exec_queue_check_timeout(struct xe_exec_queue *q) 198 { 199 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_CHECK_TIMEOUT; 200 } 201 202 static void set_exec_queue_check_timeout(struct xe_exec_queue *q) 203 { 204 atomic_or(EXEC_QUEUE_STATE_CHECK_TIMEOUT, &q->guc->state); 205 } 206 207 static void clear_exec_queue_check_timeout(struct xe_exec_queue *q) 208 { 209 atomic_and(~EXEC_QUEUE_STATE_CHECK_TIMEOUT, &q->guc->state); 210 } 211 212 static bool exec_queue_extra_ref(struct xe_exec_queue *q) 213 { 214 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_EXTRA_REF; 215 } 216 217 static void set_exec_queue_extra_ref(struct xe_exec_queue *q) 218 { 219 atomic_or(EXEC_QUEUE_STATE_EXTRA_REF, &q->guc->state); 220 } 221 222 static bool exec_queue_killed_or_banned_or_wedged(struct xe_exec_queue *q) 223 { 224 return (atomic_read(&q->guc->state) & 225 (EXEC_QUEUE_STATE_WEDGED | EXEC_QUEUE_STATE_KILLED | 226 EXEC_QUEUE_STATE_BANNED)); 227 } 228 229 static void guc_submit_fini(struct drm_device *drm, void *arg) 230 { 231 struct xe_guc *guc = arg; 232 struct xe_device *xe = guc_to_xe(guc); 233 struct xe_gt *gt = guc_to_gt(guc); 234 int ret; 235 236 ret = wait_event_timeout(guc->submission_state.fini_wq, 237 xa_empty(&guc->submission_state.exec_queue_lookup), 238 HZ * 5); 239 240 drain_workqueue(xe->destroy_wq); 241 242 xe_gt_assert(gt, ret); 243 244 xa_destroy(&guc->submission_state.exec_queue_lookup); 245 } 246 247 static void guc_submit_wedged_fini(void *arg) 248 { 249 struct xe_guc *guc = arg; 250 struct xe_exec_queue *q; 251 unsigned long index; 252 253 mutex_lock(&guc->submission_state.lock); 254 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) { 255 if (exec_queue_wedged(q)) { 256 mutex_unlock(&guc->submission_state.lock); 257 xe_exec_queue_put(q); 258 mutex_lock(&guc->submission_state.lock); 259 } 260 } 261 mutex_unlock(&guc->submission_state.lock); 262 } 263 264 static const struct xe_exec_queue_ops guc_exec_queue_ops; 265 266 static void primelockdep(struct xe_guc *guc) 267 { 268 if (!IS_ENABLED(CONFIG_LOCKDEP)) 269 return; 270 271 fs_reclaim_acquire(GFP_KERNEL); 272 273 mutex_lock(&guc->submission_state.lock); 274 mutex_unlock(&guc->submission_state.lock); 275 276 fs_reclaim_release(GFP_KERNEL); 277 } 278 279 /** 280 * xe_guc_submit_init() - Initialize GuC submission. 281 * @guc: the &xe_guc to initialize 282 * @num_ids: number of GuC context IDs to use 283 * 284 * The bare-metal or PF driver can pass ~0 as &num_ids to indicate that all 285 * GuC context IDs supported by the GuC firmware should be used for submission. 286 * 287 * Only VF drivers will have to provide explicit number of GuC context IDs 288 * that they can use for submission. 289 * 290 * Return: 0 on success or a negative error code on failure. 291 */ 292 int xe_guc_submit_init(struct xe_guc *guc, unsigned int num_ids) 293 { 294 struct xe_device *xe = guc_to_xe(guc); 295 struct xe_gt *gt = guc_to_gt(guc); 296 int err; 297 298 err = drmm_mutex_init(&xe->drm, &guc->submission_state.lock); 299 if (err) 300 return err; 301 302 err = xe_guc_id_mgr_init(&guc->submission_state.idm, num_ids); 303 if (err) 304 return err; 305 306 gt->exec_queue_ops = &guc_exec_queue_ops; 307 308 xa_init(&guc->submission_state.exec_queue_lookup); 309 310 init_waitqueue_head(&guc->submission_state.fini_wq); 311 312 primelockdep(guc); 313 314 guc->submission_state.initialized = true; 315 316 return drmm_add_action_or_reset(&xe->drm, guc_submit_fini, guc); 317 } 318 319 static void __release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q, u32 xa_count) 320 { 321 int i; 322 323 lockdep_assert_held(&guc->submission_state.lock); 324 325 for (i = 0; i < xa_count; ++i) 326 xa_erase(&guc->submission_state.exec_queue_lookup, q->guc->id + i); 327 328 xe_guc_id_mgr_release_locked(&guc->submission_state.idm, 329 q->guc->id, q->width); 330 331 if (xa_empty(&guc->submission_state.exec_queue_lookup)) 332 wake_up(&guc->submission_state.fini_wq); 333 } 334 335 static int alloc_guc_id(struct xe_guc *guc, struct xe_exec_queue *q) 336 { 337 int ret; 338 int i; 339 340 /* 341 * Must use GFP_NOWAIT as this lock is in the dma fence signalling path, 342 * worse case user gets -ENOMEM on engine create and has to try again. 343 * 344 * FIXME: Have caller pre-alloc or post-alloc /w GFP_KERNEL to prevent 345 * failure. 346 */ 347 lockdep_assert_held(&guc->submission_state.lock); 348 349 ret = xe_guc_id_mgr_reserve_locked(&guc->submission_state.idm, 350 q->width); 351 if (ret < 0) 352 return ret; 353 354 q->guc->id = ret; 355 356 for (i = 0; i < q->width; ++i) { 357 ret = xa_err(xa_store(&guc->submission_state.exec_queue_lookup, 358 q->guc->id + i, q, GFP_NOWAIT)); 359 if (ret) 360 goto err_release; 361 } 362 363 return 0; 364 365 err_release: 366 __release_guc_id(guc, q, i); 367 368 return ret; 369 } 370 371 static void release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q) 372 { 373 mutex_lock(&guc->submission_state.lock); 374 __release_guc_id(guc, q, q->width); 375 mutex_unlock(&guc->submission_state.lock); 376 } 377 378 struct exec_queue_policy { 379 u32 count; 380 struct guc_update_exec_queue_policy h2g; 381 }; 382 383 static u32 __guc_exec_queue_policy_action_size(struct exec_queue_policy *policy) 384 { 385 size_t bytes = sizeof(policy->h2g.header) + 386 (sizeof(policy->h2g.klv[0]) * policy->count); 387 388 return bytes / sizeof(u32); 389 } 390 391 static void __guc_exec_queue_policy_start_klv(struct exec_queue_policy *policy, 392 u16 guc_id) 393 { 394 policy->h2g.header.action = 395 XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES; 396 policy->h2g.header.guc_id = guc_id; 397 policy->count = 0; 398 } 399 400 #define MAKE_EXEC_QUEUE_POLICY_ADD(func, id) \ 401 static void __guc_exec_queue_policy_add_##func(struct exec_queue_policy *policy, \ 402 u32 data) \ 403 { \ 404 XE_WARN_ON(policy->count >= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \ 405 \ 406 policy->h2g.klv[policy->count].kl = \ 407 FIELD_PREP(GUC_KLV_0_KEY, \ 408 GUC_CONTEXT_POLICIES_KLV_ID_##id) | \ 409 FIELD_PREP(GUC_KLV_0_LEN, 1); \ 410 policy->h2g.klv[policy->count].value = data; \ 411 policy->count++; \ 412 } 413 414 MAKE_EXEC_QUEUE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM) 415 MAKE_EXEC_QUEUE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT) 416 MAKE_EXEC_QUEUE_POLICY_ADD(priority, SCHEDULING_PRIORITY) 417 MAKE_EXEC_QUEUE_POLICY_ADD(slpc_exec_queue_freq_req, SLPM_GT_FREQUENCY) 418 #undef MAKE_EXEC_QUEUE_POLICY_ADD 419 420 static const int xe_exec_queue_prio_to_guc[] = { 421 [XE_EXEC_QUEUE_PRIORITY_LOW] = GUC_CLIENT_PRIORITY_NORMAL, 422 [XE_EXEC_QUEUE_PRIORITY_NORMAL] = GUC_CLIENT_PRIORITY_KMD_NORMAL, 423 [XE_EXEC_QUEUE_PRIORITY_HIGH] = GUC_CLIENT_PRIORITY_HIGH, 424 [XE_EXEC_QUEUE_PRIORITY_KERNEL] = GUC_CLIENT_PRIORITY_KMD_HIGH, 425 }; 426 427 static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q) 428 { 429 struct exec_queue_policy policy; 430 enum xe_exec_queue_priority prio = q->sched_props.priority; 431 u32 timeslice_us = q->sched_props.timeslice_us; 432 u32 slpc_exec_queue_freq_req = 0; 433 u32 preempt_timeout_us = q->sched_props.preempt_timeout_us; 434 435 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 436 437 if (q->flags & EXEC_QUEUE_FLAG_LOW_LATENCY) 438 slpc_exec_queue_freq_req |= SLPC_CTX_FREQ_REQ_IS_COMPUTE; 439 440 __guc_exec_queue_policy_start_klv(&policy, q->guc->id); 441 __guc_exec_queue_policy_add_priority(&policy, xe_exec_queue_prio_to_guc[prio]); 442 __guc_exec_queue_policy_add_execution_quantum(&policy, timeslice_us); 443 __guc_exec_queue_policy_add_preemption_timeout(&policy, preempt_timeout_us); 444 __guc_exec_queue_policy_add_slpc_exec_queue_freq_req(&policy, 445 slpc_exec_queue_freq_req); 446 447 xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g, 448 __guc_exec_queue_policy_action_size(&policy), 0, 0); 449 } 450 451 static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue *q) 452 { 453 struct exec_queue_policy policy; 454 455 __guc_exec_queue_policy_start_klv(&policy, q->guc->id); 456 __guc_exec_queue_policy_add_preemption_timeout(&policy, 1); 457 458 xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g, 459 __guc_exec_queue_policy_action_size(&policy), 0, 0); 460 } 461 462 #define parallel_read(xe_, map_, field_) \ 463 xe_map_rd_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \ 464 field_) 465 #define parallel_write(xe_, map_, field_, val_) \ 466 xe_map_wr_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \ 467 field_, val_) 468 469 static void __register_mlrc_exec_queue(struct xe_guc *guc, 470 struct xe_exec_queue *q, 471 struct guc_ctxt_registration_info *info) 472 { 473 #define MAX_MLRC_REG_SIZE (13 + XE_HW_ENGINE_MAX_INSTANCE * 2) 474 u32 action[MAX_MLRC_REG_SIZE]; 475 int len = 0; 476 int i; 477 478 xe_gt_assert(guc_to_gt(guc), xe_exec_queue_is_parallel(q)); 479 480 action[len++] = XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC; 481 action[len++] = info->flags; 482 action[len++] = info->context_idx; 483 action[len++] = info->engine_class; 484 action[len++] = info->engine_submit_mask; 485 action[len++] = info->wq_desc_lo; 486 action[len++] = info->wq_desc_hi; 487 action[len++] = info->wq_base_lo; 488 action[len++] = info->wq_base_hi; 489 action[len++] = info->wq_size; 490 action[len++] = q->width; 491 action[len++] = info->hwlrca_lo; 492 action[len++] = info->hwlrca_hi; 493 494 for (i = 1; i < q->width; ++i) { 495 struct xe_lrc *lrc = q->lrc[i]; 496 497 action[len++] = lower_32_bits(xe_lrc_descriptor(lrc)); 498 action[len++] = upper_32_bits(xe_lrc_descriptor(lrc)); 499 } 500 501 xe_gt_assert(guc_to_gt(guc), len <= MAX_MLRC_REG_SIZE); 502 #undef MAX_MLRC_REG_SIZE 503 504 xe_guc_ct_send(&guc->ct, action, len, 0, 0); 505 } 506 507 static void __register_exec_queue(struct xe_guc *guc, 508 struct guc_ctxt_registration_info *info) 509 { 510 u32 action[] = { 511 XE_GUC_ACTION_REGISTER_CONTEXT, 512 info->flags, 513 info->context_idx, 514 info->engine_class, 515 info->engine_submit_mask, 516 info->wq_desc_lo, 517 info->wq_desc_hi, 518 info->wq_base_lo, 519 info->wq_base_hi, 520 info->wq_size, 521 info->hwlrca_lo, 522 info->hwlrca_hi, 523 }; 524 525 xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0); 526 } 527 528 static void register_exec_queue(struct xe_exec_queue *q) 529 { 530 struct xe_guc *guc = exec_queue_to_guc(q); 531 struct xe_device *xe = guc_to_xe(guc); 532 struct xe_lrc *lrc = q->lrc[0]; 533 struct guc_ctxt_registration_info info; 534 535 xe_gt_assert(guc_to_gt(guc), !exec_queue_registered(q)); 536 537 memset(&info, 0, sizeof(info)); 538 info.context_idx = q->guc->id; 539 info.engine_class = xe_engine_class_to_guc_class(q->class); 540 info.engine_submit_mask = q->logical_mask; 541 info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc)); 542 info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc)); 543 info.flags = CONTEXT_REGISTRATION_FLAG_KMD; 544 545 if (xe_exec_queue_is_parallel(q)) { 546 u64 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc); 547 struct iosys_map map = xe_lrc_parallel_map(lrc); 548 549 info.wq_desc_lo = lower_32_bits(ggtt_addr + 550 offsetof(struct guc_submit_parallel_scratch, wq_desc)); 551 info.wq_desc_hi = upper_32_bits(ggtt_addr + 552 offsetof(struct guc_submit_parallel_scratch, wq_desc)); 553 info.wq_base_lo = lower_32_bits(ggtt_addr + 554 offsetof(struct guc_submit_parallel_scratch, wq[0])); 555 info.wq_base_hi = upper_32_bits(ggtt_addr + 556 offsetof(struct guc_submit_parallel_scratch, wq[0])); 557 info.wq_size = WQ_SIZE; 558 559 q->guc->wqi_head = 0; 560 q->guc->wqi_tail = 0; 561 xe_map_memset(xe, &map, 0, 0, PARALLEL_SCRATCH_SIZE - WQ_SIZE); 562 parallel_write(xe, map, wq_desc.wq_status, WQ_STATUS_ACTIVE); 563 } 564 565 /* 566 * We must keep a reference for LR engines if engine is registered with 567 * the GuC as jobs signal immediately and can't destroy an engine if the 568 * GuC has a reference to it. 569 */ 570 if (xe_exec_queue_is_lr(q)) 571 xe_exec_queue_get(q); 572 573 set_exec_queue_registered(q); 574 trace_xe_exec_queue_register(q); 575 if (xe_exec_queue_is_parallel(q)) 576 __register_mlrc_exec_queue(guc, q, &info); 577 else 578 __register_exec_queue(guc, &info); 579 init_policies(guc, q); 580 } 581 582 static u32 wq_space_until_wrap(struct xe_exec_queue *q) 583 { 584 return (WQ_SIZE - q->guc->wqi_tail); 585 } 586 587 static int wq_wait_for_space(struct xe_exec_queue *q, u32 wqi_size) 588 { 589 struct xe_guc *guc = exec_queue_to_guc(q); 590 struct xe_device *xe = guc_to_xe(guc); 591 struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]); 592 unsigned int sleep_period_ms = 1; 593 594 #define AVAILABLE_SPACE \ 595 CIRC_SPACE(q->guc->wqi_tail, q->guc->wqi_head, WQ_SIZE) 596 if (wqi_size > AVAILABLE_SPACE) { 597 try_again: 598 q->guc->wqi_head = parallel_read(xe, map, wq_desc.head); 599 if (wqi_size > AVAILABLE_SPACE) { 600 if (sleep_period_ms == 1024) { 601 xe_gt_reset_async(q->gt); 602 return -ENODEV; 603 } 604 605 msleep(sleep_period_ms); 606 sleep_period_ms <<= 1; 607 goto try_again; 608 } 609 } 610 #undef AVAILABLE_SPACE 611 612 return 0; 613 } 614 615 static int wq_noop_append(struct xe_exec_queue *q) 616 { 617 struct xe_guc *guc = exec_queue_to_guc(q); 618 struct xe_device *xe = guc_to_xe(guc); 619 struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]); 620 u32 len_dw = wq_space_until_wrap(q) / sizeof(u32) - 1; 621 622 if (wq_wait_for_space(q, wq_space_until_wrap(q))) 623 return -ENODEV; 624 625 xe_gt_assert(guc_to_gt(guc), FIELD_FIT(WQ_LEN_MASK, len_dw)); 626 627 parallel_write(xe, map, wq[q->guc->wqi_tail / sizeof(u32)], 628 FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_NOOP) | 629 FIELD_PREP(WQ_LEN_MASK, len_dw)); 630 q->guc->wqi_tail = 0; 631 632 return 0; 633 } 634 635 static void wq_item_append(struct xe_exec_queue *q) 636 { 637 struct xe_guc *guc = exec_queue_to_guc(q); 638 struct xe_device *xe = guc_to_xe(guc); 639 struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]); 640 #define WQ_HEADER_SIZE 4 /* Includes 1 LRC address too */ 641 u32 wqi[XE_HW_ENGINE_MAX_INSTANCE + (WQ_HEADER_SIZE - 1)]; 642 u32 wqi_size = (q->width + (WQ_HEADER_SIZE - 1)) * sizeof(u32); 643 u32 len_dw = (wqi_size / sizeof(u32)) - 1; 644 int i = 0, j; 645 646 if (wqi_size > wq_space_until_wrap(q)) { 647 if (wq_noop_append(q)) 648 return; 649 } 650 if (wq_wait_for_space(q, wqi_size)) 651 return; 652 653 wqi[i++] = FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_MULTI_LRC) | 654 FIELD_PREP(WQ_LEN_MASK, len_dw); 655 wqi[i++] = xe_lrc_descriptor(q->lrc[0]); 656 wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, q->guc->id) | 657 FIELD_PREP(WQ_RING_TAIL_MASK, q->lrc[0]->ring.tail / sizeof(u64)); 658 wqi[i++] = 0; 659 for (j = 1; j < q->width; ++j) { 660 struct xe_lrc *lrc = q->lrc[j]; 661 662 wqi[i++] = lrc->ring.tail / sizeof(u64); 663 } 664 665 xe_gt_assert(guc_to_gt(guc), i == wqi_size / sizeof(u32)); 666 667 iosys_map_incr(&map, offsetof(struct guc_submit_parallel_scratch, 668 wq[q->guc->wqi_tail / sizeof(u32)])); 669 xe_map_memcpy_to(xe, &map, 0, wqi, wqi_size); 670 q->guc->wqi_tail += wqi_size; 671 xe_gt_assert(guc_to_gt(guc), q->guc->wqi_tail <= WQ_SIZE); 672 673 xe_device_wmb(xe); 674 675 map = xe_lrc_parallel_map(q->lrc[0]); 676 parallel_write(xe, map, wq_desc.tail, q->guc->wqi_tail); 677 } 678 679 #define RESUME_PENDING ~0x0ull 680 static void submit_exec_queue(struct xe_exec_queue *q) 681 { 682 struct xe_guc *guc = exec_queue_to_guc(q); 683 struct xe_lrc *lrc = q->lrc[0]; 684 u32 action[3]; 685 u32 g2h_len = 0; 686 u32 num_g2h = 0; 687 int len = 0; 688 bool extra_submit = false; 689 690 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 691 692 if (xe_exec_queue_is_parallel(q)) 693 wq_item_append(q); 694 else 695 xe_lrc_set_ring_tail(lrc, lrc->ring.tail); 696 697 if (exec_queue_suspended(q) && !xe_exec_queue_is_parallel(q)) 698 return; 699 700 if (!exec_queue_enabled(q) && !exec_queue_suspended(q)) { 701 action[len++] = XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET; 702 action[len++] = q->guc->id; 703 action[len++] = GUC_CONTEXT_ENABLE; 704 g2h_len = G2H_LEN_DW_SCHED_CONTEXT_MODE_SET; 705 num_g2h = 1; 706 if (xe_exec_queue_is_parallel(q)) 707 extra_submit = true; 708 709 q->guc->resume_time = RESUME_PENDING; 710 set_exec_queue_pending_enable(q); 711 set_exec_queue_enabled(q); 712 trace_xe_exec_queue_scheduling_enable(q); 713 } else { 714 action[len++] = XE_GUC_ACTION_SCHED_CONTEXT; 715 action[len++] = q->guc->id; 716 trace_xe_exec_queue_submit(q); 717 } 718 719 xe_guc_ct_send(&guc->ct, action, len, g2h_len, num_g2h); 720 721 if (extra_submit) { 722 len = 0; 723 action[len++] = XE_GUC_ACTION_SCHED_CONTEXT; 724 action[len++] = q->guc->id; 725 trace_xe_exec_queue_submit(q); 726 727 xe_guc_ct_send(&guc->ct, action, len, 0, 0); 728 } 729 } 730 731 static struct dma_fence * 732 guc_exec_queue_run_job(struct drm_sched_job *drm_job) 733 { 734 struct xe_sched_job *job = to_xe_sched_job(drm_job); 735 struct xe_exec_queue *q = job->q; 736 struct xe_guc *guc = exec_queue_to_guc(q); 737 struct dma_fence *fence = NULL; 738 bool lr = xe_exec_queue_is_lr(q); 739 740 xe_gt_assert(guc_to_gt(guc), !(exec_queue_destroyed(q) || exec_queue_pending_disable(q)) || 741 exec_queue_banned(q) || exec_queue_suspended(q)); 742 743 trace_xe_sched_job_run(job); 744 745 if (!exec_queue_killed_or_banned_or_wedged(q) && !xe_sched_job_is_error(job)) { 746 if (!exec_queue_registered(q)) 747 register_exec_queue(q); 748 if (!lr) /* LR jobs are emitted in the exec IOCTL */ 749 q->ring_ops->emit_job(job); 750 submit_exec_queue(q); 751 } 752 753 if (lr) { 754 xe_sched_job_set_error(job, -EOPNOTSUPP); 755 dma_fence_put(job->fence); /* Drop ref from xe_sched_job_arm */ 756 } else { 757 fence = job->fence; 758 } 759 760 return fence; 761 } 762 763 static void guc_exec_queue_free_job(struct drm_sched_job *drm_job) 764 { 765 struct xe_sched_job *job = to_xe_sched_job(drm_job); 766 767 trace_xe_sched_job_free(job); 768 xe_sched_job_put(job); 769 } 770 771 int xe_guc_read_stopped(struct xe_guc *guc) 772 { 773 return atomic_read(&guc->submission_state.stopped); 774 } 775 776 #define MAKE_SCHED_CONTEXT_ACTION(q, enable_disable) \ 777 u32 action[] = { \ 778 XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET, \ 779 q->guc->id, \ 780 GUC_CONTEXT_##enable_disable, \ 781 } 782 783 static void disable_scheduling_deregister(struct xe_guc *guc, 784 struct xe_exec_queue *q) 785 { 786 MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); 787 int ret; 788 789 set_min_preemption_timeout(guc, q); 790 smp_rmb(); 791 ret = wait_event_timeout(guc->ct.wq, 792 (!exec_queue_pending_enable(q) && 793 !exec_queue_pending_disable(q)) || 794 xe_guc_read_stopped(guc), 795 HZ * 5); 796 if (!ret) { 797 struct xe_gpu_scheduler *sched = &q->guc->sched; 798 799 xe_gt_warn(q->gt, "Pending enable/disable failed to respond\n"); 800 xe_sched_submission_start(sched); 801 xe_gt_reset_async(q->gt); 802 xe_sched_tdr_queue_imm(sched); 803 return; 804 } 805 806 clear_exec_queue_enabled(q); 807 set_exec_queue_pending_disable(q); 808 set_exec_queue_destroyed(q); 809 trace_xe_exec_queue_scheduling_disable(q); 810 811 /* 812 * Reserve space for both G2H here as the 2nd G2H is sent from a G2H 813 * handler and we are not allowed to reserved G2H space in handlers. 814 */ 815 xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 816 G2H_LEN_DW_SCHED_CONTEXT_MODE_SET + 817 G2H_LEN_DW_DEREGISTER_CONTEXT, 2); 818 } 819 820 static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q) 821 { 822 struct xe_guc *guc = exec_queue_to_guc(q); 823 struct xe_device *xe = guc_to_xe(guc); 824 825 /** to wakeup xe_wait_user_fence ioctl if exec queue is reset */ 826 wake_up_all(&xe->ufence_wq); 827 828 if (xe_exec_queue_is_lr(q)) 829 queue_work(guc_to_gt(guc)->ordered_wq, &q->guc->lr_tdr); 830 else 831 xe_sched_tdr_queue_imm(&q->guc->sched); 832 } 833 834 /** 835 * xe_guc_submit_wedge() - Wedge GuC submission 836 * @guc: the GuC object 837 * 838 * Save exec queue's registered with GuC state by taking a ref to each queue. 839 * Register a DRMM handler to drop refs upon driver unload. 840 */ 841 void xe_guc_submit_wedge(struct xe_guc *guc) 842 { 843 struct xe_gt *gt = guc_to_gt(guc); 844 struct xe_exec_queue *q; 845 unsigned long index; 846 int err; 847 848 xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode); 849 850 /* 851 * If device is being wedged even before submission_state is 852 * initialized, there's nothing to do here. 853 */ 854 if (!guc->submission_state.initialized) 855 return; 856 857 err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev, 858 guc_submit_wedged_fini, guc); 859 if (err) { 860 xe_gt_err(gt, "Failed to register clean-up on wedged.mode=2; " 861 "Although device is wedged.\n"); 862 return; 863 } 864 865 mutex_lock(&guc->submission_state.lock); 866 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) 867 if (xe_exec_queue_get_unless_zero(q)) 868 set_exec_queue_wedged(q); 869 mutex_unlock(&guc->submission_state.lock); 870 } 871 872 static bool guc_submit_hint_wedged(struct xe_guc *guc) 873 { 874 struct xe_device *xe = guc_to_xe(guc); 875 876 if (xe->wedged.mode != 2) 877 return false; 878 879 if (xe_device_wedged(xe)) 880 return true; 881 882 xe_device_declare_wedged(xe); 883 884 return true; 885 } 886 887 static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w) 888 { 889 struct xe_guc_exec_queue *ge = 890 container_of(w, struct xe_guc_exec_queue, lr_tdr); 891 struct xe_exec_queue *q = ge->q; 892 struct xe_guc *guc = exec_queue_to_guc(q); 893 struct xe_gpu_scheduler *sched = &ge->sched; 894 bool wedged; 895 896 xe_gt_assert(guc_to_gt(guc), xe_exec_queue_is_lr(q)); 897 trace_xe_exec_queue_lr_cleanup(q); 898 899 wedged = guc_submit_hint_wedged(exec_queue_to_guc(q)); 900 901 /* Kill the run_job / process_msg entry points */ 902 xe_sched_submission_stop(sched); 903 904 /* 905 * Engine state now mostly stable, disable scheduling / deregister if 906 * needed. This cleanup routine might be called multiple times, where 907 * the actual async engine deregister drops the final engine ref. 908 * Calling disable_scheduling_deregister will mark the engine as 909 * destroyed and fire off the CT requests to disable scheduling / 910 * deregister, which we only want to do once. We also don't want to mark 911 * the engine as pending_disable again as this may race with the 912 * xe_guc_deregister_done_handler() which treats it as an unexpected 913 * state. 914 */ 915 if (!wedged && exec_queue_registered(q) && !exec_queue_destroyed(q)) { 916 struct xe_guc *guc = exec_queue_to_guc(q); 917 int ret; 918 919 set_exec_queue_banned(q); 920 disable_scheduling_deregister(guc, q); 921 922 /* 923 * Must wait for scheduling to be disabled before signalling 924 * any fences, if GT broken the GT reset code should signal us. 925 */ 926 ret = wait_event_timeout(guc->ct.wq, 927 !exec_queue_pending_disable(q) || 928 xe_guc_read_stopped(guc), HZ * 5); 929 if (!ret) { 930 xe_gt_warn(q->gt, "Schedule disable failed to respond, guc_id=%d\n", 931 q->guc->id); 932 xe_devcoredump(q, NULL, "Schedule disable failed to respond, guc_id=%d\n", 933 q->guc->id); 934 xe_sched_submission_start(sched); 935 xe_gt_reset_async(q->gt); 936 return; 937 } 938 } 939 940 if (!exec_queue_killed(q) && !xe_lrc_ring_is_idle(q->lrc[0])) 941 xe_devcoredump(q, NULL, "LR job cleanup, guc_id=%d", q->guc->id); 942 943 xe_sched_submission_start(sched); 944 } 945 946 #define ADJUST_FIVE_PERCENT(__t) mul_u64_u32_div(__t, 105, 100) 947 948 static bool check_timeout(struct xe_exec_queue *q, struct xe_sched_job *job) 949 { 950 struct xe_gt *gt = guc_to_gt(exec_queue_to_guc(q)); 951 u32 ctx_timestamp, ctx_job_timestamp; 952 u32 timeout_ms = q->sched_props.job_timeout_ms; 953 u32 diff; 954 u64 running_time_ms; 955 956 if (!xe_sched_job_started(job)) { 957 xe_gt_warn(gt, "Check job timeout: seqno=%u, lrc_seqno=%u, guc_id=%d, not started", 958 xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job), 959 q->guc->id); 960 961 return xe_sched_invalidate_job(job, 2); 962 } 963 964 ctx_timestamp = lower_32_bits(xe_lrc_ctx_timestamp(q->lrc[0])); 965 ctx_job_timestamp = xe_lrc_ctx_job_timestamp(q->lrc[0]); 966 967 /* 968 * Counter wraps at ~223s at the usual 19.2MHz, be paranoid catch 969 * possible overflows with a high timeout. 970 */ 971 xe_gt_assert(gt, timeout_ms < 100 * MSEC_PER_SEC); 972 973 if (ctx_timestamp < ctx_job_timestamp) 974 diff = ctx_timestamp + U32_MAX - ctx_job_timestamp; 975 else 976 diff = ctx_timestamp - ctx_job_timestamp; 977 978 /* 979 * Ensure timeout is within 5% to account for an GuC scheduling latency 980 */ 981 running_time_ms = 982 ADJUST_FIVE_PERCENT(xe_gt_clock_interval_to_ms(gt, diff)); 983 984 xe_gt_dbg(gt, 985 "Check job timeout: seqno=%u, lrc_seqno=%u, guc_id=%d, running_time_ms=%llu, timeout_ms=%u, diff=0x%08x", 986 xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job), 987 q->guc->id, running_time_ms, timeout_ms, diff); 988 989 return running_time_ms >= timeout_ms; 990 } 991 992 static void enable_scheduling(struct xe_exec_queue *q) 993 { 994 MAKE_SCHED_CONTEXT_ACTION(q, ENABLE); 995 struct xe_guc *guc = exec_queue_to_guc(q); 996 int ret; 997 998 xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q)); 999 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 1000 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q)); 1001 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q)); 1002 1003 set_exec_queue_pending_enable(q); 1004 set_exec_queue_enabled(q); 1005 trace_xe_exec_queue_scheduling_enable(q); 1006 1007 xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 1008 G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1); 1009 1010 ret = wait_event_timeout(guc->ct.wq, 1011 !exec_queue_pending_enable(q) || 1012 xe_guc_read_stopped(guc), HZ * 5); 1013 if (!ret || xe_guc_read_stopped(guc)) { 1014 xe_gt_warn(guc_to_gt(guc), "Schedule enable failed to respond"); 1015 set_exec_queue_banned(q); 1016 xe_gt_reset_async(q->gt); 1017 xe_sched_tdr_queue_imm(&q->guc->sched); 1018 } 1019 } 1020 1021 static void disable_scheduling(struct xe_exec_queue *q, bool immediate) 1022 { 1023 MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); 1024 struct xe_guc *guc = exec_queue_to_guc(q); 1025 1026 xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q)); 1027 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 1028 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q)); 1029 1030 if (immediate) 1031 set_min_preemption_timeout(guc, q); 1032 clear_exec_queue_enabled(q); 1033 set_exec_queue_pending_disable(q); 1034 trace_xe_exec_queue_scheduling_disable(q); 1035 1036 xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 1037 G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1); 1038 } 1039 1040 static void __deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q) 1041 { 1042 u32 action[] = { 1043 XE_GUC_ACTION_DEREGISTER_CONTEXT, 1044 q->guc->id, 1045 }; 1046 1047 xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q)); 1048 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 1049 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q)); 1050 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q)); 1051 1052 set_exec_queue_destroyed(q); 1053 trace_xe_exec_queue_deregister(q); 1054 1055 xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 1056 G2H_LEN_DW_DEREGISTER_CONTEXT, 1); 1057 } 1058 1059 static enum drm_gpu_sched_stat 1060 guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) 1061 { 1062 struct xe_sched_job *job = to_xe_sched_job(drm_job); 1063 struct xe_sched_job *tmp_job; 1064 struct xe_exec_queue *q = job->q; 1065 struct xe_gpu_scheduler *sched = &q->guc->sched; 1066 struct xe_guc *guc = exec_queue_to_guc(q); 1067 const char *process_name = "no process"; 1068 struct xe_device *xe = guc_to_xe(guc); 1069 unsigned int fw_ref; 1070 int err = -ETIME; 1071 pid_t pid = -1; 1072 int i = 0; 1073 bool wedged, skip_timeout_check; 1074 1075 /* 1076 * TDR has fired before free job worker. Common if exec queue 1077 * immediately closed after last fence signaled. Add back to pending 1078 * list so job can be freed and kick scheduler ensuring free job is not 1079 * lost. 1080 */ 1081 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &job->fence->flags)) { 1082 xe_sched_add_pending_job(sched, job); 1083 xe_sched_submission_start(sched); 1084 1085 return DRM_GPU_SCHED_STAT_NOMINAL; 1086 } 1087 1088 /* Kill the run_job entry point */ 1089 xe_sched_submission_stop(sched); 1090 1091 /* Must check all state after stopping scheduler */ 1092 skip_timeout_check = exec_queue_reset(q) || 1093 exec_queue_killed_or_banned_or_wedged(q) || 1094 exec_queue_destroyed(q); 1095 1096 /* 1097 * If devcoredump not captured and GuC capture for the job is not ready 1098 * do manual capture first and decide later if we need to use it 1099 */ 1100 if (!exec_queue_killed(q) && !xe->devcoredump.captured && 1101 !xe_guc_capture_get_matching_and_lock(q)) { 1102 /* take force wake before engine register manual capture */ 1103 fw_ref = xe_force_wake_get(gt_to_fw(q->gt), XE_FORCEWAKE_ALL); 1104 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) 1105 xe_gt_info(q->gt, "failed to get forcewake for coredump capture\n"); 1106 1107 xe_engine_snapshot_capture_for_queue(q); 1108 1109 xe_force_wake_put(gt_to_fw(q->gt), fw_ref); 1110 } 1111 1112 /* 1113 * XXX: Sampling timeout doesn't work in wedged mode as we have to 1114 * modify scheduling state to read timestamp. We could read the 1115 * timestamp from a register to accumulate current running time but this 1116 * doesn't work for SRIOV. For now assuming timeouts in wedged mode are 1117 * genuine timeouts. 1118 */ 1119 wedged = guc_submit_hint_wedged(exec_queue_to_guc(q)); 1120 1121 /* Engine state now stable, disable scheduling to check timestamp */ 1122 if (!wedged && exec_queue_registered(q)) { 1123 int ret; 1124 1125 if (exec_queue_reset(q)) 1126 err = -EIO; 1127 1128 if (!exec_queue_destroyed(q)) { 1129 /* 1130 * Wait for any pending G2H to flush out before 1131 * modifying state 1132 */ 1133 ret = wait_event_timeout(guc->ct.wq, 1134 (!exec_queue_pending_enable(q) && 1135 !exec_queue_pending_disable(q)) || 1136 xe_guc_read_stopped(guc), HZ * 5); 1137 if (!ret || xe_guc_read_stopped(guc)) 1138 goto trigger_reset; 1139 1140 /* 1141 * Flag communicates to G2H handler that schedule 1142 * disable originated from a timeout check. The G2H then 1143 * avoid triggering cleanup or deregistering the exec 1144 * queue. 1145 */ 1146 set_exec_queue_check_timeout(q); 1147 disable_scheduling(q, skip_timeout_check); 1148 } 1149 1150 /* 1151 * Must wait for scheduling to be disabled before signalling 1152 * any fences, if GT broken the GT reset code should signal us. 1153 * 1154 * FIXME: Tests can generate a ton of 0x6000 (IOMMU CAT fault 1155 * error) messages which can cause the schedule disable to get 1156 * lost. If this occurs, trigger a GT reset to recover. 1157 */ 1158 smp_rmb(); 1159 ret = wait_event_timeout(guc->ct.wq, 1160 !exec_queue_pending_disable(q) || 1161 xe_guc_read_stopped(guc), HZ * 5); 1162 if (!ret || xe_guc_read_stopped(guc)) { 1163 trigger_reset: 1164 if (!ret) 1165 xe_gt_warn(guc_to_gt(guc), 1166 "Schedule disable failed to respond, guc_id=%d", 1167 q->guc->id); 1168 xe_devcoredump(q, job, 1169 "Schedule disable failed to respond, guc_id=%d, ret=%d, guc_read=%d", 1170 q->guc->id, ret, xe_guc_read_stopped(guc)); 1171 set_exec_queue_extra_ref(q); 1172 xe_exec_queue_get(q); /* GT reset owns this */ 1173 set_exec_queue_banned(q); 1174 xe_gt_reset_async(q->gt); 1175 xe_sched_tdr_queue_imm(sched); 1176 goto rearm; 1177 } 1178 } 1179 1180 /* 1181 * Check if job is actually timed out, if so restart job execution and TDR 1182 */ 1183 if (!wedged && !skip_timeout_check && !check_timeout(q, job) && 1184 !exec_queue_reset(q) && exec_queue_registered(q)) { 1185 clear_exec_queue_check_timeout(q); 1186 goto sched_enable; 1187 } 1188 1189 if (q->vm && q->vm->xef) { 1190 process_name = q->vm->xef->process_name; 1191 pid = q->vm->xef->pid; 1192 } 1193 1194 if (!exec_queue_killed(q)) 1195 xe_gt_notice(guc_to_gt(guc), 1196 "Timedout job: seqno=%u, lrc_seqno=%u, guc_id=%d, flags=0x%lx in %s [%d]", 1197 xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job), 1198 q->guc->id, q->flags, process_name, pid); 1199 1200 trace_xe_sched_job_timedout(job); 1201 1202 if (!exec_queue_killed(q)) 1203 xe_devcoredump(q, job, 1204 "Timedout job - seqno=%u, lrc_seqno=%u, guc_id=%d, flags=0x%lx", 1205 xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job), 1206 q->guc->id, q->flags); 1207 1208 /* 1209 * Kernel jobs should never fail, nor should VM jobs if they do 1210 * somethings has gone wrong and the GT needs a reset 1211 */ 1212 xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_KERNEL, 1213 "Kernel-submitted job timed out\n"); 1214 xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q), 1215 "VM job timed out on non-killed execqueue\n"); 1216 if (!wedged && (q->flags & EXEC_QUEUE_FLAG_KERNEL || 1217 (q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q)))) { 1218 if (!xe_sched_invalidate_job(job, 2)) { 1219 clear_exec_queue_check_timeout(q); 1220 xe_gt_reset_async(q->gt); 1221 goto rearm; 1222 } 1223 } 1224 1225 /* Finish cleaning up exec queue via deregister */ 1226 set_exec_queue_banned(q); 1227 if (!wedged && exec_queue_registered(q) && !exec_queue_destroyed(q)) { 1228 set_exec_queue_extra_ref(q); 1229 xe_exec_queue_get(q); 1230 __deregister_exec_queue(guc, q); 1231 } 1232 1233 /* Stop fence signaling */ 1234 xe_hw_fence_irq_stop(q->fence_irq); 1235 1236 /* 1237 * Fence state now stable, stop / start scheduler which cleans up any 1238 * fences that are complete 1239 */ 1240 xe_sched_add_pending_job(sched, job); 1241 xe_sched_submission_start(sched); 1242 1243 xe_guc_exec_queue_trigger_cleanup(q); 1244 1245 /* Mark all outstanding jobs as bad, thus completing them */ 1246 spin_lock(&sched->base.job_list_lock); 1247 list_for_each_entry(tmp_job, &sched->base.pending_list, drm.list) 1248 xe_sched_job_set_error(tmp_job, !i++ ? err : -ECANCELED); 1249 spin_unlock(&sched->base.job_list_lock); 1250 1251 /* Start fence signaling */ 1252 xe_hw_fence_irq_start(q->fence_irq); 1253 1254 return DRM_GPU_SCHED_STAT_NOMINAL; 1255 1256 sched_enable: 1257 enable_scheduling(q); 1258 rearm: 1259 /* 1260 * XXX: Ideally want to adjust timeout based on current execution time 1261 * but there is not currently an easy way to do in DRM scheduler. With 1262 * some thought, do this in a follow up. 1263 */ 1264 xe_sched_add_pending_job(sched, job); 1265 xe_sched_submission_start(sched); 1266 1267 return DRM_GPU_SCHED_STAT_NOMINAL; 1268 } 1269 1270 static void __guc_exec_queue_fini_async(struct work_struct *w) 1271 { 1272 struct xe_guc_exec_queue *ge = 1273 container_of(w, struct xe_guc_exec_queue, fini_async); 1274 struct xe_exec_queue *q = ge->q; 1275 struct xe_guc *guc = exec_queue_to_guc(q); 1276 1277 xe_pm_runtime_get(guc_to_xe(guc)); 1278 trace_xe_exec_queue_destroy(q); 1279 1280 release_guc_id(guc, q); 1281 if (xe_exec_queue_is_lr(q)) 1282 cancel_work_sync(&ge->lr_tdr); 1283 /* Confirm no work left behind accessing device structures */ 1284 cancel_delayed_work_sync(&ge->sched.base.work_tdr); 1285 xe_sched_entity_fini(&ge->entity); 1286 xe_sched_fini(&ge->sched); 1287 1288 kfree(ge); 1289 xe_exec_queue_fini(q); 1290 xe_pm_runtime_put(guc_to_xe(guc)); 1291 } 1292 1293 static void guc_exec_queue_fini_async(struct xe_exec_queue *q) 1294 { 1295 struct xe_guc *guc = exec_queue_to_guc(q); 1296 struct xe_device *xe = guc_to_xe(guc); 1297 1298 INIT_WORK(&q->guc->fini_async, __guc_exec_queue_fini_async); 1299 1300 /* We must block on kernel engines so slabs are empty on driver unload */ 1301 if (q->flags & EXEC_QUEUE_FLAG_PERMANENT || exec_queue_wedged(q)) 1302 __guc_exec_queue_fini_async(&q->guc->fini_async); 1303 else 1304 queue_work(xe->destroy_wq, &q->guc->fini_async); 1305 } 1306 1307 static void __guc_exec_queue_fini(struct xe_guc *guc, struct xe_exec_queue *q) 1308 { 1309 /* 1310 * Might be done from within the GPU scheduler, need to do async as we 1311 * fini the scheduler when the engine is fini'd, the scheduler can't 1312 * complete fini within itself (circular dependency). Async resolves 1313 * this we and don't really care when everything is fini'd, just that it 1314 * is. 1315 */ 1316 guc_exec_queue_fini_async(q); 1317 } 1318 1319 static void __guc_exec_queue_process_msg_cleanup(struct xe_sched_msg *msg) 1320 { 1321 struct xe_exec_queue *q = msg->private_data; 1322 struct xe_guc *guc = exec_queue_to_guc(q); 1323 1324 xe_gt_assert(guc_to_gt(guc), !(q->flags & EXEC_QUEUE_FLAG_PERMANENT)); 1325 trace_xe_exec_queue_cleanup_entity(q); 1326 1327 if (exec_queue_registered(q)) 1328 disable_scheduling_deregister(guc, q); 1329 else 1330 __guc_exec_queue_fini(guc, q); 1331 } 1332 1333 static bool guc_exec_queue_allowed_to_change_state(struct xe_exec_queue *q) 1334 { 1335 return !exec_queue_killed_or_banned_or_wedged(q) && exec_queue_registered(q); 1336 } 1337 1338 static void __guc_exec_queue_process_msg_set_sched_props(struct xe_sched_msg *msg) 1339 { 1340 struct xe_exec_queue *q = msg->private_data; 1341 struct xe_guc *guc = exec_queue_to_guc(q); 1342 1343 if (guc_exec_queue_allowed_to_change_state(q)) 1344 init_policies(guc, q); 1345 kfree(msg); 1346 } 1347 1348 static void __suspend_fence_signal(struct xe_exec_queue *q) 1349 { 1350 if (!q->guc->suspend_pending) 1351 return; 1352 1353 WRITE_ONCE(q->guc->suspend_pending, false); 1354 wake_up(&q->guc->suspend_wait); 1355 } 1356 1357 static void suspend_fence_signal(struct xe_exec_queue *q) 1358 { 1359 struct xe_guc *guc = exec_queue_to_guc(q); 1360 1361 xe_gt_assert(guc_to_gt(guc), exec_queue_suspended(q) || exec_queue_killed(q) || 1362 xe_guc_read_stopped(guc)); 1363 xe_gt_assert(guc_to_gt(guc), q->guc->suspend_pending); 1364 1365 __suspend_fence_signal(q); 1366 } 1367 1368 static void __guc_exec_queue_process_msg_suspend(struct xe_sched_msg *msg) 1369 { 1370 struct xe_exec_queue *q = msg->private_data; 1371 struct xe_guc *guc = exec_queue_to_guc(q); 1372 1373 if (guc_exec_queue_allowed_to_change_state(q) && !exec_queue_suspended(q) && 1374 exec_queue_enabled(q)) { 1375 wait_event(guc->ct.wq, (q->guc->resume_time != RESUME_PENDING || 1376 xe_guc_read_stopped(guc)) && !exec_queue_pending_disable(q)); 1377 1378 if (!xe_guc_read_stopped(guc)) { 1379 s64 since_resume_ms = 1380 ktime_ms_delta(ktime_get(), 1381 q->guc->resume_time); 1382 s64 wait_ms = q->vm->preempt.min_run_period_ms - 1383 since_resume_ms; 1384 1385 if (wait_ms > 0 && q->guc->resume_time) 1386 msleep(wait_ms); 1387 1388 set_exec_queue_suspended(q); 1389 disable_scheduling(q, false); 1390 } 1391 } else if (q->guc->suspend_pending) { 1392 set_exec_queue_suspended(q); 1393 suspend_fence_signal(q); 1394 } 1395 } 1396 1397 static void __guc_exec_queue_process_msg_resume(struct xe_sched_msg *msg) 1398 { 1399 struct xe_exec_queue *q = msg->private_data; 1400 1401 if (guc_exec_queue_allowed_to_change_state(q)) { 1402 clear_exec_queue_suspended(q); 1403 if (!exec_queue_enabled(q)) { 1404 q->guc->resume_time = RESUME_PENDING; 1405 enable_scheduling(q); 1406 } 1407 } else { 1408 clear_exec_queue_suspended(q); 1409 } 1410 } 1411 1412 #define CLEANUP 1 /* Non-zero values to catch uninitialized msg */ 1413 #define SET_SCHED_PROPS 2 1414 #define SUSPEND 3 1415 #define RESUME 4 1416 #define OPCODE_MASK 0xf 1417 #define MSG_LOCKED BIT(8) 1418 1419 static void guc_exec_queue_process_msg(struct xe_sched_msg *msg) 1420 { 1421 struct xe_device *xe = guc_to_xe(exec_queue_to_guc(msg->private_data)); 1422 1423 trace_xe_sched_msg_recv(msg); 1424 1425 switch (msg->opcode) { 1426 case CLEANUP: 1427 __guc_exec_queue_process_msg_cleanup(msg); 1428 break; 1429 case SET_SCHED_PROPS: 1430 __guc_exec_queue_process_msg_set_sched_props(msg); 1431 break; 1432 case SUSPEND: 1433 __guc_exec_queue_process_msg_suspend(msg); 1434 break; 1435 case RESUME: 1436 __guc_exec_queue_process_msg_resume(msg); 1437 break; 1438 default: 1439 XE_WARN_ON("Unknown message type"); 1440 } 1441 1442 xe_pm_runtime_put(xe); 1443 } 1444 1445 static const struct drm_sched_backend_ops drm_sched_ops = { 1446 .run_job = guc_exec_queue_run_job, 1447 .free_job = guc_exec_queue_free_job, 1448 .timedout_job = guc_exec_queue_timedout_job, 1449 }; 1450 1451 static const struct xe_sched_backend_ops xe_sched_ops = { 1452 .process_msg = guc_exec_queue_process_msg, 1453 }; 1454 1455 static int guc_exec_queue_init(struct xe_exec_queue *q) 1456 { 1457 struct xe_gpu_scheduler *sched; 1458 struct xe_guc *guc = exec_queue_to_guc(q); 1459 struct xe_guc_exec_queue *ge; 1460 long timeout; 1461 int err, i; 1462 1463 xe_gt_assert(guc_to_gt(guc), xe_device_uc_enabled(guc_to_xe(guc))); 1464 1465 ge = kzalloc(sizeof(*ge), GFP_KERNEL); 1466 if (!ge) 1467 return -ENOMEM; 1468 1469 q->guc = ge; 1470 ge->q = q; 1471 init_waitqueue_head(&ge->suspend_wait); 1472 1473 for (i = 0; i < MAX_STATIC_MSG_TYPE; ++i) 1474 INIT_LIST_HEAD(&ge->static_msgs[i].link); 1475 1476 timeout = (q->vm && xe_vm_in_lr_mode(q->vm)) ? MAX_SCHEDULE_TIMEOUT : 1477 msecs_to_jiffies(q->sched_props.job_timeout_ms); 1478 err = xe_sched_init(&ge->sched, &drm_sched_ops, &xe_sched_ops, 1479 NULL, q->lrc[0]->ring.size / MAX_JOB_SIZE_BYTES, 64, 1480 timeout, guc_to_gt(guc)->ordered_wq, NULL, 1481 q->name, gt_to_xe(q->gt)->drm.dev); 1482 if (err) 1483 goto err_free; 1484 1485 sched = &ge->sched; 1486 err = xe_sched_entity_init(&ge->entity, sched); 1487 if (err) 1488 goto err_sched; 1489 1490 if (xe_exec_queue_is_lr(q)) 1491 INIT_WORK(&q->guc->lr_tdr, xe_guc_exec_queue_lr_cleanup); 1492 1493 mutex_lock(&guc->submission_state.lock); 1494 1495 err = alloc_guc_id(guc, q); 1496 if (err) 1497 goto err_entity; 1498 1499 q->entity = &ge->entity; 1500 1501 if (xe_guc_read_stopped(guc)) 1502 xe_sched_stop(sched); 1503 1504 mutex_unlock(&guc->submission_state.lock); 1505 1506 xe_exec_queue_assign_name(q, q->guc->id); 1507 1508 trace_xe_exec_queue_create(q); 1509 1510 return 0; 1511 1512 err_entity: 1513 mutex_unlock(&guc->submission_state.lock); 1514 xe_sched_entity_fini(&ge->entity); 1515 err_sched: 1516 xe_sched_fini(&ge->sched); 1517 err_free: 1518 kfree(ge); 1519 1520 return err; 1521 } 1522 1523 static void guc_exec_queue_kill(struct xe_exec_queue *q) 1524 { 1525 trace_xe_exec_queue_kill(q); 1526 set_exec_queue_killed(q); 1527 __suspend_fence_signal(q); 1528 xe_guc_exec_queue_trigger_cleanup(q); 1529 } 1530 1531 static void guc_exec_queue_add_msg(struct xe_exec_queue *q, struct xe_sched_msg *msg, 1532 u32 opcode) 1533 { 1534 xe_pm_runtime_get_noresume(guc_to_xe(exec_queue_to_guc(q))); 1535 1536 INIT_LIST_HEAD(&msg->link); 1537 msg->opcode = opcode & OPCODE_MASK; 1538 msg->private_data = q; 1539 1540 trace_xe_sched_msg_add(msg); 1541 if (opcode & MSG_LOCKED) 1542 xe_sched_add_msg_locked(&q->guc->sched, msg); 1543 else 1544 xe_sched_add_msg(&q->guc->sched, msg); 1545 } 1546 1547 static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q, 1548 struct xe_sched_msg *msg, 1549 u32 opcode) 1550 { 1551 if (!list_empty(&msg->link)) 1552 return false; 1553 1554 guc_exec_queue_add_msg(q, msg, opcode | MSG_LOCKED); 1555 1556 return true; 1557 } 1558 1559 #define STATIC_MSG_CLEANUP 0 1560 #define STATIC_MSG_SUSPEND 1 1561 #define STATIC_MSG_RESUME 2 1562 static void guc_exec_queue_fini(struct xe_exec_queue *q) 1563 { 1564 struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP; 1565 1566 if (!(q->flags & EXEC_QUEUE_FLAG_PERMANENT) && !exec_queue_wedged(q)) 1567 guc_exec_queue_add_msg(q, msg, CLEANUP); 1568 else 1569 __guc_exec_queue_fini(exec_queue_to_guc(q), q); 1570 } 1571 1572 static int guc_exec_queue_set_priority(struct xe_exec_queue *q, 1573 enum xe_exec_queue_priority priority) 1574 { 1575 struct xe_sched_msg *msg; 1576 1577 if (q->sched_props.priority == priority || 1578 exec_queue_killed_or_banned_or_wedged(q)) 1579 return 0; 1580 1581 msg = kmalloc(sizeof(*msg), GFP_KERNEL); 1582 if (!msg) 1583 return -ENOMEM; 1584 1585 q->sched_props.priority = priority; 1586 guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); 1587 1588 return 0; 1589 } 1590 1591 static int guc_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us) 1592 { 1593 struct xe_sched_msg *msg; 1594 1595 if (q->sched_props.timeslice_us == timeslice_us || 1596 exec_queue_killed_or_banned_or_wedged(q)) 1597 return 0; 1598 1599 msg = kmalloc(sizeof(*msg), GFP_KERNEL); 1600 if (!msg) 1601 return -ENOMEM; 1602 1603 q->sched_props.timeslice_us = timeslice_us; 1604 guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); 1605 1606 return 0; 1607 } 1608 1609 static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q, 1610 u32 preempt_timeout_us) 1611 { 1612 struct xe_sched_msg *msg; 1613 1614 if (q->sched_props.preempt_timeout_us == preempt_timeout_us || 1615 exec_queue_killed_or_banned_or_wedged(q)) 1616 return 0; 1617 1618 msg = kmalloc(sizeof(*msg), GFP_KERNEL); 1619 if (!msg) 1620 return -ENOMEM; 1621 1622 q->sched_props.preempt_timeout_us = preempt_timeout_us; 1623 guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); 1624 1625 return 0; 1626 } 1627 1628 static int guc_exec_queue_suspend(struct xe_exec_queue *q) 1629 { 1630 struct xe_gpu_scheduler *sched = &q->guc->sched; 1631 struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_SUSPEND; 1632 1633 if (exec_queue_killed_or_banned_or_wedged(q)) 1634 return -EINVAL; 1635 1636 xe_sched_msg_lock(sched); 1637 if (guc_exec_queue_try_add_msg(q, msg, SUSPEND)) 1638 q->guc->suspend_pending = true; 1639 xe_sched_msg_unlock(sched); 1640 1641 return 0; 1642 } 1643 1644 static int guc_exec_queue_suspend_wait(struct xe_exec_queue *q) 1645 { 1646 struct xe_guc *guc = exec_queue_to_guc(q); 1647 int ret; 1648 1649 /* 1650 * Likely don't need to check exec_queue_killed() as we clear 1651 * suspend_pending upon kill but to be paranoid but races in which 1652 * suspend_pending is set after kill also check kill here. 1653 */ 1654 ret = wait_event_interruptible_timeout(q->guc->suspend_wait, 1655 !READ_ONCE(q->guc->suspend_pending) || 1656 exec_queue_killed(q) || 1657 xe_guc_read_stopped(guc), 1658 HZ * 5); 1659 1660 if (!ret) { 1661 xe_gt_warn(guc_to_gt(guc), 1662 "Suspend fence, guc_id=%d, failed to respond", 1663 q->guc->id); 1664 /* XXX: Trigger GT reset? */ 1665 return -ETIME; 1666 } 1667 1668 return ret < 0 ? ret : 0; 1669 } 1670 1671 static void guc_exec_queue_resume(struct xe_exec_queue *q) 1672 { 1673 struct xe_gpu_scheduler *sched = &q->guc->sched; 1674 struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_RESUME; 1675 struct xe_guc *guc = exec_queue_to_guc(q); 1676 1677 xe_gt_assert(guc_to_gt(guc), !q->guc->suspend_pending); 1678 1679 xe_sched_msg_lock(sched); 1680 guc_exec_queue_try_add_msg(q, msg, RESUME); 1681 xe_sched_msg_unlock(sched); 1682 } 1683 1684 static bool guc_exec_queue_reset_status(struct xe_exec_queue *q) 1685 { 1686 return exec_queue_reset(q) || exec_queue_killed_or_banned_or_wedged(q); 1687 } 1688 1689 /* 1690 * All of these functions are an abstraction layer which other parts of XE can 1691 * use to trap into the GuC backend. All of these functions, aside from init, 1692 * really shouldn't do much other than trap into the DRM scheduler which 1693 * synchronizes these operations. 1694 */ 1695 static const struct xe_exec_queue_ops guc_exec_queue_ops = { 1696 .init = guc_exec_queue_init, 1697 .kill = guc_exec_queue_kill, 1698 .fini = guc_exec_queue_fini, 1699 .set_priority = guc_exec_queue_set_priority, 1700 .set_timeslice = guc_exec_queue_set_timeslice, 1701 .set_preempt_timeout = guc_exec_queue_set_preempt_timeout, 1702 .suspend = guc_exec_queue_suspend, 1703 .suspend_wait = guc_exec_queue_suspend_wait, 1704 .resume = guc_exec_queue_resume, 1705 .reset_status = guc_exec_queue_reset_status, 1706 }; 1707 1708 static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q) 1709 { 1710 struct xe_gpu_scheduler *sched = &q->guc->sched; 1711 1712 /* Stop scheduling + flush any DRM scheduler operations */ 1713 xe_sched_submission_stop(sched); 1714 1715 /* Clean up lost G2H + reset engine state */ 1716 if (exec_queue_registered(q)) { 1717 if (exec_queue_extra_ref(q) || xe_exec_queue_is_lr(q)) 1718 xe_exec_queue_put(q); 1719 else if (exec_queue_destroyed(q)) 1720 __guc_exec_queue_fini(guc, q); 1721 } 1722 if (q->guc->suspend_pending) { 1723 set_exec_queue_suspended(q); 1724 suspend_fence_signal(q); 1725 } 1726 atomic_and(EXEC_QUEUE_STATE_WEDGED | EXEC_QUEUE_STATE_BANNED | 1727 EXEC_QUEUE_STATE_KILLED | EXEC_QUEUE_STATE_DESTROYED | 1728 EXEC_QUEUE_STATE_SUSPENDED, 1729 &q->guc->state); 1730 q->guc->resume_time = 0; 1731 trace_xe_exec_queue_stop(q); 1732 1733 /* 1734 * Ban any engine (aside from kernel and engines used for VM ops) with a 1735 * started but not complete job or if a job has gone through a GT reset 1736 * more than twice. 1737 */ 1738 if (!(q->flags & (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM))) { 1739 struct xe_sched_job *job = xe_sched_first_pending_job(sched); 1740 bool ban = false; 1741 1742 if (job) { 1743 if ((xe_sched_job_started(job) && 1744 !xe_sched_job_completed(job)) || 1745 xe_sched_invalidate_job(job, 2)) { 1746 trace_xe_sched_job_ban(job); 1747 ban = true; 1748 } 1749 } else if (xe_exec_queue_is_lr(q) && 1750 !xe_lrc_ring_is_idle(q->lrc[0])) { 1751 ban = true; 1752 } 1753 1754 if (ban) { 1755 set_exec_queue_banned(q); 1756 xe_guc_exec_queue_trigger_cleanup(q); 1757 } 1758 } 1759 } 1760 1761 int xe_guc_submit_reset_prepare(struct xe_guc *guc) 1762 { 1763 int ret; 1764 1765 if (!guc->submission_state.initialized) 1766 return 0; 1767 1768 /* 1769 * Using an atomic here rather than submission_state.lock as this 1770 * function can be called while holding the CT lock (engine reset 1771 * failure). submission_state.lock needs the CT lock to resubmit jobs. 1772 * Atomic is not ideal, but it works to prevent against concurrent reset 1773 * and releasing any TDRs waiting on guc->submission_state.stopped. 1774 */ 1775 ret = atomic_fetch_or(1, &guc->submission_state.stopped); 1776 smp_wmb(); 1777 wake_up_all(&guc->ct.wq); 1778 1779 return ret; 1780 } 1781 1782 void xe_guc_submit_reset_wait(struct xe_guc *guc) 1783 { 1784 wait_event(guc->ct.wq, xe_device_wedged(guc_to_xe(guc)) || 1785 !xe_guc_read_stopped(guc)); 1786 } 1787 1788 void xe_guc_submit_stop(struct xe_guc *guc) 1789 { 1790 struct xe_exec_queue *q; 1791 unsigned long index; 1792 1793 xe_gt_assert(guc_to_gt(guc), xe_guc_read_stopped(guc) == 1); 1794 1795 mutex_lock(&guc->submission_state.lock); 1796 1797 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) { 1798 /* Prevent redundant attempts to stop parallel queues */ 1799 if (q->guc->id != index) 1800 continue; 1801 1802 guc_exec_queue_stop(guc, q); 1803 } 1804 1805 mutex_unlock(&guc->submission_state.lock); 1806 1807 /* 1808 * No one can enter the backend at this point, aside from new engine 1809 * creation which is protected by guc->submission_state.lock. 1810 */ 1811 1812 } 1813 1814 static void guc_exec_queue_start(struct xe_exec_queue *q) 1815 { 1816 struct xe_gpu_scheduler *sched = &q->guc->sched; 1817 1818 if (!exec_queue_killed_or_banned_or_wedged(q)) { 1819 int i; 1820 1821 trace_xe_exec_queue_resubmit(q); 1822 for (i = 0; i < q->width; ++i) 1823 xe_lrc_set_ring_head(q->lrc[i], q->lrc[i]->ring.tail); 1824 xe_sched_resubmit_jobs(sched); 1825 } 1826 1827 xe_sched_submission_start(sched); 1828 xe_sched_submission_resume_tdr(sched); 1829 } 1830 1831 int xe_guc_submit_start(struct xe_guc *guc) 1832 { 1833 struct xe_exec_queue *q; 1834 unsigned long index; 1835 1836 xe_gt_assert(guc_to_gt(guc), xe_guc_read_stopped(guc) == 1); 1837 1838 mutex_lock(&guc->submission_state.lock); 1839 atomic_dec(&guc->submission_state.stopped); 1840 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) { 1841 /* Prevent redundant attempts to start parallel queues */ 1842 if (q->guc->id != index) 1843 continue; 1844 1845 guc_exec_queue_start(q); 1846 } 1847 mutex_unlock(&guc->submission_state.lock); 1848 1849 wake_up_all(&guc->ct.wq); 1850 1851 return 0; 1852 } 1853 1854 static struct xe_exec_queue * 1855 g2h_exec_queue_lookup(struct xe_guc *guc, u32 guc_id) 1856 { 1857 struct xe_gt *gt = guc_to_gt(guc); 1858 struct xe_exec_queue *q; 1859 1860 if (unlikely(guc_id >= GUC_ID_MAX)) { 1861 xe_gt_err(gt, "Invalid guc_id %u\n", guc_id); 1862 return NULL; 1863 } 1864 1865 q = xa_load(&guc->submission_state.exec_queue_lookup, guc_id); 1866 if (unlikely(!q)) { 1867 xe_gt_err(gt, "Not engine present for guc_id %u\n", guc_id); 1868 return NULL; 1869 } 1870 1871 xe_gt_assert(guc_to_gt(guc), guc_id >= q->guc->id); 1872 xe_gt_assert(guc_to_gt(guc), guc_id < (q->guc->id + q->width)); 1873 1874 return q; 1875 } 1876 1877 static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q) 1878 { 1879 u32 action[] = { 1880 XE_GUC_ACTION_DEREGISTER_CONTEXT, 1881 q->guc->id, 1882 }; 1883 1884 xe_gt_assert(guc_to_gt(guc), exec_queue_destroyed(q)); 1885 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 1886 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q)); 1887 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q)); 1888 1889 trace_xe_exec_queue_deregister(q); 1890 1891 xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action)); 1892 } 1893 1894 static void handle_sched_done(struct xe_guc *guc, struct xe_exec_queue *q, 1895 u32 runnable_state) 1896 { 1897 trace_xe_exec_queue_scheduling_done(q); 1898 1899 if (runnable_state == 1) { 1900 xe_gt_assert(guc_to_gt(guc), exec_queue_pending_enable(q)); 1901 1902 q->guc->resume_time = ktime_get(); 1903 clear_exec_queue_pending_enable(q); 1904 smp_wmb(); 1905 wake_up_all(&guc->ct.wq); 1906 } else { 1907 bool check_timeout = exec_queue_check_timeout(q); 1908 1909 xe_gt_assert(guc_to_gt(guc), runnable_state == 0); 1910 xe_gt_assert(guc_to_gt(guc), exec_queue_pending_disable(q)); 1911 1912 if (q->guc->suspend_pending) { 1913 suspend_fence_signal(q); 1914 clear_exec_queue_pending_disable(q); 1915 } else { 1916 if (exec_queue_banned(q) || check_timeout) { 1917 smp_wmb(); 1918 wake_up_all(&guc->ct.wq); 1919 } 1920 if (!check_timeout && exec_queue_destroyed(q)) { 1921 /* 1922 * Make sure to clear the pending_disable only 1923 * after sampling the destroyed state. We want 1924 * to ensure we don't trigger the unregister too 1925 * early with something intending to only 1926 * disable scheduling. The caller doing the 1927 * destroy must wait for an ongoing 1928 * pending_disable before marking as destroyed. 1929 */ 1930 clear_exec_queue_pending_disable(q); 1931 deregister_exec_queue(guc, q); 1932 } else { 1933 clear_exec_queue_pending_disable(q); 1934 } 1935 } 1936 } 1937 } 1938 1939 int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len) 1940 { 1941 struct xe_exec_queue *q; 1942 u32 guc_id, runnable_state; 1943 1944 if (unlikely(len < 2)) 1945 return -EPROTO; 1946 1947 guc_id = msg[0]; 1948 runnable_state = msg[1]; 1949 1950 q = g2h_exec_queue_lookup(guc, guc_id); 1951 if (unlikely(!q)) 1952 return -EPROTO; 1953 1954 if (unlikely(!exec_queue_pending_enable(q) && 1955 !exec_queue_pending_disable(q))) { 1956 xe_gt_err(guc_to_gt(guc), 1957 "SCHED_DONE: Unexpected engine state 0x%04x, guc_id=%d, runnable_state=%u", 1958 atomic_read(&q->guc->state), q->guc->id, 1959 runnable_state); 1960 return -EPROTO; 1961 } 1962 1963 handle_sched_done(guc, q, runnable_state); 1964 1965 return 0; 1966 } 1967 1968 static void handle_deregister_done(struct xe_guc *guc, struct xe_exec_queue *q) 1969 { 1970 trace_xe_exec_queue_deregister_done(q); 1971 1972 clear_exec_queue_registered(q); 1973 1974 if (exec_queue_extra_ref(q) || xe_exec_queue_is_lr(q)) 1975 xe_exec_queue_put(q); 1976 else 1977 __guc_exec_queue_fini(guc, q); 1978 } 1979 1980 int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len) 1981 { 1982 struct xe_exec_queue *q; 1983 u32 guc_id; 1984 1985 if (unlikely(len < 1)) 1986 return -EPROTO; 1987 1988 guc_id = msg[0]; 1989 1990 q = g2h_exec_queue_lookup(guc, guc_id); 1991 if (unlikely(!q)) 1992 return -EPROTO; 1993 1994 if (!exec_queue_destroyed(q) || exec_queue_pending_disable(q) || 1995 exec_queue_pending_enable(q) || exec_queue_enabled(q)) { 1996 xe_gt_err(guc_to_gt(guc), 1997 "DEREGISTER_DONE: Unexpected engine state 0x%04x, guc_id=%d", 1998 atomic_read(&q->guc->state), q->guc->id); 1999 return -EPROTO; 2000 } 2001 2002 handle_deregister_done(guc, q); 2003 2004 return 0; 2005 } 2006 2007 int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) 2008 { 2009 struct xe_gt *gt = guc_to_gt(guc); 2010 struct xe_exec_queue *q; 2011 u32 guc_id; 2012 2013 if (unlikely(len < 1)) 2014 return -EPROTO; 2015 2016 guc_id = msg[0]; 2017 2018 q = g2h_exec_queue_lookup(guc, guc_id); 2019 if (unlikely(!q)) 2020 return -EPROTO; 2021 2022 xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: 0x%x, guc_id=%d", 2023 xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id); 2024 2025 trace_xe_exec_queue_reset(q); 2026 2027 /* 2028 * A banned engine is a NOP at this point (came from 2029 * guc_exec_queue_timedout_job). Otherwise, kick drm scheduler to cancel 2030 * jobs by setting timeout of the job to the minimum value kicking 2031 * guc_exec_queue_timedout_job. 2032 */ 2033 set_exec_queue_reset(q); 2034 if (!exec_queue_banned(q) && !exec_queue_check_timeout(q)) 2035 xe_guc_exec_queue_trigger_cleanup(q); 2036 2037 return 0; 2038 } 2039 2040 /* 2041 * xe_guc_error_capture_handler - Handler of GuC captured message 2042 * @guc: The GuC object 2043 * @msg: Point to the message 2044 * @len: The message length 2045 * 2046 * When GuC captured data is ready, GuC will send message 2047 * XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION to host, this function will be 2048 * called 1st to check status before process the data comes with the message. 2049 * 2050 * Returns: error code. 0 if success 2051 */ 2052 int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 len) 2053 { 2054 u32 status; 2055 2056 if (unlikely(len != XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION_DATA_LEN)) 2057 return -EPROTO; 2058 2059 status = msg[0] & XE_GUC_STATE_CAPTURE_EVENT_STATUS_MASK; 2060 if (status == XE_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE) 2061 xe_gt_warn(guc_to_gt(guc), "G2H-Error capture no space"); 2062 2063 xe_guc_capture_process(guc); 2064 2065 return 0; 2066 } 2067 2068 int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, 2069 u32 len) 2070 { 2071 struct xe_gt *gt = guc_to_gt(guc); 2072 struct xe_exec_queue *q; 2073 u32 guc_id; 2074 2075 if (unlikely(len < 1)) 2076 return -EPROTO; 2077 2078 guc_id = msg[0]; 2079 2080 if (guc_id == GUC_ID_UNKNOWN) { 2081 /* 2082 * GuC uses GUC_ID_UNKNOWN if it can not map the CAT fault to any PF/VF 2083 * context. In such case only PF will be notified about that fault. 2084 */ 2085 xe_gt_err_ratelimited(gt, "Memory CAT error reported by GuC!\n"); 2086 return 0; 2087 } 2088 2089 q = g2h_exec_queue_lookup(guc, guc_id); 2090 if (unlikely(!q)) 2091 return -EPROTO; 2092 2093 xe_gt_dbg(gt, "Engine memory cat error: engine_class=%s, logical_mask: 0x%x, guc_id=%d", 2094 xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id); 2095 2096 trace_xe_exec_queue_memory_cat_error(q); 2097 2098 /* Treat the same as engine reset */ 2099 set_exec_queue_reset(q); 2100 if (!exec_queue_banned(q) && !exec_queue_check_timeout(q)) 2101 xe_guc_exec_queue_trigger_cleanup(q); 2102 2103 return 0; 2104 } 2105 2106 int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len) 2107 { 2108 struct xe_gt *gt = guc_to_gt(guc); 2109 u8 guc_class, instance; 2110 u32 reason; 2111 2112 if (unlikely(len != 3)) 2113 return -EPROTO; 2114 2115 guc_class = msg[0]; 2116 instance = msg[1]; 2117 reason = msg[2]; 2118 2119 /* Unexpected failure of a hardware feature, log an actual error */ 2120 xe_gt_err(gt, "GuC engine reset request failed on %d:%d because 0x%08X", 2121 guc_class, instance, reason); 2122 2123 xe_gt_reset_async(gt); 2124 2125 return 0; 2126 } 2127 2128 static void 2129 guc_exec_queue_wq_snapshot_capture(struct xe_exec_queue *q, 2130 struct xe_guc_submit_exec_queue_snapshot *snapshot) 2131 { 2132 struct xe_guc *guc = exec_queue_to_guc(q); 2133 struct xe_device *xe = guc_to_xe(guc); 2134 struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]); 2135 int i; 2136 2137 snapshot->guc.wqi_head = q->guc->wqi_head; 2138 snapshot->guc.wqi_tail = q->guc->wqi_tail; 2139 snapshot->parallel.wq_desc.head = parallel_read(xe, map, wq_desc.head); 2140 snapshot->parallel.wq_desc.tail = parallel_read(xe, map, wq_desc.tail); 2141 snapshot->parallel.wq_desc.status = parallel_read(xe, map, 2142 wq_desc.wq_status); 2143 2144 if (snapshot->parallel.wq_desc.head != 2145 snapshot->parallel.wq_desc.tail) { 2146 for (i = snapshot->parallel.wq_desc.head; 2147 i != snapshot->parallel.wq_desc.tail; 2148 i = (i + sizeof(u32)) % WQ_SIZE) 2149 snapshot->parallel.wq[i / sizeof(u32)] = 2150 parallel_read(xe, map, wq[i / sizeof(u32)]); 2151 } 2152 } 2153 2154 static void 2155 guc_exec_queue_wq_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, 2156 struct drm_printer *p) 2157 { 2158 int i; 2159 2160 drm_printf(p, "\tWQ head: %u (internal), %d (memory)\n", 2161 snapshot->guc.wqi_head, snapshot->parallel.wq_desc.head); 2162 drm_printf(p, "\tWQ tail: %u (internal), %d (memory)\n", 2163 snapshot->guc.wqi_tail, snapshot->parallel.wq_desc.tail); 2164 drm_printf(p, "\tWQ status: %u\n", snapshot->parallel.wq_desc.status); 2165 2166 if (snapshot->parallel.wq_desc.head != 2167 snapshot->parallel.wq_desc.tail) { 2168 for (i = snapshot->parallel.wq_desc.head; 2169 i != snapshot->parallel.wq_desc.tail; 2170 i = (i + sizeof(u32)) % WQ_SIZE) 2171 drm_printf(p, "\tWQ[%zu]: 0x%08x\n", i / sizeof(u32), 2172 snapshot->parallel.wq[i / sizeof(u32)]); 2173 } 2174 } 2175 2176 /** 2177 * xe_guc_exec_queue_snapshot_capture - Take a quick snapshot of the GuC Engine. 2178 * @q: faulty exec queue 2179 * 2180 * This can be printed out in a later stage like during dev_coredump 2181 * analysis. 2182 * 2183 * Returns: a GuC Submit Engine snapshot object that must be freed by the 2184 * caller, using `xe_guc_exec_queue_snapshot_free`. 2185 */ 2186 struct xe_guc_submit_exec_queue_snapshot * 2187 xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q) 2188 { 2189 struct xe_gpu_scheduler *sched = &q->guc->sched; 2190 struct xe_guc_submit_exec_queue_snapshot *snapshot; 2191 int i; 2192 2193 snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); 2194 2195 if (!snapshot) 2196 return NULL; 2197 2198 snapshot->guc.id = q->guc->id; 2199 memcpy(&snapshot->name, &q->name, sizeof(snapshot->name)); 2200 snapshot->class = q->class; 2201 snapshot->logical_mask = q->logical_mask; 2202 snapshot->width = q->width; 2203 snapshot->refcount = kref_read(&q->refcount); 2204 snapshot->sched_timeout = sched->base.timeout; 2205 snapshot->sched_props.timeslice_us = q->sched_props.timeslice_us; 2206 snapshot->sched_props.preempt_timeout_us = 2207 q->sched_props.preempt_timeout_us; 2208 2209 snapshot->lrc = kmalloc_array(q->width, sizeof(struct xe_lrc_snapshot *), 2210 GFP_ATOMIC); 2211 2212 if (snapshot->lrc) { 2213 for (i = 0; i < q->width; ++i) { 2214 struct xe_lrc *lrc = q->lrc[i]; 2215 2216 snapshot->lrc[i] = xe_lrc_snapshot_capture(lrc); 2217 } 2218 } 2219 2220 snapshot->schedule_state = atomic_read(&q->guc->state); 2221 snapshot->exec_queue_flags = q->flags; 2222 2223 snapshot->parallel_execution = xe_exec_queue_is_parallel(q); 2224 if (snapshot->parallel_execution) 2225 guc_exec_queue_wq_snapshot_capture(q, snapshot); 2226 2227 spin_lock(&sched->base.job_list_lock); 2228 snapshot->pending_list_size = list_count_nodes(&sched->base.pending_list); 2229 snapshot->pending_list = kmalloc_array(snapshot->pending_list_size, 2230 sizeof(struct pending_list_snapshot), 2231 GFP_ATOMIC); 2232 2233 if (snapshot->pending_list) { 2234 struct xe_sched_job *job_iter; 2235 2236 i = 0; 2237 list_for_each_entry(job_iter, &sched->base.pending_list, drm.list) { 2238 snapshot->pending_list[i].seqno = 2239 xe_sched_job_seqno(job_iter); 2240 snapshot->pending_list[i].fence = 2241 dma_fence_is_signaled(job_iter->fence) ? 1 : 0; 2242 snapshot->pending_list[i].finished = 2243 dma_fence_is_signaled(&job_iter->drm.s_fence->finished) 2244 ? 1 : 0; 2245 i++; 2246 } 2247 } 2248 2249 spin_unlock(&sched->base.job_list_lock); 2250 2251 return snapshot; 2252 } 2253 2254 /** 2255 * xe_guc_exec_queue_snapshot_capture_delayed - Take delayed part of snapshot of the GuC Engine. 2256 * @snapshot: Previously captured snapshot of job. 2257 * 2258 * This captures some data that requires taking some locks, so it cannot be done in signaling path. 2259 */ 2260 void 2261 xe_guc_exec_queue_snapshot_capture_delayed(struct xe_guc_submit_exec_queue_snapshot *snapshot) 2262 { 2263 int i; 2264 2265 if (!snapshot || !snapshot->lrc) 2266 return; 2267 2268 for (i = 0; i < snapshot->width; ++i) 2269 xe_lrc_snapshot_capture_delayed(snapshot->lrc[i]); 2270 } 2271 2272 /** 2273 * xe_guc_exec_queue_snapshot_print - Print out a given GuC Engine snapshot. 2274 * @snapshot: GuC Submit Engine snapshot object. 2275 * @p: drm_printer where it will be printed out. 2276 * 2277 * This function prints out a given GuC Submit Engine snapshot object. 2278 */ 2279 void 2280 xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, 2281 struct drm_printer *p) 2282 { 2283 int i; 2284 2285 if (!snapshot) 2286 return; 2287 2288 drm_printf(p, "GuC ID: %d\n", snapshot->guc.id); 2289 drm_printf(p, "\tName: %s\n", snapshot->name); 2290 drm_printf(p, "\tClass: %d\n", snapshot->class); 2291 drm_printf(p, "\tLogical mask: 0x%x\n", snapshot->logical_mask); 2292 drm_printf(p, "\tWidth: %d\n", snapshot->width); 2293 drm_printf(p, "\tRef: %d\n", snapshot->refcount); 2294 drm_printf(p, "\tTimeout: %ld (ms)\n", snapshot->sched_timeout); 2295 drm_printf(p, "\tTimeslice: %u (us)\n", 2296 snapshot->sched_props.timeslice_us); 2297 drm_printf(p, "\tPreempt timeout: %u (us)\n", 2298 snapshot->sched_props.preempt_timeout_us); 2299 2300 for (i = 0; snapshot->lrc && i < snapshot->width; ++i) 2301 xe_lrc_snapshot_print(snapshot->lrc[i], p); 2302 2303 drm_printf(p, "\tSchedule State: 0x%x\n", snapshot->schedule_state); 2304 drm_printf(p, "\tFlags: 0x%lx\n", snapshot->exec_queue_flags); 2305 2306 if (snapshot->parallel_execution) 2307 guc_exec_queue_wq_snapshot_print(snapshot, p); 2308 2309 for (i = 0; snapshot->pending_list && i < snapshot->pending_list_size; 2310 i++) 2311 drm_printf(p, "\tJob: seqno=%d, fence=%d, finished=%d\n", 2312 snapshot->pending_list[i].seqno, 2313 snapshot->pending_list[i].fence, 2314 snapshot->pending_list[i].finished); 2315 } 2316 2317 /** 2318 * xe_guc_exec_queue_snapshot_free - Free all allocated objects for a given 2319 * snapshot. 2320 * @snapshot: GuC Submit Engine snapshot object. 2321 * 2322 * This function free all the memory that needed to be allocated at capture 2323 * time. 2324 */ 2325 void xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot) 2326 { 2327 int i; 2328 2329 if (!snapshot) 2330 return; 2331 2332 if (snapshot->lrc) { 2333 for (i = 0; i < snapshot->width; i++) 2334 xe_lrc_snapshot_free(snapshot->lrc[i]); 2335 kfree(snapshot->lrc); 2336 } 2337 kfree(snapshot->pending_list); 2338 kfree(snapshot); 2339 } 2340 2341 static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p) 2342 { 2343 struct xe_guc_submit_exec_queue_snapshot *snapshot; 2344 2345 snapshot = xe_guc_exec_queue_snapshot_capture(q); 2346 xe_guc_exec_queue_snapshot_print(snapshot, p); 2347 xe_guc_exec_queue_snapshot_free(snapshot); 2348 } 2349 2350 /** 2351 * xe_guc_submit_print - GuC Submit Print. 2352 * @guc: GuC. 2353 * @p: drm_printer where it will be printed out. 2354 * 2355 * This function capture and prints snapshots of **all** GuC Engines. 2356 */ 2357 void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p) 2358 { 2359 struct xe_exec_queue *q; 2360 unsigned long index; 2361 2362 if (!xe_device_uc_enabled(guc_to_xe(guc))) 2363 return; 2364 2365 mutex_lock(&guc->submission_state.lock); 2366 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) 2367 guc_exec_queue_print(q, p); 2368 mutex_unlock(&guc->submission_state.lock); 2369 } 2370