xref: /linux/drivers/gpu/drm/xe/xe_guc_submit.c (revision bcfe43f0ea77c42c2154fb79b99b7d1d82ac3231)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #include "xe_guc_submit.h"
7 
8 #include <linux/bitfield.h>
9 #include <linux/bitmap.h>
10 #include <linux/circ_buf.h>
11 #include <linux/delay.h>
12 #include <linux/dma-fence-array.h>
13 #include <linux/math64.h>
14 
15 #include <drm/drm_managed.h>
16 
17 #include "abi/guc_actions_abi.h"
18 #include "abi/guc_klvs_abi.h"
19 #include "regs/xe_lrc_layout.h"
20 #include "xe_assert.h"
21 #include "xe_devcoredump.h"
22 #include "xe_device.h"
23 #include "xe_exec_queue.h"
24 #include "xe_force_wake.h"
25 #include "xe_gpu_scheduler.h"
26 #include "xe_gt.h"
27 #include "xe_gt_clock.h"
28 #include "xe_gt_printk.h"
29 #include "xe_guc.h"
30 #include "xe_guc_capture.h"
31 #include "xe_guc_ct.h"
32 #include "xe_guc_exec_queue_types.h"
33 #include "xe_guc_id_mgr.h"
34 #include "xe_guc_submit_types.h"
35 #include "xe_hw_engine.h"
36 #include "xe_hw_fence.h"
37 #include "xe_lrc.h"
38 #include "xe_macros.h"
39 #include "xe_map.h"
40 #include "xe_mocs.h"
41 #include "xe_pm.h"
42 #include "xe_ring_ops_types.h"
43 #include "xe_sched_job.h"
44 #include "xe_trace.h"
45 #include "xe_vm.h"
46 
47 static struct xe_guc *
48 exec_queue_to_guc(struct xe_exec_queue *q)
49 {
50 	return &q->gt->uc.guc;
51 }
52 
53 /*
54  * Helpers for engine state, using an atomic as some of the bits can transition
55  * as the same time (e.g. a suspend can be happning at the same time as schedule
56  * engine done being processed).
57  */
58 #define EXEC_QUEUE_STATE_REGISTERED		(1 << 0)
59 #define EXEC_QUEUE_STATE_ENABLED		(1 << 1)
60 #define EXEC_QUEUE_STATE_PENDING_ENABLE		(1 << 2)
61 #define EXEC_QUEUE_STATE_PENDING_DISABLE	(1 << 3)
62 #define EXEC_QUEUE_STATE_DESTROYED		(1 << 4)
63 #define EXEC_QUEUE_STATE_SUSPENDED		(1 << 5)
64 #define EXEC_QUEUE_STATE_RESET			(1 << 6)
65 #define EXEC_QUEUE_STATE_KILLED			(1 << 7)
66 #define EXEC_QUEUE_STATE_WEDGED			(1 << 8)
67 #define EXEC_QUEUE_STATE_BANNED			(1 << 9)
68 #define EXEC_QUEUE_STATE_CHECK_TIMEOUT		(1 << 10)
69 #define EXEC_QUEUE_STATE_EXTRA_REF		(1 << 11)
70 
71 static bool exec_queue_registered(struct xe_exec_queue *q)
72 {
73 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_REGISTERED;
74 }
75 
76 static void set_exec_queue_registered(struct xe_exec_queue *q)
77 {
78 	atomic_or(EXEC_QUEUE_STATE_REGISTERED, &q->guc->state);
79 }
80 
81 static void clear_exec_queue_registered(struct xe_exec_queue *q)
82 {
83 	atomic_and(~EXEC_QUEUE_STATE_REGISTERED, &q->guc->state);
84 }
85 
86 static bool exec_queue_enabled(struct xe_exec_queue *q)
87 {
88 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_ENABLED;
89 }
90 
91 static void set_exec_queue_enabled(struct xe_exec_queue *q)
92 {
93 	atomic_or(EXEC_QUEUE_STATE_ENABLED, &q->guc->state);
94 }
95 
96 static void clear_exec_queue_enabled(struct xe_exec_queue *q)
97 {
98 	atomic_and(~EXEC_QUEUE_STATE_ENABLED, &q->guc->state);
99 }
100 
101 static bool exec_queue_pending_enable(struct xe_exec_queue *q)
102 {
103 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_ENABLE;
104 }
105 
106 static void set_exec_queue_pending_enable(struct xe_exec_queue *q)
107 {
108 	atomic_or(EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state);
109 }
110 
111 static void clear_exec_queue_pending_enable(struct xe_exec_queue *q)
112 {
113 	atomic_and(~EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state);
114 }
115 
116 static bool exec_queue_pending_disable(struct xe_exec_queue *q)
117 {
118 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_DISABLE;
119 }
120 
121 static void set_exec_queue_pending_disable(struct xe_exec_queue *q)
122 {
123 	atomic_or(EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state);
124 }
125 
126 static void clear_exec_queue_pending_disable(struct xe_exec_queue *q)
127 {
128 	atomic_and(~EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state);
129 }
130 
131 static bool exec_queue_destroyed(struct xe_exec_queue *q)
132 {
133 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_DESTROYED;
134 }
135 
136 static void set_exec_queue_destroyed(struct xe_exec_queue *q)
137 {
138 	atomic_or(EXEC_QUEUE_STATE_DESTROYED, &q->guc->state);
139 }
140 
141 static bool exec_queue_banned(struct xe_exec_queue *q)
142 {
143 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_BANNED;
144 }
145 
146 static void set_exec_queue_banned(struct xe_exec_queue *q)
147 {
148 	atomic_or(EXEC_QUEUE_STATE_BANNED, &q->guc->state);
149 }
150 
151 static bool exec_queue_suspended(struct xe_exec_queue *q)
152 {
153 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_SUSPENDED;
154 }
155 
156 static void set_exec_queue_suspended(struct xe_exec_queue *q)
157 {
158 	atomic_or(EXEC_QUEUE_STATE_SUSPENDED, &q->guc->state);
159 }
160 
161 static void clear_exec_queue_suspended(struct xe_exec_queue *q)
162 {
163 	atomic_and(~EXEC_QUEUE_STATE_SUSPENDED, &q->guc->state);
164 }
165 
166 static bool exec_queue_reset(struct xe_exec_queue *q)
167 {
168 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_RESET;
169 }
170 
171 static void set_exec_queue_reset(struct xe_exec_queue *q)
172 {
173 	atomic_or(EXEC_QUEUE_STATE_RESET, &q->guc->state);
174 }
175 
176 static bool exec_queue_killed(struct xe_exec_queue *q)
177 {
178 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_KILLED;
179 }
180 
181 static void set_exec_queue_killed(struct xe_exec_queue *q)
182 {
183 	atomic_or(EXEC_QUEUE_STATE_KILLED, &q->guc->state);
184 }
185 
186 static bool exec_queue_wedged(struct xe_exec_queue *q)
187 {
188 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_WEDGED;
189 }
190 
191 static void set_exec_queue_wedged(struct xe_exec_queue *q)
192 {
193 	atomic_or(EXEC_QUEUE_STATE_WEDGED, &q->guc->state);
194 }
195 
196 static bool exec_queue_check_timeout(struct xe_exec_queue *q)
197 {
198 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_CHECK_TIMEOUT;
199 }
200 
201 static void set_exec_queue_check_timeout(struct xe_exec_queue *q)
202 {
203 	atomic_or(EXEC_QUEUE_STATE_CHECK_TIMEOUT, &q->guc->state);
204 }
205 
206 static void clear_exec_queue_check_timeout(struct xe_exec_queue *q)
207 {
208 	atomic_and(~EXEC_QUEUE_STATE_CHECK_TIMEOUT, &q->guc->state);
209 }
210 
211 static bool exec_queue_extra_ref(struct xe_exec_queue *q)
212 {
213 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_EXTRA_REF;
214 }
215 
216 static void set_exec_queue_extra_ref(struct xe_exec_queue *q)
217 {
218 	atomic_or(EXEC_QUEUE_STATE_EXTRA_REF, &q->guc->state);
219 }
220 
221 static bool exec_queue_killed_or_banned_or_wedged(struct xe_exec_queue *q)
222 {
223 	return (atomic_read(&q->guc->state) &
224 		(EXEC_QUEUE_STATE_WEDGED | EXEC_QUEUE_STATE_KILLED |
225 		 EXEC_QUEUE_STATE_BANNED));
226 }
227 
228 #ifdef CONFIG_PROVE_LOCKING
229 static int alloc_submit_wq(struct xe_guc *guc)
230 {
231 	int i;
232 
233 	for (i = 0; i < NUM_SUBMIT_WQ; ++i) {
234 		guc->submission_state.submit_wq_pool[i] =
235 			alloc_ordered_workqueue("submit_wq", 0);
236 		if (!guc->submission_state.submit_wq_pool[i])
237 			goto err_free;
238 	}
239 
240 	return 0;
241 
242 err_free:
243 	while (i)
244 		destroy_workqueue(guc->submission_state.submit_wq_pool[--i]);
245 
246 	return -ENOMEM;
247 }
248 
249 static void free_submit_wq(struct xe_guc *guc)
250 {
251 	int i;
252 
253 	for (i = 0; i < NUM_SUBMIT_WQ; ++i)
254 		destroy_workqueue(guc->submission_state.submit_wq_pool[i]);
255 }
256 
257 static struct workqueue_struct *get_submit_wq(struct xe_guc *guc)
258 {
259 	int idx = guc->submission_state.submit_wq_idx++ % NUM_SUBMIT_WQ;
260 
261 	return guc->submission_state.submit_wq_pool[idx];
262 }
263 #else
264 static int alloc_submit_wq(struct xe_guc *guc)
265 {
266 	return 0;
267 }
268 
269 static void free_submit_wq(struct xe_guc *guc)
270 {
271 
272 }
273 
274 static struct workqueue_struct *get_submit_wq(struct xe_guc *guc)
275 {
276 	return NULL;
277 }
278 #endif
279 
280 static void xe_guc_submit_fini(struct xe_guc *guc)
281 {
282 	struct xe_device *xe = guc_to_xe(guc);
283 	struct xe_gt *gt = guc_to_gt(guc);
284 	int ret;
285 
286 	ret = wait_event_timeout(guc->submission_state.fini_wq,
287 				 xa_empty(&guc->submission_state.exec_queue_lookup),
288 				 HZ * 5);
289 
290 	drain_workqueue(xe->destroy_wq);
291 
292 	xe_gt_assert(gt, ret);
293 }
294 
295 static void guc_submit_fini(struct drm_device *drm, void *arg)
296 {
297 	struct xe_guc *guc = arg;
298 
299 	xe_guc_submit_fini(guc);
300 	xa_destroy(&guc->submission_state.exec_queue_lookup);
301 	free_submit_wq(guc);
302 }
303 
304 static void guc_submit_wedged_fini(void *arg)
305 {
306 	struct xe_guc *guc = arg;
307 	struct xe_exec_queue *q;
308 	unsigned long index;
309 
310 	mutex_lock(&guc->submission_state.lock);
311 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) {
312 		if (exec_queue_wedged(q)) {
313 			mutex_unlock(&guc->submission_state.lock);
314 			xe_exec_queue_put(q);
315 			mutex_lock(&guc->submission_state.lock);
316 		}
317 	}
318 	mutex_unlock(&guc->submission_state.lock);
319 }
320 
321 static const struct xe_exec_queue_ops guc_exec_queue_ops;
322 
323 static void primelockdep(struct xe_guc *guc)
324 {
325 	if (!IS_ENABLED(CONFIG_LOCKDEP))
326 		return;
327 
328 	fs_reclaim_acquire(GFP_KERNEL);
329 
330 	mutex_lock(&guc->submission_state.lock);
331 	mutex_unlock(&guc->submission_state.lock);
332 
333 	fs_reclaim_release(GFP_KERNEL);
334 }
335 
336 /**
337  * xe_guc_submit_init() - Initialize GuC submission.
338  * @guc: the &xe_guc to initialize
339  * @num_ids: number of GuC context IDs to use
340  *
341  * The bare-metal or PF driver can pass ~0 as &num_ids to indicate that all
342  * GuC context IDs supported by the GuC firmware should be used for submission.
343  *
344  * Only VF drivers will have to provide explicit number of GuC context IDs
345  * that they can use for submission.
346  *
347  * Return: 0 on success or a negative error code on failure.
348  */
349 int xe_guc_submit_init(struct xe_guc *guc, unsigned int num_ids)
350 {
351 	struct xe_device *xe = guc_to_xe(guc);
352 	struct xe_gt *gt = guc_to_gt(guc);
353 	int err;
354 
355 	err = drmm_mutex_init(&xe->drm, &guc->submission_state.lock);
356 	if (err)
357 		return err;
358 
359 	err = xe_guc_id_mgr_init(&guc->submission_state.idm, num_ids);
360 	if (err)
361 		return err;
362 
363 	err = alloc_submit_wq(guc);
364 	if (err)
365 		return err;
366 
367 	gt->exec_queue_ops = &guc_exec_queue_ops;
368 
369 	xa_init(&guc->submission_state.exec_queue_lookup);
370 
371 	init_waitqueue_head(&guc->submission_state.fini_wq);
372 
373 	primelockdep(guc);
374 
375 	return drmm_add_action_or_reset(&xe->drm, guc_submit_fini, guc);
376 }
377 
378 static void __release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q, u32 xa_count)
379 {
380 	int i;
381 
382 	lockdep_assert_held(&guc->submission_state.lock);
383 
384 	for (i = 0; i < xa_count; ++i)
385 		xa_erase(&guc->submission_state.exec_queue_lookup, q->guc->id + i);
386 
387 	xe_guc_id_mgr_release_locked(&guc->submission_state.idm,
388 				     q->guc->id, q->width);
389 
390 	if (xa_empty(&guc->submission_state.exec_queue_lookup))
391 		wake_up(&guc->submission_state.fini_wq);
392 }
393 
394 static int alloc_guc_id(struct xe_guc *guc, struct xe_exec_queue *q)
395 {
396 	int ret;
397 	int i;
398 
399 	/*
400 	 * Must use GFP_NOWAIT as this lock is in the dma fence signalling path,
401 	 * worse case user gets -ENOMEM on engine create and has to try again.
402 	 *
403 	 * FIXME: Have caller pre-alloc or post-alloc /w GFP_KERNEL to prevent
404 	 * failure.
405 	 */
406 	lockdep_assert_held(&guc->submission_state.lock);
407 
408 	ret = xe_guc_id_mgr_reserve_locked(&guc->submission_state.idm,
409 					   q->width);
410 	if (ret < 0)
411 		return ret;
412 
413 	q->guc->id = ret;
414 
415 	for (i = 0; i < q->width; ++i) {
416 		ret = xa_err(xa_store(&guc->submission_state.exec_queue_lookup,
417 				      q->guc->id + i, q, GFP_NOWAIT));
418 		if (ret)
419 			goto err_release;
420 	}
421 
422 	return 0;
423 
424 err_release:
425 	__release_guc_id(guc, q, i);
426 
427 	return ret;
428 }
429 
430 static void release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q)
431 {
432 	mutex_lock(&guc->submission_state.lock);
433 	__release_guc_id(guc, q, q->width);
434 	mutex_unlock(&guc->submission_state.lock);
435 }
436 
437 struct exec_queue_policy {
438 	u32 count;
439 	struct guc_update_exec_queue_policy h2g;
440 };
441 
442 static u32 __guc_exec_queue_policy_action_size(struct exec_queue_policy *policy)
443 {
444 	size_t bytes = sizeof(policy->h2g.header) +
445 		       (sizeof(policy->h2g.klv[0]) * policy->count);
446 
447 	return bytes / sizeof(u32);
448 }
449 
450 static void __guc_exec_queue_policy_start_klv(struct exec_queue_policy *policy,
451 					      u16 guc_id)
452 {
453 	policy->h2g.header.action =
454 		XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES;
455 	policy->h2g.header.guc_id = guc_id;
456 	policy->count = 0;
457 }
458 
459 #define MAKE_EXEC_QUEUE_POLICY_ADD(func, id) \
460 static void __guc_exec_queue_policy_add_##func(struct exec_queue_policy *policy, \
461 					   u32 data) \
462 { \
463 	XE_WARN_ON(policy->count >= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \
464 \
465 	policy->h2g.klv[policy->count].kl = \
466 		FIELD_PREP(GUC_KLV_0_KEY, \
467 			   GUC_CONTEXT_POLICIES_KLV_ID_##id) | \
468 		FIELD_PREP(GUC_KLV_0_LEN, 1); \
469 	policy->h2g.klv[policy->count].value = data; \
470 	policy->count++; \
471 }
472 
473 MAKE_EXEC_QUEUE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM)
474 MAKE_EXEC_QUEUE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT)
475 MAKE_EXEC_QUEUE_POLICY_ADD(priority, SCHEDULING_PRIORITY)
476 #undef MAKE_EXEC_QUEUE_POLICY_ADD
477 
478 static const int xe_exec_queue_prio_to_guc[] = {
479 	[XE_EXEC_QUEUE_PRIORITY_LOW] = GUC_CLIENT_PRIORITY_NORMAL,
480 	[XE_EXEC_QUEUE_PRIORITY_NORMAL] = GUC_CLIENT_PRIORITY_KMD_NORMAL,
481 	[XE_EXEC_QUEUE_PRIORITY_HIGH] = GUC_CLIENT_PRIORITY_HIGH,
482 	[XE_EXEC_QUEUE_PRIORITY_KERNEL] = GUC_CLIENT_PRIORITY_KMD_HIGH,
483 };
484 
485 static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q)
486 {
487 	struct exec_queue_policy policy;
488 	struct xe_device *xe = guc_to_xe(guc);
489 	enum xe_exec_queue_priority prio = q->sched_props.priority;
490 	u32 timeslice_us = q->sched_props.timeslice_us;
491 	u32 preempt_timeout_us = q->sched_props.preempt_timeout_us;
492 
493 	xe_assert(xe, exec_queue_registered(q));
494 
495 	__guc_exec_queue_policy_start_klv(&policy, q->guc->id);
496 	__guc_exec_queue_policy_add_priority(&policy, xe_exec_queue_prio_to_guc[prio]);
497 	__guc_exec_queue_policy_add_execution_quantum(&policy, timeslice_us);
498 	__guc_exec_queue_policy_add_preemption_timeout(&policy, preempt_timeout_us);
499 
500 	xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g,
501 		       __guc_exec_queue_policy_action_size(&policy), 0, 0);
502 }
503 
504 static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue *q)
505 {
506 	struct exec_queue_policy policy;
507 
508 	__guc_exec_queue_policy_start_klv(&policy, q->guc->id);
509 	__guc_exec_queue_policy_add_preemption_timeout(&policy, 1);
510 
511 	xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g,
512 		       __guc_exec_queue_policy_action_size(&policy), 0, 0);
513 }
514 
515 #define parallel_read(xe_, map_, field_) \
516 	xe_map_rd_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \
517 			field_)
518 #define parallel_write(xe_, map_, field_, val_) \
519 	xe_map_wr_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \
520 			field_, val_)
521 
522 static void __register_mlrc_exec_queue(struct xe_guc *guc,
523 				       struct xe_exec_queue *q,
524 				       struct guc_ctxt_registration_info *info)
525 {
526 #define MAX_MLRC_REG_SIZE      (13 + XE_HW_ENGINE_MAX_INSTANCE * 2)
527 	struct xe_device *xe = guc_to_xe(guc);
528 	u32 action[MAX_MLRC_REG_SIZE];
529 	int len = 0;
530 	int i;
531 
532 	xe_assert(xe, xe_exec_queue_is_parallel(q));
533 
534 	action[len++] = XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC;
535 	action[len++] = info->flags;
536 	action[len++] = info->context_idx;
537 	action[len++] = info->engine_class;
538 	action[len++] = info->engine_submit_mask;
539 	action[len++] = info->wq_desc_lo;
540 	action[len++] = info->wq_desc_hi;
541 	action[len++] = info->wq_base_lo;
542 	action[len++] = info->wq_base_hi;
543 	action[len++] = info->wq_size;
544 	action[len++] = q->width;
545 	action[len++] = info->hwlrca_lo;
546 	action[len++] = info->hwlrca_hi;
547 
548 	for (i = 1; i < q->width; ++i) {
549 		struct xe_lrc *lrc = q->lrc[i];
550 
551 		action[len++] = lower_32_bits(xe_lrc_descriptor(lrc));
552 		action[len++] = upper_32_bits(xe_lrc_descriptor(lrc));
553 	}
554 
555 	xe_assert(xe, len <= MAX_MLRC_REG_SIZE);
556 #undef MAX_MLRC_REG_SIZE
557 
558 	xe_guc_ct_send(&guc->ct, action, len, 0, 0);
559 }
560 
561 static void __register_exec_queue(struct xe_guc *guc,
562 				  struct guc_ctxt_registration_info *info)
563 {
564 	u32 action[] = {
565 		XE_GUC_ACTION_REGISTER_CONTEXT,
566 		info->flags,
567 		info->context_idx,
568 		info->engine_class,
569 		info->engine_submit_mask,
570 		info->wq_desc_lo,
571 		info->wq_desc_hi,
572 		info->wq_base_lo,
573 		info->wq_base_hi,
574 		info->wq_size,
575 		info->hwlrca_lo,
576 		info->hwlrca_hi,
577 	};
578 
579 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
580 }
581 
582 static void register_exec_queue(struct xe_exec_queue *q)
583 {
584 	struct xe_guc *guc = exec_queue_to_guc(q);
585 	struct xe_device *xe = guc_to_xe(guc);
586 	struct xe_lrc *lrc = q->lrc[0];
587 	struct guc_ctxt_registration_info info;
588 
589 	xe_assert(xe, !exec_queue_registered(q));
590 
591 	memset(&info, 0, sizeof(info));
592 	info.context_idx = q->guc->id;
593 	info.engine_class = xe_engine_class_to_guc_class(q->class);
594 	info.engine_submit_mask = q->logical_mask;
595 	info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc));
596 	info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc));
597 	info.flags = CONTEXT_REGISTRATION_FLAG_KMD;
598 
599 	if (xe_exec_queue_is_parallel(q)) {
600 		u64 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc);
601 		struct iosys_map map = xe_lrc_parallel_map(lrc);
602 
603 		info.wq_desc_lo = lower_32_bits(ggtt_addr +
604 			offsetof(struct guc_submit_parallel_scratch, wq_desc));
605 		info.wq_desc_hi = upper_32_bits(ggtt_addr +
606 			offsetof(struct guc_submit_parallel_scratch, wq_desc));
607 		info.wq_base_lo = lower_32_bits(ggtt_addr +
608 			offsetof(struct guc_submit_parallel_scratch, wq[0]));
609 		info.wq_base_hi = upper_32_bits(ggtt_addr +
610 			offsetof(struct guc_submit_parallel_scratch, wq[0]));
611 		info.wq_size = WQ_SIZE;
612 
613 		q->guc->wqi_head = 0;
614 		q->guc->wqi_tail = 0;
615 		xe_map_memset(xe, &map, 0, 0, PARALLEL_SCRATCH_SIZE - WQ_SIZE);
616 		parallel_write(xe, map, wq_desc.wq_status, WQ_STATUS_ACTIVE);
617 	}
618 
619 	/*
620 	 * We must keep a reference for LR engines if engine is registered with
621 	 * the GuC as jobs signal immediately and can't destroy an engine if the
622 	 * GuC has a reference to it.
623 	 */
624 	if (xe_exec_queue_is_lr(q))
625 		xe_exec_queue_get(q);
626 
627 	set_exec_queue_registered(q);
628 	trace_xe_exec_queue_register(q);
629 	if (xe_exec_queue_is_parallel(q))
630 		__register_mlrc_exec_queue(guc, q, &info);
631 	else
632 		__register_exec_queue(guc, &info);
633 	init_policies(guc, q);
634 }
635 
636 static u32 wq_space_until_wrap(struct xe_exec_queue *q)
637 {
638 	return (WQ_SIZE - q->guc->wqi_tail);
639 }
640 
641 static int wq_wait_for_space(struct xe_exec_queue *q, u32 wqi_size)
642 {
643 	struct xe_guc *guc = exec_queue_to_guc(q);
644 	struct xe_device *xe = guc_to_xe(guc);
645 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
646 	unsigned int sleep_period_ms = 1;
647 
648 #define AVAILABLE_SPACE \
649 	CIRC_SPACE(q->guc->wqi_tail, q->guc->wqi_head, WQ_SIZE)
650 	if (wqi_size > AVAILABLE_SPACE) {
651 try_again:
652 		q->guc->wqi_head = parallel_read(xe, map, wq_desc.head);
653 		if (wqi_size > AVAILABLE_SPACE) {
654 			if (sleep_period_ms == 1024) {
655 				xe_gt_reset_async(q->gt);
656 				return -ENODEV;
657 			}
658 
659 			msleep(sleep_period_ms);
660 			sleep_period_ms <<= 1;
661 			goto try_again;
662 		}
663 	}
664 #undef AVAILABLE_SPACE
665 
666 	return 0;
667 }
668 
669 static int wq_noop_append(struct xe_exec_queue *q)
670 {
671 	struct xe_guc *guc = exec_queue_to_guc(q);
672 	struct xe_device *xe = guc_to_xe(guc);
673 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
674 	u32 len_dw = wq_space_until_wrap(q) / sizeof(u32) - 1;
675 
676 	if (wq_wait_for_space(q, wq_space_until_wrap(q)))
677 		return -ENODEV;
678 
679 	xe_assert(xe, FIELD_FIT(WQ_LEN_MASK, len_dw));
680 
681 	parallel_write(xe, map, wq[q->guc->wqi_tail / sizeof(u32)],
682 		       FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_NOOP) |
683 		       FIELD_PREP(WQ_LEN_MASK, len_dw));
684 	q->guc->wqi_tail = 0;
685 
686 	return 0;
687 }
688 
689 static void wq_item_append(struct xe_exec_queue *q)
690 {
691 	struct xe_guc *guc = exec_queue_to_guc(q);
692 	struct xe_device *xe = guc_to_xe(guc);
693 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
694 #define WQ_HEADER_SIZE	4	/* Includes 1 LRC address too */
695 	u32 wqi[XE_HW_ENGINE_MAX_INSTANCE + (WQ_HEADER_SIZE - 1)];
696 	u32 wqi_size = (q->width + (WQ_HEADER_SIZE - 1)) * sizeof(u32);
697 	u32 len_dw = (wqi_size / sizeof(u32)) - 1;
698 	int i = 0, j;
699 
700 	if (wqi_size > wq_space_until_wrap(q)) {
701 		if (wq_noop_append(q))
702 			return;
703 	}
704 	if (wq_wait_for_space(q, wqi_size))
705 		return;
706 
707 	wqi[i++] = FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_MULTI_LRC) |
708 		FIELD_PREP(WQ_LEN_MASK, len_dw);
709 	wqi[i++] = xe_lrc_descriptor(q->lrc[0]);
710 	wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, q->guc->id) |
711 		FIELD_PREP(WQ_RING_TAIL_MASK, q->lrc[0]->ring.tail / sizeof(u64));
712 	wqi[i++] = 0;
713 	for (j = 1; j < q->width; ++j) {
714 		struct xe_lrc *lrc = q->lrc[j];
715 
716 		wqi[i++] = lrc->ring.tail / sizeof(u64);
717 	}
718 
719 	xe_assert(xe, i == wqi_size / sizeof(u32));
720 
721 	iosys_map_incr(&map, offsetof(struct guc_submit_parallel_scratch,
722 				      wq[q->guc->wqi_tail / sizeof(u32)]));
723 	xe_map_memcpy_to(xe, &map, 0, wqi, wqi_size);
724 	q->guc->wqi_tail += wqi_size;
725 	xe_assert(xe, q->guc->wqi_tail <= WQ_SIZE);
726 
727 	xe_device_wmb(xe);
728 
729 	map = xe_lrc_parallel_map(q->lrc[0]);
730 	parallel_write(xe, map, wq_desc.tail, q->guc->wqi_tail);
731 }
732 
733 #define RESUME_PENDING	~0x0ull
734 static void submit_exec_queue(struct xe_exec_queue *q)
735 {
736 	struct xe_guc *guc = exec_queue_to_guc(q);
737 	struct xe_device *xe = guc_to_xe(guc);
738 	struct xe_lrc *lrc = q->lrc[0];
739 	u32 action[3];
740 	u32 g2h_len = 0;
741 	u32 num_g2h = 0;
742 	int len = 0;
743 	bool extra_submit = false;
744 
745 	xe_assert(xe, exec_queue_registered(q));
746 
747 	if (xe_exec_queue_is_parallel(q))
748 		wq_item_append(q);
749 	else
750 		xe_lrc_set_ring_tail(lrc, lrc->ring.tail);
751 
752 	if (exec_queue_suspended(q) && !xe_exec_queue_is_parallel(q))
753 		return;
754 
755 	if (!exec_queue_enabled(q) && !exec_queue_suspended(q)) {
756 		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET;
757 		action[len++] = q->guc->id;
758 		action[len++] = GUC_CONTEXT_ENABLE;
759 		g2h_len = G2H_LEN_DW_SCHED_CONTEXT_MODE_SET;
760 		num_g2h = 1;
761 		if (xe_exec_queue_is_parallel(q))
762 			extra_submit = true;
763 
764 		q->guc->resume_time = RESUME_PENDING;
765 		set_exec_queue_pending_enable(q);
766 		set_exec_queue_enabled(q);
767 		trace_xe_exec_queue_scheduling_enable(q);
768 	} else {
769 		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT;
770 		action[len++] = q->guc->id;
771 		trace_xe_exec_queue_submit(q);
772 	}
773 
774 	xe_guc_ct_send(&guc->ct, action, len, g2h_len, num_g2h);
775 
776 	if (extra_submit) {
777 		len = 0;
778 		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT;
779 		action[len++] = q->guc->id;
780 		trace_xe_exec_queue_submit(q);
781 
782 		xe_guc_ct_send(&guc->ct, action, len, 0, 0);
783 	}
784 }
785 
786 static struct dma_fence *
787 guc_exec_queue_run_job(struct drm_sched_job *drm_job)
788 {
789 	struct xe_sched_job *job = to_xe_sched_job(drm_job);
790 	struct xe_exec_queue *q = job->q;
791 	struct xe_guc *guc = exec_queue_to_guc(q);
792 	struct xe_device *xe = guc_to_xe(guc);
793 	bool lr = xe_exec_queue_is_lr(q);
794 
795 	xe_assert(xe, !(exec_queue_destroyed(q) || exec_queue_pending_disable(q)) ||
796 		  exec_queue_banned(q) || exec_queue_suspended(q));
797 
798 	trace_xe_sched_job_run(job);
799 
800 	if (!exec_queue_killed_or_banned_or_wedged(q) && !xe_sched_job_is_error(job)) {
801 		if (!exec_queue_registered(q))
802 			register_exec_queue(q);
803 		if (!lr)	/* LR jobs are emitted in the exec IOCTL */
804 			q->ring_ops->emit_job(job);
805 		submit_exec_queue(q);
806 	}
807 
808 	if (lr) {
809 		xe_sched_job_set_error(job, -EOPNOTSUPP);
810 		return NULL;
811 	} else if (test_and_set_bit(JOB_FLAG_SUBMIT, &job->fence->flags)) {
812 		return job->fence;
813 	} else {
814 		return dma_fence_get(job->fence);
815 	}
816 }
817 
818 static void guc_exec_queue_free_job(struct drm_sched_job *drm_job)
819 {
820 	struct xe_sched_job *job = to_xe_sched_job(drm_job);
821 
822 	xe_exec_queue_update_run_ticks(job->q);
823 
824 	trace_xe_sched_job_free(job);
825 	xe_sched_job_put(job);
826 }
827 
828 int xe_guc_read_stopped(struct xe_guc *guc)
829 {
830 	return atomic_read(&guc->submission_state.stopped);
831 }
832 
833 #define MAKE_SCHED_CONTEXT_ACTION(q, enable_disable)			\
834 	u32 action[] = {						\
835 		XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET,			\
836 		q->guc->id,						\
837 		GUC_CONTEXT_##enable_disable,				\
838 	}
839 
840 static void disable_scheduling_deregister(struct xe_guc *guc,
841 					  struct xe_exec_queue *q)
842 {
843 	MAKE_SCHED_CONTEXT_ACTION(q, DISABLE);
844 	struct xe_device *xe = guc_to_xe(guc);
845 	int ret;
846 
847 	set_min_preemption_timeout(guc, q);
848 	smp_rmb();
849 	ret = wait_event_timeout(guc->ct.wq, !exec_queue_pending_enable(q) ||
850 				 xe_guc_read_stopped(guc), HZ * 5);
851 	if (!ret) {
852 		struct xe_gpu_scheduler *sched = &q->guc->sched;
853 
854 		drm_warn(&xe->drm, "Pending enable failed to respond");
855 		xe_sched_submission_start(sched);
856 		xe_gt_reset_async(q->gt);
857 		xe_sched_tdr_queue_imm(sched);
858 		return;
859 	}
860 
861 	clear_exec_queue_enabled(q);
862 	set_exec_queue_pending_disable(q);
863 	set_exec_queue_destroyed(q);
864 	trace_xe_exec_queue_scheduling_disable(q);
865 
866 	/*
867 	 * Reserve space for both G2H here as the 2nd G2H is sent from a G2H
868 	 * handler and we are not allowed to reserved G2H space in handlers.
869 	 */
870 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
871 		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
872 		       G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
873 }
874 
875 static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q)
876 {
877 	struct xe_guc *guc = exec_queue_to_guc(q);
878 	struct xe_device *xe = guc_to_xe(guc);
879 
880 	/** to wakeup xe_wait_user_fence ioctl if exec queue is reset */
881 	wake_up_all(&xe->ufence_wq);
882 
883 	if (xe_exec_queue_is_lr(q))
884 		queue_work(guc_to_gt(guc)->ordered_wq, &q->guc->lr_tdr);
885 	else
886 		xe_sched_tdr_queue_imm(&q->guc->sched);
887 }
888 
889 /**
890  * xe_guc_submit_wedge() - Wedge GuC submission
891  * @guc: the GuC object
892  *
893  * Save exec queue's registered with GuC state by taking a ref to each queue.
894  * Register a DRMM handler to drop refs upon driver unload.
895  */
896 void xe_guc_submit_wedge(struct xe_guc *guc)
897 {
898 	struct xe_device *xe = guc_to_xe(guc);
899 	struct xe_exec_queue *q;
900 	unsigned long index;
901 	int err;
902 
903 	xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode);
904 
905 	err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev,
906 				       guc_submit_wedged_fini, guc);
907 	if (err) {
908 		drm_err(&xe->drm, "Failed to register xe_guc_submit clean-up on wedged.mode=2. Although device is wedged.\n");
909 		return;
910 	}
911 
912 	mutex_lock(&guc->submission_state.lock);
913 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
914 		if (xe_exec_queue_get_unless_zero(q))
915 			set_exec_queue_wedged(q);
916 	mutex_unlock(&guc->submission_state.lock);
917 }
918 
919 static bool guc_submit_hint_wedged(struct xe_guc *guc)
920 {
921 	struct xe_device *xe = guc_to_xe(guc);
922 
923 	if (xe->wedged.mode != 2)
924 		return false;
925 
926 	if (xe_device_wedged(xe))
927 		return true;
928 
929 	xe_device_declare_wedged(xe);
930 
931 	return true;
932 }
933 
934 static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w)
935 {
936 	struct xe_guc_exec_queue *ge =
937 		container_of(w, struct xe_guc_exec_queue, lr_tdr);
938 	struct xe_exec_queue *q = ge->q;
939 	struct xe_guc *guc = exec_queue_to_guc(q);
940 	struct xe_device *xe = guc_to_xe(guc);
941 	struct xe_gpu_scheduler *sched = &ge->sched;
942 	bool wedged;
943 
944 	xe_assert(xe, xe_exec_queue_is_lr(q));
945 	trace_xe_exec_queue_lr_cleanup(q);
946 
947 	wedged = guc_submit_hint_wedged(exec_queue_to_guc(q));
948 
949 	/* Kill the run_job / process_msg entry points */
950 	xe_sched_submission_stop(sched);
951 
952 	/*
953 	 * Engine state now mostly stable, disable scheduling / deregister if
954 	 * needed. This cleanup routine might be called multiple times, where
955 	 * the actual async engine deregister drops the final engine ref.
956 	 * Calling disable_scheduling_deregister will mark the engine as
957 	 * destroyed and fire off the CT requests to disable scheduling /
958 	 * deregister, which we only want to do once. We also don't want to mark
959 	 * the engine as pending_disable again as this may race with the
960 	 * xe_guc_deregister_done_handler() which treats it as an unexpected
961 	 * state.
962 	 */
963 	if (!wedged && exec_queue_registered(q) && !exec_queue_destroyed(q)) {
964 		struct xe_guc *guc = exec_queue_to_guc(q);
965 		int ret;
966 
967 		set_exec_queue_banned(q);
968 		disable_scheduling_deregister(guc, q);
969 
970 		/*
971 		 * Must wait for scheduling to be disabled before signalling
972 		 * any fences, if GT broken the GT reset code should signal us.
973 		 */
974 		ret = wait_event_timeout(guc->ct.wq,
975 					 !exec_queue_pending_disable(q) ||
976 					 xe_guc_read_stopped(guc), HZ * 5);
977 		if (!ret) {
978 			drm_warn(&xe->drm, "Schedule disable failed to respond");
979 			xe_sched_submission_start(sched);
980 			xe_gt_reset_async(q->gt);
981 			return;
982 		}
983 	}
984 
985 	xe_sched_submission_start(sched);
986 }
987 
988 #define ADJUST_FIVE_PERCENT(__t)	mul_u64_u32_div(__t, 105, 100)
989 
990 static bool check_timeout(struct xe_exec_queue *q, struct xe_sched_job *job)
991 {
992 	struct xe_gt *gt = guc_to_gt(exec_queue_to_guc(q));
993 	u32 ctx_timestamp = xe_lrc_ctx_timestamp(q->lrc[0]);
994 	u32 ctx_job_timestamp = xe_lrc_ctx_job_timestamp(q->lrc[0]);
995 	u32 timeout_ms = q->sched_props.job_timeout_ms;
996 	u32 diff;
997 	u64 running_time_ms;
998 
999 	/*
1000 	 * Counter wraps at ~223s at the usual 19.2MHz, be paranoid catch
1001 	 * possible overflows with a high timeout.
1002 	 */
1003 	xe_gt_assert(gt, timeout_ms < 100 * MSEC_PER_SEC);
1004 
1005 	if (ctx_timestamp < ctx_job_timestamp)
1006 		diff = ctx_timestamp + U32_MAX - ctx_job_timestamp;
1007 	else
1008 		diff = ctx_timestamp - ctx_job_timestamp;
1009 
1010 	/*
1011 	 * Ensure timeout is within 5% to account for an GuC scheduling latency
1012 	 */
1013 	running_time_ms =
1014 		ADJUST_FIVE_PERCENT(xe_gt_clock_interval_to_ms(gt, diff));
1015 
1016 	xe_gt_dbg(gt,
1017 		  "Check job timeout: seqno=%u, lrc_seqno=%u, guc_id=%d, running_time_ms=%llu, timeout_ms=%u, diff=0x%08x",
1018 		  xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job),
1019 		  q->guc->id, running_time_ms, timeout_ms, diff);
1020 
1021 	return running_time_ms >= timeout_ms;
1022 }
1023 
1024 static void enable_scheduling(struct xe_exec_queue *q)
1025 {
1026 	MAKE_SCHED_CONTEXT_ACTION(q, ENABLE);
1027 	struct xe_guc *guc = exec_queue_to_guc(q);
1028 	int ret;
1029 
1030 	xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q));
1031 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
1032 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
1033 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q));
1034 
1035 	set_exec_queue_pending_enable(q);
1036 	set_exec_queue_enabled(q);
1037 	trace_xe_exec_queue_scheduling_enable(q);
1038 
1039 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
1040 		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);
1041 
1042 	ret = wait_event_timeout(guc->ct.wq,
1043 				 !exec_queue_pending_enable(q) ||
1044 				 xe_guc_read_stopped(guc), HZ * 5);
1045 	if (!ret || xe_guc_read_stopped(guc)) {
1046 		xe_gt_warn(guc_to_gt(guc), "Schedule enable failed to respond");
1047 		set_exec_queue_banned(q);
1048 		xe_gt_reset_async(q->gt);
1049 		xe_sched_tdr_queue_imm(&q->guc->sched);
1050 	}
1051 }
1052 
1053 static void disable_scheduling(struct xe_exec_queue *q, bool immediate)
1054 {
1055 	MAKE_SCHED_CONTEXT_ACTION(q, DISABLE);
1056 	struct xe_guc *guc = exec_queue_to_guc(q);
1057 
1058 	xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q));
1059 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
1060 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
1061 
1062 	if (immediate)
1063 		set_min_preemption_timeout(guc, q);
1064 	clear_exec_queue_enabled(q);
1065 	set_exec_queue_pending_disable(q);
1066 	trace_xe_exec_queue_scheduling_disable(q);
1067 
1068 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
1069 		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);
1070 }
1071 
1072 static void __deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
1073 {
1074 	u32 action[] = {
1075 		XE_GUC_ACTION_DEREGISTER_CONTEXT,
1076 		q->guc->id,
1077 	};
1078 
1079 	xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q));
1080 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
1081 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q));
1082 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
1083 
1084 	set_exec_queue_destroyed(q);
1085 	trace_xe_exec_queue_deregister(q);
1086 
1087 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
1088 		       G2H_LEN_DW_DEREGISTER_CONTEXT, 1);
1089 }
1090 
1091 static enum drm_gpu_sched_stat
1092 guc_exec_queue_timedout_job(struct drm_sched_job *drm_job)
1093 {
1094 	struct xe_sched_job *job = to_xe_sched_job(drm_job);
1095 	struct xe_sched_job *tmp_job;
1096 	struct xe_exec_queue *q = job->q;
1097 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1098 	struct xe_guc *guc = exec_queue_to_guc(q);
1099 	const char *process_name = "no process";
1100 	struct xe_device *xe = guc_to_xe(guc);
1101 	int err = -ETIME;
1102 	pid_t pid = -1;
1103 	int i = 0;
1104 	bool wedged, skip_timeout_check;
1105 
1106 	/*
1107 	 * TDR has fired before free job worker. Common if exec queue
1108 	 * immediately closed after last fence signaled. Add back to pending
1109 	 * list so job can be freed and kick scheduler ensuring free job is not
1110 	 * lost.
1111 	 */
1112 	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &job->fence->flags)) {
1113 		xe_sched_add_pending_job(sched, job);
1114 		xe_sched_submission_start(sched);
1115 
1116 		return DRM_GPU_SCHED_STAT_NOMINAL;
1117 	}
1118 
1119 	/* Kill the run_job entry point */
1120 	xe_sched_submission_stop(sched);
1121 
1122 	/* Must check all state after stopping scheduler */
1123 	skip_timeout_check = exec_queue_reset(q) ||
1124 		exec_queue_killed_or_banned_or_wedged(q) ||
1125 		exec_queue_destroyed(q);
1126 
1127 	/* Job hasn't started, can't be timed out */
1128 	if (!skip_timeout_check && !xe_sched_job_started(job))
1129 		goto rearm;
1130 
1131 	/*
1132 	 * If devcoredump not captured and GuC capture for the job is not ready
1133 	 * do manual capture first and decide later if we need to use it
1134 	 */
1135 	if (!exec_queue_killed(q) && !xe->devcoredump.captured &&
1136 	    !xe_guc_capture_get_matching_and_lock(job)) {
1137 		/* take force wake before engine register manual capture */
1138 		if (xe_force_wake_get(gt_to_fw(q->gt), XE_FORCEWAKE_ALL))
1139 			xe_gt_info(q->gt, "failed to get forcewake for coredump capture\n");
1140 
1141 		xe_engine_snapshot_capture_for_job(job);
1142 
1143 		xe_force_wake_put(gt_to_fw(q->gt), XE_FORCEWAKE_ALL);
1144 	}
1145 
1146 	/*
1147 	 * XXX: Sampling timeout doesn't work in wedged mode as we have to
1148 	 * modify scheduling state to read timestamp. We could read the
1149 	 * timestamp from a register to accumulate current running time but this
1150 	 * doesn't work for SRIOV. For now assuming timeouts in wedged mode are
1151 	 * genuine timeouts.
1152 	 */
1153 	wedged = guc_submit_hint_wedged(exec_queue_to_guc(q));
1154 
1155 	/* Engine state now stable, disable scheduling to check timestamp */
1156 	if (!wedged && exec_queue_registered(q)) {
1157 		int ret;
1158 
1159 		if (exec_queue_reset(q))
1160 			err = -EIO;
1161 
1162 		if (!exec_queue_destroyed(q)) {
1163 			/*
1164 			 * Wait for any pending G2H to flush out before
1165 			 * modifying state
1166 			 */
1167 			ret = wait_event_timeout(guc->ct.wq,
1168 						 !exec_queue_pending_enable(q) ||
1169 						 xe_guc_read_stopped(guc), HZ * 5);
1170 			if (!ret || xe_guc_read_stopped(guc))
1171 				goto trigger_reset;
1172 
1173 			/*
1174 			 * Flag communicates to G2H handler that schedule
1175 			 * disable originated from a timeout check. The G2H then
1176 			 * avoid triggering cleanup or deregistering the exec
1177 			 * queue.
1178 			 */
1179 			set_exec_queue_check_timeout(q);
1180 			disable_scheduling(q, skip_timeout_check);
1181 		}
1182 
1183 		/*
1184 		 * Must wait for scheduling to be disabled before signalling
1185 		 * any fences, if GT broken the GT reset code should signal us.
1186 		 *
1187 		 * FIXME: Tests can generate a ton of 0x6000 (IOMMU CAT fault
1188 		 * error) messages which can cause the schedule disable to get
1189 		 * lost. If this occurs, trigger a GT reset to recover.
1190 		 */
1191 		smp_rmb();
1192 		ret = wait_event_timeout(guc->ct.wq,
1193 					 !exec_queue_pending_disable(q) ||
1194 					 xe_guc_read_stopped(guc), HZ * 5);
1195 		if (!ret || xe_guc_read_stopped(guc)) {
1196 trigger_reset:
1197 			if (!ret)
1198 				xe_gt_warn(guc_to_gt(guc), "Schedule disable failed to respond");
1199 			set_exec_queue_extra_ref(q);
1200 			xe_exec_queue_get(q);	/* GT reset owns this */
1201 			set_exec_queue_banned(q);
1202 			xe_gt_reset_async(q->gt);
1203 			xe_sched_tdr_queue_imm(sched);
1204 			goto rearm;
1205 		}
1206 	}
1207 
1208 	/*
1209 	 * Check if job is actually timed out, if so restart job execution and TDR
1210 	 */
1211 	if (!wedged && !skip_timeout_check && !check_timeout(q, job) &&
1212 	    !exec_queue_reset(q) && exec_queue_registered(q)) {
1213 		clear_exec_queue_check_timeout(q);
1214 		goto sched_enable;
1215 	}
1216 
1217 	if (q->vm && q->vm->xef) {
1218 		process_name = q->vm->xef->process_name;
1219 		pid = q->vm->xef->pid;
1220 	}
1221 	xe_gt_notice(guc_to_gt(guc), "Timedout job: seqno=%u, lrc_seqno=%u, guc_id=%d, flags=0x%lx in %s [%d]",
1222 		     xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job),
1223 		     q->guc->id, q->flags, process_name, pid);
1224 
1225 	trace_xe_sched_job_timedout(job);
1226 
1227 	if (!exec_queue_killed(q))
1228 		xe_devcoredump(job);
1229 
1230 	/*
1231 	 * Kernel jobs should never fail, nor should VM jobs if they do
1232 	 * somethings has gone wrong and the GT needs a reset
1233 	 */
1234 	xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_KERNEL,
1235 		   "Kernel-submitted job timed out\n");
1236 	xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q),
1237 		   "VM job timed out on non-killed execqueue\n");
1238 	if (!wedged && (q->flags & EXEC_QUEUE_FLAG_KERNEL ||
1239 			(q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q)))) {
1240 		if (!xe_sched_invalidate_job(job, 2)) {
1241 			clear_exec_queue_check_timeout(q);
1242 			xe_gt_reset_async(q->gt);
1243 			goto rearm;
1244 		}
1245 	}
1246 
1247 	/* Finish cleaning up exec queue via deregister */
1248 	set_exec_queue_banned(q);
1249 	if (!wedged && exec_queue_registered(q) && !exec_queue_destroyed(q)) {
1250 		set_exec_queue_extra_ref(q);
1251 		xe_exec_queue_get(q);
1252 		__deregister_exec_queue(guc, q);
1253 	}
1254 
1255 	/* Stop fence signaling */
1256 	xe_hw_fence_irq_stop(q->fence_irq);
1257 
1258 	/*
1259 	 * Fence state now stable, stop / start scheduler which cleans up any
1260 	 * fences that are complete
1261 	 */
1262 	xe_sched_add_pending_job(sched, job);
1263 	xe_sched_submission_start(sched);
1264 
1265 	xe_guc_exec_queue_trigger_cleanup(q);
1266 
1267 	/* Mark all outstanding jobs as bad, thus completing them */
1268 	spin_lock(&sched->base.job_list_lock);
1269 	list_for_each_entry(tmp_job, &sched->base.pending_list, drm.list)
1270 		xe_sched_job_set_error(tmp_job, !i++ ? err : -ECANCELED);
1271 	spin_unlock(&sched->base.job_list_lock);
1272 
1273 	/* Start fence signaling */
1274 	xe_hw_fence_irq_start(q->fence_irq);
1275 
1276 	return DRM_GPU_SCHED_STAT_NOMINAL;
1277 
1278 sched_enable:
1279 	enable_scheduling(q);
1280 rearm:
1281 	/*
1282 	 * XXX: Ideally want to adjust timeout based on current exection time
1283 	 * but there is not currently an easy way to do in DRM scheduler. With
1284 	 * some thought, do this in a follow up.
1285 	 */
1286 	xe_sched_add_pending_job(sched, job);
1287 	xe_sched_submission_start(sched);
1288 
1289 	return DRM_GPU_SCHED_STAT_NOMINAL;
1290 }
1291 
1292 static void __guc_exec_queue_fini_async(struct work_struct *w)
1293 {
1294 	struct xe_guc_exec_queue *ge =
1295 		container_of(w, struct xe_guc_exec_queue, fini_async);
1296 	struct xe_exec_queue *q = ge->q;
1297 	struct xe_guc *guc = exec_queue_to_guc(q);
1298 
1299 	xe_pm_runtime_get(guc_to_xe(guc));
1300 	trace_xe_exec_queue_destroy(q);
1301 
1302 	if (xe_exec_queue_is_lr(q))
1303 		cancel_work_sync(&ge->lr_tdr);
1304 	release_guc_id(guc, q);
1305 	xe_sched_entity_fini(&ge->entity);
1306 	xe_sched_fini(&ge->sched);
1307 
1308 	kfree(ge);
1309 	xe_exec_queue_fini(q);
1310 	xe_pm_runtime_put(guc_to_xe(guc));
1311 }
1312 
1313 static void guc_exec_queue_fini_async(struct xe_exec_queue *q)
1314 {
1315 	struct xe_guc *guc = exec_queue_to_guc(q);
1316 	struct xe_device *xe = guc_to_xe(guc);
1317 
1318 	INIT_WORK(&q->guc->fini_async, __guc_exec_queue_fini_async);
1319 
1320 	/* We must block on kernel engines so slabs are empty on driver unload */
1321 	if (q->flags & EXEC_QUEUE_FLAG_PERMANENT || exec_queue_wedged(q))
1322 		__guc_exec_queue_fini_async(&q->guc->fini_async);
1323 	else
1324 		queue_work(xe->destroy_wq, &q->guc->fini_async);
1325 }
1326 
1327 static void __guc_exec_queue_fini(struct xe_guc *guc, struct xe_exec_queue *q)
1328 {
1329 	/*
1330 	 * Might be done from within the GPU scheduler, need to do async as we
1331 	 * fini the scheduler when the engine is fini'd, the scheduler can't
1332 	 * complete fini within itself (circular dependency). Async resolves
1333 	 * this we and don't really care when everything is fini'd, just that it
1334 	 * is.
1335 	 */
1336 	guc_exec_queue_fini_async(q);
1337 }
1338 
1339 static void __guc_exec_queue_process_msg_cleanup(struct xe_sched_msg *msg)
1340 {
1341 	struct xe_exec_queue *q = msg->private_data;
1342 	struct xe_guc *guc = exec_queue_to_guc(q);
1343 	struct xe_device *xe = guc_to_xe(guc);
1344 
1345 	xe_assert(xe, !(q->flags & EXEC_QUEUE_FLAG_PERMANENT));
1346 	trace_xe_exec_queue_cleanup_entity(q);
1347 
1348 	if (exec_queue_registered(q))
1349 		disable_scheduling_deregister(guc, q);
1350 	else
1351 		__guc_exec_queue_fini(guc, q);
1352 }
1353 
1354 static bool guc_exec_queue_allowed_to_change_state(struct xe_exec_queue *q)
1355 {
1356 	return !exec_queue_killed_or_banned_or_wedged(q) && exec_queue_registered(q);
1357 }
1358 
1359 static void __guc_exec_queue_process_msg_set_sched_props(struct xe_sched_msg *msg)
1360 {
1361 	struct xe_exec_queue *q = msg->private_data;
1362 	struct xe_guc *guc = exec_queue_to_guc(q);
1363 
1364 	if (guc_exec_queue_allowed_to_change_state(q))
1365 		init_policies(guc, q);
1366 	kfree(msg);
1367 }
1368 
1369 static void __suspend_fence_signal(struct xe_exec_queue *q)
1370 {
1371 	if (!q->guc->suspend_pending)
1372 		return;
1373 
1374 	WRITE_ONCE(q->guc->suspend_pending, false);
1375 	wake_up(&q->guc->suspend_wait);
1376 }
1377 
1378 static void suspend_fence_signal(struct xe_exec_queue *q)
1379 {
1380 	struct xe_guc *guc = exec_queue_to_guc(q);
1381 	struct xe_device *xe = guc_to_xe(guc);
1382 
1383 	xe_assert(xe, exec_queue_suspended(q) || exec_queue_killed(q) ||
1384 		  xe_guc_read_stopped(guc));
1385 	xe_assert(xe, q->guc->suspend_pending);
1386 
1387 	__suspend_fence_signal(q);
1388 }
1389 
1390 static void __guc_exec_queue_process_msg_suspend(struct xe_sched_msg *msg)
1391 {
1392 	struct xe_exec_queue *q = msg->private_data;
1393 	struct xe_guc *guc = exec_queue_to_guc(q);
1394 
1395 	if (guc_exec_queue_allowed_to_change_state(q) && !exec_queue_suspended(q) &&
1396 	    exec_queue_enabled(q)) {
1397 		wait_event(guc->ct.wq, q->guc->resume_time != RESUME_PENDING ||
1398 			   xe_guc_read_stopped(guc));
1399 
1400 		if (!xe_guc_read_stopped(guc)) {
1401 			s64 since_resume_ms =
1402 				ktime_ms_delta(ktime_get(),
1403 					       q->guc->resume_time);
1404 			s64 wait_ms = q->vm->preempt.min_run_period_ms -
1405 				since_resume_ms;
1406 
1407 			if (wait_ms > 0 && q->guc->resume_time)
1408 				msleep(wait_ms);
1409 
1410 			set_exec_queue_suspended(q);
1411 			disable_scheduling(q, false);
1412 		}
1413 	} else if (q->guc->suspend_pending) {
1414 		set_exec_queue_suspended(q);
1415 		suspend_fence_signal(q);
1416 	}
1417 }
1418 
1419 static void __guc_exec_queue_process_msg_resume(struct xe_sched_msg *msg)
1420 {
1421 	struct xe_exec_queue *q = msg->private_data;
1422 
1423 	if (guc_exec_queue_allowed_to_change_state(q)) {
1424 		clear_exec_queue_suspended(q);
1425 		if (!exec_queue_enabled(q)) {
1426 			q->guc->resume_time = RESUME_PENDING;
1427 			enable_scheduling(q);
1428 		}
1429 	} else {
1430 		clear_exec_queue_suspended(q);
1431 	}
1432 }
1433 
1434 #define CLEANUP		1	/* Non-zero values to catch uninitialized msg */
1435 #define SET_SCHED_PROPS	2
1436 #define SUSPEND		3
1437 #define RESUME		4
1438 #define OPCODE_MASK	0xf
1439 #define MSG_LOCKED	BIT(8)
1440 
1441 static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)
1442 {
1443 	struct xe_device *xe = guc_to_xe(exec_queue_to_guc(msg->private_data));
1444 
1445 	trace_xe_sched_msg_recv(msg);
1446 
1447 	switch (msg->opcode) {
1448 	case CLEANUP:
1449 		__guc_exec_queue_process_msg_cleanup(msg);
1450 		break;
1451 	case SET_SCHED_PROPS:
1452 		__guc_exec_queue_process_msg_set_sched_props(msg);
1453 		break;
1454 	case SUSPEND:
1455 		__guc_exec_queue_process_msg_suspend(msg);
1456 		break;
1457 	case RESUME:
1458 		__guc_exec_queue_process_msg_resume(msg);
1459 		break;
1460 	default:
1461 		XE_WARN_ON("Unknown message type");
1462 	}
1463 
1464 	xe_pm_runtime_put(xe);
1465 }
1466 
1467 static const struct drm_sched_backend_ops drm_sched_ops = {
1468 	.run_job = guc_exec_queue_run_job,
1469 	.free_job = guc_exec_queue_free_job,
1470 	.timedout_job = guc_exec_queue_timedout_job,
1471 };
1472 
1473 static const struct xe_sched_backend_ops xe_sched_ops = {
1474 	.process_msg = guc_exec_queue_process_msg,
1475 };
1476 
1477 static int guc_exec_queue_init(struct xe_exec_queue *q)
1478 {
1479 	struct xe_gpu_scheduler *sched;
1480 	struct xe_guc *guc = exec_queue_to_guc(q);
1481 	struct xe_device *xe = guc_to_xe(guc);
1482 	struct xe_guc_exec_queue *ge;
1483 	long timeout;
1484 	int err, i;
1485 
1486 	xe_assert(xe, xe_device_uc_enabled(guc_to_xe(guc)));
1487 
1488 	ge = kzalloc(sizeof(*ge), GFP_KERNEL);
1489 	if (!ge)
1490 		return -ENOMEM;
1491 
1492 	q->guc = ge;
1493 	ge->q = q;
1494 	init_waitqueue_head(&ge->suspend_wait);
1495 
1496 	for (i = 0; i < MAX_STATIC_MSG_TYPE; ++i)
1497 		INIT_LIST_HEAD(&ge->static_msgs[i].link);
1498 
1499 	timeout = (q->vm && xe_vm_in_lr_mode(q->vm)) ? MAX_SCHEDULE_TIMEOUT :
1500 		  msecs_to_jiffies(q->sched_props.job_timeout_ms);
1501 	err = xe_sched_init(&ge->sched, &drm_sched_ops, &xe_sched_ops,
1502 			    get_submit_wq(guc),
1503 			    q->lrc[0]->ring.size / MAX_JOB_SIZE_BYTES, 64,
1504 			    timeout, guc_to_gt(guc)->ordered_wq, NULL,
1505 			    q->name, gt_to_xe(q->gt)->drm.dev);
1506 	if (err)
1507 		goto err_free;
1508 
1509 	sched = &ge->sched;
1510 	err = xe_sched_entity_init(&ge->entity, sched);
1511 	if (err)
1512 		goto err_sched;
1513 
1514 	if (xe_exec_queue_is_lr(q))
1515 		INIT_WORK(&q->guc->lr_tdr, xe_guc_exec_queue_lr_cleanup);
1516 
1517 	mutex_lock(&guc->submission_state.lock);
1518 
1519 	err = alloc_guc_id(guc, q);
1520 	if (err)
1521 		goto err_entity;
1522 
1523 	q->entity = &ge->entity;
1524 
1525 	if (xe_guc_read_stopped(guc))
1526 		xe_sched_stop(sched);
1527 
1528 	mutex_unlock(&guc->submission_state.lock);
1529 
1530 	xe_exec_queue_assign_name(q, q->guc->id);
1531 
1532 	trace_xe_exec_queue_create(q);
1533 
1534 	return 0;
1535 
1536 err_entity:
1537 	mutex_unlock(&guc->submission_state.lock);
1538 	xe_sched_entity_fini(&ge->entity);
1539 err_sched:
1540 	xe_sched_fini(&ge->sched);
1541 err_free:
1542 	kfree(ge);
1543 
1544 	return err;
1545 }
1546 
1547 static void guc_exec_queue_kill(struct xe_exec_queue *q)
1548 {
1549 	trace_xe_exec_queue_kill(q);
1550 	set_exec_queue_killed(q);
1551 	__suspend_fence_signal(q);
1552 	xe_guc_exec_queue_trigger_cleanup(q);
1553 }
1554 
1555 static void guc_exec_queue_add_msg(struct xe_exec_queue *q, struct xe_sched_msg *msg,
1556 				   u32 opcode)
1557 {
1558 	xe_pm_runtime_get_noresume(guc_to_xe(exec_queue_to_guc(q)));
1559 
1560 	INIT_LIST_HEAD(&msg->link);
1561 	msg->opcode = opcode & OPCODE_MASK;
1562 	msg->private_data = q;
1563 
1564 	trace_xe_sched_msg_add(msg);
1565 	if (opcode & MSG_LOCKED)
1566 		xe_sched_add_msg_locked(&q->guc->sched, msg);
1567 	else
1568 		xe_sched_add_msg(&q->guc->sched, msg);
1569 }
1570 
1571 static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q,
1572 				       struct xe_sched_msg *msg,
1573 				       u32 opcode)
1574 {
1575 	if (!list_empty(&msg->link))
1576 		return false;
1577 
1578 	guc_exec_queue_add_msg(q, msg, opcode | MSG_LOCKED);
1579 
1580 	return true;
1581 }
1582 
1583 #define STATIC_MSG_CLEANUP	0
1584 #define STATIC_MSG_SUSPEND	1
1585 #define STATIC_MSG_RESUME	2
1586 static void guc_exec_queue_fini(struct xe_exec_queue *q)
1587 {
1588 	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP;
1589 
1590 	if (!(q->flags & EXEC_QUEUE_FLAG_PERMANENT) && !exec_queue_wedged(q))
1591 		guc_exec_queue_add_msg(q, msg, CLEANUP);
1592 	else
1593 		__guc_exec_queue_fini(exec_queue_to_guc(q), q);
1594 }
1595 
1596 static int guc_exec_queue_set_priority(struct xe_exec_queue *q,
1597 				       enum xe_exec_queue_priority priority)
1598 {
1599 	struct xe_sched_msg *msg;
1600 
1601 	if (q->sched_props.priority == priority ||
1602 	    exec_queue_killed_or_banned_or_wedged(q))
1603 		return 0;
1604 
1605 	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
1606 	if (!msg)
1607 		return -ENOMEM;
1608 
1609 	q->sched_props.priority = priority;
1610 	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);
1611 
1612 	return 0;
1613 }
1614 
1615 static int guc_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us)
1616 {
1617 	struct xe_sched_msg *msg;
1618 
1619 	if (q->sched_props.timeslice_us == timeslice_us ||
1620 	    exec_queue_killed_or_banned_or_wedged(q))
1621 		return 0;
1622 
1623 	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
1624 	if (!msg)
1625 		return -ENOMEM;
1626 
1627 	q->sched_props.timeslice_us = timeslice_us;
1628 	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);
1629 
1630 	return 0;
1631 }
1632 
1633 static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q,
1634 					      u32 preempt_timeout_us)
1635 {
1636 	struct xe_sched_msg *msg;
1637 
1638 	if (q->sched_props.preempt_timeout_us == preempt_timeout_us ||
1639 	    exec_queue_killed_or_banned_or_wedged(q))
1640 		return 0;
1641 
1642 	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
1643 	if (!msg)
1644 		return -ENOMEM;
1645 
1646 	q->sched_props.preempt_timeout_us = preempt_timeout_us;
1647 	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);
1648 
1649 	return 0;
1650 }
1651 
1652 static int guc_exec_queue_suspend(struct xe_exec_queue *q)
1653 {
1654 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1655 	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_SUSPEND;
1656 
1657 	if (exec_queue_killed_or_banned_or_wedged(q))
1658 		return -EINVAL;
1659 
1660 	xe_sched_msg_lock(sched);
1661 	if (guc_exec_queue_try_add_msg(q, msg, SUSPEND))
1662 		q->guc->suspend_pending = true;
1663 	xe_sched_msg_unlock(sched);
1664 
1665 	return 0;
1666 }
1667 
1668 static int guc_exec_queue_suspend_wait(struct xe_exec_queue *q)
1669 {
1670 	struct xe_guc *guc = exec_queue_to_guc(q);
1671 	int ret;
1672 
1673 	/*
1674 	 * Likely don't need to check exec_queue_killed() as we clear
1675 	 * suspend_pending upon kill but to be paranoid but races in which
1676 	 * suspend_pending is set after kill also check kill here.
1677 	 */
1678 	ret = wait_event_interruptible_timeout(q->guc->suspend_wait,
1679 					       !READ_ONCE(q->guc->suspend_pending) ||
1680 					       exec_queue_killed(q) ||
1681 					       xe_guc_read_stopped(guc),
1682 					       HZ * 5);
1683 
1684 	if (!ret) {
1685 		xe_gt_warn(guc_to_gt(guc),
1686 			   "Suspend fence, guc_id=%d, failed to respond",
1687 			   q->guc->id);
1688 		/* XXX: Trigger GT reset? */
1689 		return -ETIME;
1690 	}
1691 
1692 	return ret < 0 ? ret : 0;
1693 }
1694 
1695 static void guc_exec_queue_resume(struct xe_exec_queue *q)
1696 {
1697 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1698 	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_RESUME;
1699 	struct xe_guc *guc = exec_queue_to_guc(q);
1700 	struct xe_device *xe = guc_to_xe(guc);
1701 
1702 	xe_assert(xe, !q->guc->suspend_pending);
1703 
1704 	xe_sched_msg_lock(sched);
1705 	guc_exec_queue_try_add_msg(q, msg, RESUME);
1706 	xe_sched_msg_unlock(sched);
1707 }
1708 
1709 static bool guc_exec_queue_reset_status(struct xe_exec_queue *q)
1710 {
1711 	return exec_queue_reset(q) || exec_queue_killed_or_banned_or_wedged(q);
1712 }
1713 
1714 /*
1715  * All of these functions are an abstraction layer which other parts of XE can
1716  * use to trap into the GuC backend. All of these functions, aside from init,
1717  * really shouldn't do much other than trap into the DRM scheduler which
1718  * synchronizes these operations.
1719  */
1720 static const struct xe_exec_queue_ops guc_exec_queue_ops = {
1721 	.init = guc_exec_queue_init,
1722 	.kill = guc_exec_queue_kill,
1723 	.fini = guc_exec_queue_fini,
1724 	.set_priority = guc_exec_queue_set_priority,
1725 	.set_timeslice = guc_exec_queue_set_timeslice,
1726 	.set_preempt_timeout = guc_exec_queue_set_preempt_timeout,
1727 	.suspend = guc_exec_queue_suspend,
1728 	.suspend_wait = guc_exec_queue_suspend_wait,
1729 	.resume = guc_exec_queue_resume,
1730 	.reset_status = guc_exec_queue_reset_status,
1731 };
1732 
1733 static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q)
1734 {
1735 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1736 
1737 	/* Stop scheduling + flush any DRM scheduler operations */
1738 	xe_sched_submission_stop(sched);
1739 
1740 	/* Clean up lost G2H + reset engine state */
1741 	if (exec_queue_registered(q)) {
1742 		if (exec_queue_extra_ref(q) || xe_exec_queue_is_lr(q))
1743 			xe_exec_queue_put(q);
1744 		else if (exec_queue_destroyed(q))
1745 			__guc_exec_queue_fini(guc, q);
1746 	}
1747 	if (q->guc->suspend_pending) {
1748 		set_exec_queue_suspended(q);
1749 		suspend_fence_signal(q);
1750 	}
1751 	atomic_and(EXEC_QUEUE_STATE_WEDGED | EXEC_QUEUE_STATE_BANNED |
1752 		   EXEC_QUEUE_STATE_KILLED | EXEC_QUEUE_STATE_DESTROYED |
1753 		   EXEC_QUEUE_STATE_SUSPENDED,
1754 		   &q->guc->state);
1755 	q->guc->resume_time = 0;
1756 	trace_xe_exec_queue_stop(q);
1757 
1758 	/*
1759 	 * Ban any engine (aside from kernel and engines used for VM ops) with a
1760 	 * started but not complete job or if a job has gone through a GT reset
1761 	 * more than twice.
1762 	 */
1763 	if (!(q->flags & (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM))) {
1764 		struct xe_sched_job *job = xe_sched_first_pending_job(sched);
1765 		bool ban = false;
1766 
1767 		if (job) {
1768 			if ((xe_sched_job_started(job) &&
1769 			    !xe_sched_job_completed(job)) ||
1770 			    xe_sched_invalidate_job(job, 2)) {
1771 				trace_xe_sched_job_ban(job);
1772 				ban = true;
1773 			}
1774 		} else if (xe_exec_queue_is_lr(q) &&
1775 			   (xe_lrc_ring_head(q->lrc[0]) != xe_lrc_ring_tail(q->lrc[0]))) {
1776 			ban = true;
1777 		}
1778 
1779 		if (ban) {
1780 			set_exec_queue_banned(q);
1781 			xe_guc_exec_queue_trigger_cleanup(q);
1782 		}
1783 	}
1784 }
1785 
1786 int xe_guc_submit_reset_prepare(struct xe_guc *guc)
1787 {
1788 	int ret;
1789 
1790 	/*
1791 	 * Using an atomic here rather than submission_state.lock as this
1792 	 * function can be called while holding the CT lock (engine reset
1793 	 * failure). submission_state.lock needs the CT lock to resubmit jobs.
1794 	 * Atomic is not ideal, but it works to prevent against concurrent reset
1795 	 * and releasing any TDRs waiting on guc->submission_state.stopped.
1796 	 */
1797 	ret = atomic_fetch_or(1, &guc->submission_state.stopped);
1798 	smp_wmb();
1799 	wake_up_all(&guc->ct.wq);
1800 
1801 	return ret;
1802 }
1803 
1804 void xe_guc_submit_reset_wait(struct xe_guc *guc)
1805 {
1806 	wait_event(guc->ct.wq, xe_device_wedged(guc_to_xe(guc)) ||
1807 		   !xe_guc_read_stopped(guc));
1808 }
1809 
1810 void xe_guc_submit_stop(struct xe_guc *guc)
1811 {
1812 	struct xe_exec_queue *q;
1813 	unsigned long index;
1814 	struct xe_device *xe = guc_to_xe(guc);
1815 
1816 	xe_assert(xe, xe_guc_read_stopped(guc) == 1);
1817 
1818 	mutex_lock(&guc->submission_state.lock);
1819 
1820 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
1821 		guc_exec_queue_stop(guc, q);
1822 
1823 	mutex_unlock(&guc->submission_state.lock);
1824 
1825 	/*
1826 	 * No one can enter the backend at this point, aside from new engine
1827 	 * creation which is protected by guc->submission_state.lock.
1828 	 */
1829 
1830 }
1831 
1832 static void guc_exec_queue_start(struct xe_exec_queue *q)
1833 {
1834 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1835 
1836 	if (!exec_queue_killed_or_banned_or_wedged(q)) {
1837 		int i;
1838 
1839 		trace_xe_exec_queue_resubmit(q);
1840 		for (i = 0; i < q->width; ++i)
1841 			xe_lrc_set_ring_head(q->lrc[i], q->lrc[i]->ring.tail);
1842 		xe_sched_resubmit_jobs(sched);
1843 	}
1844 
1845 	xe_sched_submission_start(sched);
1846 	xe_sched_submission_resume_tdr(sched);
1847 }
1848 
1849 int xe_guc_submit_start(struct xe_guc *guc)
1850 {
1851 	struct xe_exec_queue *q;
1852 	unsigned long index;
1853 	struct xe_device *xe = guc_to_xe(guc);
1854 
1855 	xe_assert(xe, xe_guc_read_stopped(guc) == 1);
1856 
1857 	mutex_lock(&guc->submission_state.lock);
1858 	atomic_dec(&guc->submission_state.stopped);
1859 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
1860 		guc_exec_queue_start(q);
1861 	mutex_unlock(&guc->submission_state.lock);
1862 
1863 	wake_up_all(&guc->ct.wq);
1864 
1865 	return 0;
1866 }
1867 
1868 static struct xe_exec_queue *
1869 g2h_exec_queue_lookup(struct xe_guc *guc, u32 guc_id)
1870 {
1871 	struct xe_device *xe = guc_to_xe(guc);
1872 	struct xe_exec_queue *q;
1873 
1874 	if (unlikely(guc_id >= GUC_ID_MAX)) {
1875 		drm_err(&xe->drm, "Invalid guc_id %u", guc_id);
1876 		return NULL;
1877 	}
1878 
1879 	q = xa_load(&guc->submission_state.exec_queue_lookup, guc_id);
1880 	if (unlikely(!q)) {
1881 		drm_err(&xe->drm, "Not engine present for guc_id %u", guc_id);
1882 		return NULL;
1883 	}
1884 
1885 	xe_assert(xe, guc_id >= q->guc->id);
1886 	xe_assert(xe, guc_id < (q->guc->id + q->width));
1887 
1888 	return q;
1889 }
1890 
1891 static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
1892 {
1893 	u32 action[] = {
1894 		XE_GUC_ACTION_DEREGISTER_CONTEXT,
1895 		q->guc->id,
1896 	};
1897 
1898 	xe_gt_assert(guc_to_gt(guc), exec_queue_destroyed(q));
1899 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
1900 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
1901 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q));
1902 
1903 	trace_xe_exec_queue_deregister(q);
1904 
1905 	xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action));
1906 }
1907 
1908 static void handle_sched_done(struct xe_guc *guc, struct xe_exec_queue *q,
1909 			      u32 runnable_state)
1910 {
1911 	trace_xe_exec_queue_scheduling_done(q);
1912 
1913 	if (runnable_state == 1) {
1914 		xe_gt_assert(guc_to_gt(guc), exec_queue_pending_enable(q));
1915 
1916 		q->guc->resume_time = ktime_get();
1917 		clear_exec_queue_pending_enable(q);
1918 		smp_wmb();
1919 		wake_up_all(&guc->ct.wq);
1920 	} else {
1921 		bool check_timeout = exec_queue_check_timeout(q);
1922 
1923 		xe_gt_assert(guc_to_gt(guc), runnable_state == 0);
1924 		xe_gt_assert(guc_to_gt(guc), exec_queue_pending_disable(q));
1925 
1926 		clear_exec_queue_pending_disable(q);
1927 		if (q->guc->suspend_pending) {
1928 			suspend_fence_signal(q);
1929 		} else {
1930 			if (exec_queue_banned(q) || check_timeout) {
1931 				smp_wmb();
1932 				wake_up_all(&guc->ct.wq);
1933 			}
1934 			if (!check_timeout)
1935 				deregister_exec_queue(guc, q);
1936 		}
1937 	}
1938 }
1939 
1940 int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
1941 {
1942 	struct xe_device *xe = guc_to_xe(guc);
1943 	struct xe_exec_queue *q;
1944 	u32 guc_id = msg[0];
1945 	u32 runnable_state = msg[1];
1946 
1947 	if (unlikely(len < 2)) {
1948 		drm_err(&xe->drm, "Invalid length %u", len);
1949 		return -EPROTO;
1950 	}
1951 
1952 	q = g2h_exec_queue_lookup(guc, guc_id);
1953 	if (unlikely(!q))
1954 		return -EPROTO;
1955 
1956 	if (unlikely(!exec_queue_pending_enable(q) &&
1957 		     !exec_queue_pending_disable(q))) {
1958 		xe_gt_err(guc_to_gt(guc),
1959 			  "SCHED_DONE: Unexpected engine state 0x%04x, guc_id=%d, runnable_state=%u",
1960 			  atomic_read(&q->guc->state), q->guc->id,
1961 			  runnable_state);
1962 		return -EPROTO;
1963 	}
1964 
1965 	handle_sched_done(guc, q, runnable_state);
1966 
1967 	return 0;
1968 }
1969 
1970 static void handle_deregister_done(struct xe_guc *guc, struct xe_exec_queue *q)
1971 {
1972 	trace_xe_exec_queue_deregister_done(q);
1973 
1974 	clear_exec_queue_registered(q);
1975 
1976 	if (exec_queue_extra_ref(q) || xe_exec_queue_is_lr(q))
1977 		xe_exec_queue_put(q);
1978 	else
1979 		__guc_exec_queue_fini(guc, q);
1980 }
1981 
1982 int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
1983 {
1984 	struct xe_device *xe = guc_to_xe(guc);
1985 	struct xe_exec_queue *q;
1986 	u32 guc_id = msg[0];
1987 
1988 	if (unlikely(len < 1)) {
1989 		drm_err(&xe->drm, "Invalid length %u", len);
1990 		return -EPROTO;
1991 	}
1992 
1993 	q = g2h_exec_queue_lookup(guc, guc_id);
1994 	if (unlikely(!q))
1995 		return -EPROTO;
1996 
1997 	if (!exec_queue_destroyed(q) || exec_queue_pending_disable(q) ||
1998 	    exec_queue_pending_enable(q) || exec_queue_enabled(q)) {
1999 		xe_gt_err(guc_to_gt(guc),
2000 			  "DEREGISTER_DONE: Unexpected engine state 0x%04x, guc_id=%d",
2001 			  atomic_read(&q->guc->state), q->guc->id);
2002 		return -EPROTO;
2003 	}
2004 
2005 	handle_deregister_done(guc, q);
2006 
2007 	return 0;
2008 }
2009 
2010 int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len)
2011 {
2012 	struct xe_gt *gt = guc_to_gt(guc);
2013 	struct xe_device *xe = guc_to_xe(guc);
2014 	struct xe_exec_queue *q;
2015 	u32 guc_id = msg[0];
2016 
2017 	if (unlikely(len < 1)) {
2018 		drm_err(&xe->drm, "Invalid length %u", len);
2019 		return -EPROTO;
2020 	}
2021 
2022 	q = g2h_exec_queue_lookup(guc, guc_id);
2023 	if (unlikely(!q))
2024 		return -EPROTO;
2025 
2026 	xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: 0x%x, guc_id=%d",
2027 		   xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id);
2028 
2029 	trace_xe_exec_queue_reset(q);
2030 
2031 	/*
2032 	 * A banned engine is a NOP at this point (came from
2033 	 * guc_exec_queue_timedout_job). Otherwise, kick drm scheduler to cancel
2034 	 * jobs by setting timeout of the job to the minimum value kicking
2035 	 * guc_exec_queue_timedout_job.
2036 	 */
2037 	set_exec_queue_reset(q);
2038 	if (!exec_queue_banned(q) && !exec_queue_check_timeout(q))
2039 		xe_guc_exec_queue_trigger_cleanup(q);
2040 
2041 	return 0;
2042 }
2043 
2044 /*
2045  * xe_guc_error_capture_handler - Handler of GuC captured message
2046  * @guc: The GuC object
2047  * @msg: Point to the message
2048  * @len: The message length
2049  *
2050  * When GuC captured data is ready, GuC will send message
2051  * XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION to host, this function will be
2052  * called 1st to check status before process the data comes with the message.
2053  *
2054  * Returns: error code. 0 if success
2055  */
2056 int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 len)
2057 {
2058 	u32 status;
2059 
2060 	if (unlikely(len != XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION_DATA_LEN)) {
2061 		xe_gt_dbg(guc_to_gt(guc), "Invalid length %u", len);
2062 		return -EPROTO;
2063 	}
2064 
2065 	status = msg[0] & XE_GUC_STATE_CAPTURE_EVENT_STATUS_MASK;
2066 	if (status == XE_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE)
2067 		xe_gt_warn(guc_to_gt(guc), "G2H-Error capture no space");
2068 
2069 	xe_guc_capture_process(guc);
2070 
2071 	return 0;
2072 }
2073 
2074 int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg,
2075 					       u32 len)
2076 {
2077 	struct xe_gt *gt = guc_to_gt(guc);
2078 	struct xe_device *xe = guc_to_xe(guc);
2079 	struct xe_exec_queue *q;
2080 	u32 guc_id = msg[0];
2081 
2082 	if (unlikely(len < 1)) {
2083 		drm_err(&xe->drm, "Invalid length %u", len);
2084 		return -EPROTO;
2085 	}
2086 
2087 	q = g2h_exec_queue_lookup(guc, guc_id);
2088 	if (unlikely(!q))
2089 		return -EPROTO;
2090 
2091 	xe_gt_dbg(gt, "Engine memory cat error: engine_class=%s, logical_mask: 0x%x, guc_id=%d",
2092 		  xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id);
2093 
2094 	trace_xe_exec_queue_memory_cat_error(q);
2095 
2096 	/* Treat the same as engine reset */
2097 	set_exec_queue_reset(q);
2098 	if (!exec_queue_banned(q) && !exec_queue_check_timeout(q))
2099 		xe_guc_exec_queue_trigger_cleanup(q);
2100 
2101 	return 0;
2102 }
2103 
2104 int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len)
2105 {
2106 	struct xe_device *xe = guc_to_xe(guc);
2107 	u8 guc_class, instance;
2108 	u32 reason;
2109 
2110 	if (unlikely(len != 3)) {
2111 		drm_err(&xe->drm, "Invalid length %u", len);
2112 		return -EPROTO;
2113 	}
2114 
2115 	guc_class = msg[0];
2116 	instance = msg[1];
2117 	reason = msg[2];
2118 
2119 	/* Unexpected failure of a hardware feature, log an actual error */
2120 	drm_err(&xe->drm, "GuC engine reset request failed on %d:%d because 0x%08X",
2121 		guc_class, instance, reason);
2122 
2123 	xe_gt_reset_async(guc_to_gt(guc));
2124 
2125 	return 0;
2126 }
2127 
2128 static void
2129 guc_exec_queue_wq_snapshot_capture(struct xe_exec_queue *q,
2130 				   struct xe_guc_submit_exec_queue_snapshot *snapshot)
2131 {
2132 	struct xe_guc *guc = exec_queue_to_guc(q);
2133 	struct xe_device *xe = guc_to_xe(guc);
2134 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
2135 	int i;
2136 
2137 	snapshot->guc.wqi_head = q->guc->wqi_head;
2138 	snapshot->guc.wqi_tail = q->guc->wqi_tail;
2139 	snapshot->parallel.wq_desc.head = parallel_read(xe, map, wq_desc.head);
2140 	snapshot->parallel.wq_desc.tail = parallel_read(xe, map, wq_desc.tail);
2141 	snapshot->parallel.wq_desc.status = parallel_read(xe, map,
2142 							  wq_desc.wq_status);
2143 
2144 	if (snapshot->parallel.wq_desc.head !=
2145 	    snapshot->parallel.wq_desc.tail) {
2146 		for (i = snapshot->parallel.wq_desc.head;
2147 		     i != snapshot->parallel.wq_desc.tail;
2148 		     i = (i + sizeof(u32)) % WQ_SIZE)
2149 			snapshot->parallel.wq[i / sizeof(u32)] =
2150 				parallel_read(xe, map, wq[i / sizeof(u32)]);
2151 	}
2152 }
2153 
2154 static void
2155 guc_exec_queue_wq_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot,
2156 				 struct drm_printer *p)
2157 {
2158 	int i;
2159 
2160 	drm_printf(p, "\tWQ head: %u (internal), %d (memory)\n",
2161 		   snapshot->guc.wqi_head, snapshot->parallel.wq_desc.head);
2162 	drm_printf(p, "\tWQ tail: %u (internal), %d (memory)\n",
2163 		   snapshot->guc.wqi_tail, snapshot->parallel.wq_desc.tail);
2164 	drm_printf(p, "\tWQ status: %u\n", snapshot->parallel.wq_desc.status);
2165 
2166 	if (snapshot->parallel.wq_desc.head !=
2167 	    snapshot->parallel.wq_desc.tail) {
2168 		for (i = snapshot->parallel.wq_desc.head;
2169 		     i != snapshot->parallel.wq_desc.tail;
2170 		     i = (i + sizeof(u32)) % WQ_SIZE)
2171 			drm_printf(p, "\tWQ[%zu]: 0x%08x\n", i / sizeof(u32),
2172 				   snapshot->parallel.wq[i / sizeof(u32)]);
2173 	}
2174 }
2175 
2176 /**
2177  * xe_guc_exec_queue_snapshot_capture - Take a quick snapshot of the GuC Engine.
2178  * @q: faulty exec queue
2179  *
2180  * This can be printed out in a later stage like during dev_coredump
2181  * analysis.
2182  *
2183  * Returns: a GuC Submit Engine snapshot object that must be freed by the
2184  * caller, using `xe_guc_exec_queue_snapshot_free`.
2185  */
2186 struct xe_guc_submit_exec_queue_snapshot *
2187 xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q)
2188 {
2189 	struct xe_gpu_scheduler *sched = &q->guc->sched;
2190 	struct xe_guc_submit_exec_queue_snapshot *snapshot;
2191 	int i;
2192 
2193 	snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC);
2194 
2195 	if (!snapshot)
2196 		return NULL;
2197 
2198 	snapshot->guc.id = q->guc->id;
2199 	memcpy(&snapshot->name, &q->name, sizeof(snapshot->name));
2200 	snapshot->class = q->class;
2201 	snapshot->logical_mask = q->logical_mask;
2202 	snapshot->width = q->width;
2203 	snapshot->refcount = kref_read(&q->refcount);
2204 	snapshot->sched_timeout = sched->base.timeout;
2205 	snapshot->sched_props.timeslice_us = q->sched_props.timeslice_us;
2206 	snapshot->sched_props.preempt_timeout_us =
2207 		q->sched_props.preempt_timeout_us;
2208 
2209 	snapshot->lrc = kmalloc_array(q->width, sizeof(struct xe_lrc_snapshot *),
2210 				      GFP_ATOMIC);
2211 
2212 	if (snapshot->lrc) {
2213 		for (i = 0; i < q->width; ++i) {
2214 			struct xe_lrc *lrc = q->lrc[i];
2215 
2216 			snapshot->lrc[i] = xe_lrc_snapshot_capture(lrc);
2217 		}
2218 	}
2219 
2220 	snapshot->schedule_state = atomic_read(&q->guc->state);
2221 	snapshot->exec_queue_flags = q->flags;
2222 
2223 	snapshot->parallel_execution = xe_exec_queue_is_parallel(q);
2224 	if (snapshot->parallel_execution)
2225 		guc_exec_queue_wq_snapshot_capture(q, snapshot);
2226 
2227 	spin_lock(&sched->base.job_list_lock);
2228 	snapshot->pending_list_size = list_count_nodes(&sched->base.pending_list);
2229 	snapshot->pending_list = kmalloc_array(snapshot->pending_list_size,
2230 					       sizeof(struct pending_list_snapshot),
2231 					       GFP_ATOMIC);
2232 
2233 	if (snapshot->pending_list) {
2234 		struct xe_sched_job *job_iter;
2235 
2236 		i = 0;
2237 		list_for_each_entry(job_iter, &sched->base.pending_list, drm.list) {
2238 			snapshot->pending_list[i].seqno =
2239 				xe_sched_job_seqno(job_iter);
2240 			snapshot->pending_list[i].fence =
2241 				dma_fence_is_signaled(job_iter->fence) ? 1 : 0;
2242 			snapshot->pending_list[i].finished =
2243 				dma_fence_is_signaled(&job_iter->drm.s_fence->finished)
2244 				? 1 : 0;
2245 			i++;
2246 		}
2247 	}
2248 
2249 	spin_unlock(&sched->base.job_list_lock);
2250 
2251 	return snapshot;
2252 }
2253 
2254 /**
2255  * xe_guc_exec_queue_snapshot_capture_delayed - Take delayed part of snapshot of the GuC Engine.
2256  * @snapshot: Previously captured snapshot of job.
2257  *
2258  * This captures some data that requires taking some locks, so it cannot be done in signaling path.
2259  */
2260 void
2261 xe_guc_exec_queue_snapshot_capture_delayed(struct xe_guc_submit_exec_queue_snapshot *snapshot)
2262 {
2263 	int i;
2264 
2265 	if (!snapshot || !snapshot->lrc)
2266 		return;
2267 
2268 	for (i = 0; i < snapshot->width; ++i)
2269 		xe_lrc_snapshot_capture_delayed(snapshot->lrc[i]);
2270 }
2271 
2272 /**
2273  * xe_guc_exec_queue_snapshot_print - Print out a given GuC Engine snapshot.
2274  * @snapshot: GuC Submit Engine snapshot object.
2275  * @p: drm_printer where it will be printed out.
2276  *
2277  * This function prints out a given GuC Submit Engine snapshot object.
2278  */
2279 void
2280 xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot,
2281 				 struct drm_printer *p)
2282 {
2283 	int i;
2284 
2285 	if (!snapshot)
2286 		return;
2287 
2288 	drm_printf(p, "GuC ID: %d\n", snapshot->guc.id);
2289 	drm_printf(p, "\tName: %s\n", snapshot->name);
2290 	drm_printf(p, "\tClass: %d\n", snapshot->class);
2291 	drm_printf(p, "\tLogical mask: 0x%x\n", snapshot->logical_mask);
2292 	drm_printf(p, "\tWidth: %d\n", snapshot->width);
2293 	drm_printf(p, "\tRef: %d\n", snapshot->refcount);
2294 	drm_printf(p, "\tTimeout: %ld (ms)\n", snapshot->sched_timeout);
2295 	drm_printf(p, "\tTimeslice: %u (us)\n",
2296 		   snapshot->sched_props.timeslice_us);
2297 	drm_printf(p, "\tPreempt timeout: %u (us)\n",
2298 		   snapshot->sched_props.preempt_timeout_us);
2299 
2300 	for (i = 0; snapshot->lrc && i < snapshot->width; ++i)
2301 		xe_lrc_snapshot_print(snapshot->lrc[i], p);
2302 
2303 	drm_printf(p, "\tSchedule State: 0x%x\n", snapshot->schedule_state);
2304 	drm_printf(p, "\tFlags: 0x%lx\n", snapshot->exec_queue_flags);
2305 
2306 	if (snapshot->parallel_execution)
2307 		guc_exec_queue_wq_snapshot_print(snapshot, p);
2308 
2309 	for (i = 0; snapshot->pending_list && i < snapshot->pending_list_size;
2310 	     i++)
2311 		drm_printf(p, "\tJob: seqno=%d, fence=%d, finished=%d\n",
2312 			   snapshot->pending_list[i].seqno,
2313 			   snapshot->pending_list[i].fence,
2314 			   snapshot->pending_list[i].finished);
2315 }
2316 
2317 /**
2318  * xe_guc_exec_queue_snapshot_free - Free all allocated objects for a given
2319  * snapshot.
2320  * @snapshot: GuC Submit Engine snapshot object.
2321  *
2322  * This function free all the memory that needed to be allocated at capture
2323  * time.
2324  */
2325 void xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot)
2326 {
2327 	int i;
2328 
2329 	if (!snapshot)
2330 		return;
2331 
2332 	if (snapshot->lrc) {
2333 		for (i = 0; i < snapshot->width; i++)
2334 			xe_lrc_snapshot_free(snapshot->lrc[i]);
2335 		kfree(snapshot->lrc);
2336 	}
2337 	kfree(snapshot->pending_list);
2338 	kfree(snapshot);
2339 }
2340 
2341 static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p)
2342 {
2343 	struct xe_guc_submit_exec_queue_snapshot *snapshot;
2344 
2345 	snapshot = xe_guc_exec_queue_snapshot_capture(q);
2346 	xe_guc_exec_queue_snapshot_print(snapshot, p);
2347 	xe_guc_exec_queue_snapshot_free(snapshot);
2348 }
2349 
2350 /**
2351  * xe_guc_submit_print - GuC Submit Print.
2352  * @guc: GuC.
2353  * @p: drm_printer where it will be printed out.
2354  *
2355  * This function capture and prints snapshots of **all** GuC Engines.
2356  */
2357 void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p)
2358 {
2359 	struct xe_exec_queue *q;
2360 	unsigned long index;
2361 
2362 	if (!xe_device_uc_enabled(guc_to_xe(guc)))
2363 		return;
2364 
2365 	mutex_lock(&guc->submission_state.lock);
2366 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
2367 		guc_exec_queue_print(q, p);
2368 	mutex_unlock(&guc->submission_state.lock);
2369 }
2370