1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc_submit.h" 7 8 #include <linux/bitfield.h> 9 #include <linux/bitmap.h> 10 #include <linux/circ_buf.h> 11 #include <linux/delay.h> 12 #include <linux/dma-fence-array.h> 13 #include <linux/math64.h> 14 15 #include <drm/drm_managed.h> 16 17 #include "abi/guc_actions_abi.h" 18 #include "abi/guc_actions_slpc_abi.h" 19 #include "abi/guc_klvs_abi.h" 20 #include "regs/xe_lrc_layout.h" 21 #include "xe_assert.h" 22 #include "xe_devcoredump.h" 23 #include "xe_device.h" 24 #include "xe_exec_queue.h" 25 #include "xe_force_wake.h" 26 #include "xe_gpu_scheduler.h" 27 #include "xe_gt.h" 28 #include "xe_gt_clock.h" 29 #include "xe_gt_printk.h" 30 #include "xe_guc.h" 31 #include "xe_guc_capture.h" 32 #include "xe_guc_ct.h" 33 #include "xe_guc_exec_queue_types.h" 34 #include "xe_guc_id_mgr.h" 35 #include "xe_guc_submit_types.h" 36 #include "xe_hw_engine.h" 37 #include "xe_hw_fence.h" 38 #include "xe_lrc.h" 39 #include "xe_macros.h" 40 #include "xe_map.h" 41 #include "xe_mocs.h" 42 #include "xe_pm.h" 43 #include "xe_ring_ops_types.h" 44 #include "xe_sched_job.h" 45 #include "xe_trace.h" 46 #include "xe_vm.h" 47 48 static struct xe_guc * 49 exec_queue_to_guc(struct xe_exec_queue *q) 50 { 51 return &q->gt->uc.guc; 52 } 53 54 /* 55 * Helpers for engine state, using an atomic as some of the bits can transition 56 * as the same time (e.g. a suspend can be happning at the same time as schedule 57 * engine done being processed). 58 */ 59 #define EXEC_QUEUE_STATE_REGISTERED (1 << 0) 60 #define EXEC_QUEUE_STATE_ENABLED (1 << 1) 61 #define EXEC_QUEUE_STATE_PENDING_ENABLE (1 << 2) 62 #define EXEC_QUEUE_STATE_PENDING_DISABLE (1 << 3) 63 #define EXEC_QUEUE_STATE_DESTROYED (1 << 4) 64 #define EXEC_QUEUE_STATE_SUSPENDED (1 << 5) 65 #define EXEC_QUEUE_STATE_RESET (1 << 6) 66 #define EXEC_QUEUE_STATE_KILLED (1 << 7) 67 #define EXEC_QUEUE_STATE_WEDGED (1 << 8) 68 #define EXEC_QUEUE_STATE_BANNED (1 << 9) 69 #define EXEC_QUEUE_STATE_CHECK_TIMEOUT (1 << 10) 70 #define EXEC_QUEUE_STATE_EXTRA_REF (1 << 11) 71 72 static bool exec_queue_registered(struct xe_exec_queue *q) 73 { 74 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_REGISTERED; 75 } 76 77 static void set_exec_queue_registered(struct xe_exec_queue *q) 78 { 79 atomic_or(EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); 80 } 81 82 static void clear_exec_queue_registered(struct xe_exec_queue *q) 83 { 84 atomic_and(~EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); 85 } 86 87 static bool exec_queue_enabled(struct xe_exec_queue *q) 88 { 89 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_ENABLED; 90 } 91 92 static void set_exec_queue_enabled(struct xe_exec_queue *q) 93 { 94 atomic_or(EXEC_QUEUE_STATE_ENABLED, &q->guc->state); 95 } 96 97 static void clear_exec_queue_enabled(struct xe_exec_queue *q) 98 { 99 atomic_and(~EXEC_QUEUE_STATE_ENABLED, &q->guc->state); 100 } 101 102 static bool exec_queue_pending_enable(struct xe_exec_queue *q) 103 { 104 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_ENABLE; 105 } 106 107 static void set_exec_queue_pending_enable(struct xe_exec_queue *q) 108 { 109 atomic_or(EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state); 110 } 111 112 static void clear_exec_queue_pending_enable(struct xe_exec_queue *q) 113 { 114 atomic_and(~EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state); 115 } 116 117 static bool exec_queue_pending_disable(struct xe_exec_queue *q) 118 { 119 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_DISABLE; 120 } 121 122 static void set_exec_queue_pending_disable(struct xe_exec_queue *q) 123 { 124 atomic_or(EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state); 125 } 126 127 static void clear_exec_queue_pending_disable(struct xe_exec_queue *q) 128 { 129 atomic_and(~EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state); 130 } 131 132 static bool exec_queue_destroyed(struct xe_exec_queue *q) 133 { 134 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_DESTROYED; 135 } 136 137 static void set_exec_queue_destroyed(struct xe_exec_queue *q) 138 { 139 atomic_or(EXEC_QUEUE_STATE_DESTROYED, &q->guc->state); 140 } 141 142 static bool exec_queue_banned(struct xe_exec_queue *q) 143 { 144 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_BANNED; 145 } 146 147 static void set_exec_queue_banned(struct xe_exec_queue *q) 148 { 149 atomic_or(EXEC_QUEUE_STATE_BANNED, &q->guc->state); 150 } 151 152 static bool exec_queue_suspended(struct xe_exec_queue *q) 153 { 154 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_SUSPENDED; 155 } 156 157 static void set_exec_queue_suspended(struct xe_exec_queue *q) 158 { 159 atomic_or(EXEC_QUEUE_STATE_SUSPENDED, &q->guc->state); 160 } 161 162 static void clear_exec_queue_suspended(struct xe_exec_queue *q) 163 { 164 atomic_and(~EXEC_QUEUE_STATE_SUSPENDED, &q->guc->state); 165 } 166 167 static bool exec_queue_reset(struct xe_exec_queue *q) 168 { 169 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_RESET; 170 } 171 172 static void set_exec_queue_reset(struct xe_exec_queue *q) 173 { 174 atomic_or(EXEC_QUEUE_STATE_RESET, &q->guc->state); 175 } 176 177 static bool exec_queue_killed(struct xe_exec_queue *q) 178 { 179 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_KILLED; 180 } 181 182 static void set_exec_queue_killed(struct xe_exec_queue *q) 183 { 184 atomic_or(EXEC_QUEUE_STATE_KILLED, &q->guc->state); 185 } 186 187 static bool exec_queue_wedged(struct xe_exec_queue *q) 188 { 189 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_WEDGED; 190 } 191 192 static void set_exec_queue_wedged(struct xe_exec_queue *q) 193 { 194 atomic_or(EXEC_QUEUE_STATE_WEDGED, &q->guc->state); 195 } 196 197 static bool exec_queue_check_timeout(struct xe_exec_queue *q) 198 { 199 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_CHECK_TIMEOUT; 200 } 201 202 static void set_exec_queue_check_timeout(struct xe_exec_queue *q) 203 { 204 atomic_or(EXEC_QUEUE_STATE_CHECK_TIMEOUT, &q->guc->state); 205 } 206 207 static void clear_exec_queue_check_timeout(struct xe_exec_queue *q) 208 { 209 atomic_and(~EXEC_QUEUE_STATE_CHECK_TIMEOUT, &q->guc->state); 210 } 211 212 static bool exec_queue_extra_ref(struct xe_exec_queue *q) 213 { 214 return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_EXTRA_REF; 215 } 216 217 static void set_exec_queue_extra_ref(struct xe_exec_queue *q) 218 { 219 atomic_or(EXEC_QUEUE_STATE_EXTRA_REF, &q->guc->state); 220 } 221 222 static bool exec_queue_killed_or_banned_or_wedged(struct xe_exec_queue *q) 223 { 224 return (atomic_read(&q->guc->state) & 225 (EXEC_QUEUE_STATE_WEDGED | EXEC_QUEUE_STATE_KILLED | 226 EXEC_QUEUE_STATE_BANNED)); 227 } 228 229 static void guc_submit_fini(struct drm_device *drm, void *arg) 230 { 231 struct xe_guc *guc = arg; 232 struct xe_device *xe = guc_to_xe(guc); 233 struct xe_gt *gt = guc_to_gt(guc); 234 int ret; 235 236 ret = wait_event_timeout(guc->submission_state.fini_wq, 237 xa_empty(&guc->submission_state.exec_queue_lookup), 238 HZ * 5); 239 240 drain_workqueue(xe->destroy_wq); 241 242 xe_gt_assert(gt, ret); 243 244 xa_destroy(&guc->submission_state.exec_queue_lookup); 245 } 246 247 static void guc_submit_wedged_fini(void *arg) 248 { 249 struct xe_guc *guc = arg; 250 struct xe_exec_queue *q; 251 unsigned long index; 252 253 mutex_lock(&guc->submission_state.lock); 254 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) { 255 if (exec_queue_wedged(q)) { 256 mutex_unlock(&guc->submission_state.lock); 257 xe_exec_queue_put(q); 258 mutex_lock(&guc->submission_state.lock); 259 } 260 } 261 mutex_unlock(&guc->submission_state.lock); 262 } 263 264 static const struct xe_exec_queue_ops guc_exec_queue_ops; 265 266 static void primelockdep(struct xe_guc *guc) 267 { 268 if (!IS_ENABLED(CONFIG_LOCKDEP)) 269 return; 270 271 fs_reclaim_acquire(GFP_KERNEL); 272 273 mutex_lock(&guc->submission_state.lock); 274 mutex_unlock(&guc->submission_state.lock); 275 276 fs_reclaim_release(GFP_KERNEL); 277 } 278 279 /** 280 * xe_guc_submit_init() - Initialize GuC submission. 281 * @guc: the &xe_guc to initialize 282 * @num_ids: number of GuC context IDs to use 283 * 284 * The bare-metal or PF driver can pass ~0 as &num_ids to indicate that all 285 * GuC context IDs supported by the GuC firmware should be used for submission. 286 * 287 * Only VF drivers will have to provide explicit number of GuC context IDs 288 * that they can use for submission. 289 * 290 * Return: 0 on success or a negative error code on failure. 291 */ 292 int xe_guc_submit_init(struct xe_guc *guc, unsigned int num_ids) 293 { 294 struct xe_device *xe = guc_to_xe(guc); 295 struct xe_gt *gt = guc_to_gt(guc); 296 int err; 297 298 err = drmm_mutex_init(&xe->drm, &guc->submission_state.lock); 299 if (err) 300 return err; 301 302 err = xe_guc_id_mgr_init(&guc->submission_state.idm, num_ids); 303 if (err) 304 return err; 305 306 gt->exec_queue_ops = &guc_exec_queue_ops; 307 308 xa_init(&guc->submission_state.exec_queue_lookup); 309 310 init_waitqueue_head(&guc->submission_state.fini_wq); 311 312 primelockdep(guc); 313 314 guc->submission_state.initialized = true; 315 316 return drmm_add_action_or_reset(&xe->drm, guc_submit_fini, guc); 317 } 318 319 static void __release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q, u32 xa_count) 320 { 321 int i; 322 323 lockdep_assert_held(&guc->submission_state.lock); 324 325 for (i = 0; i < xa_count; ++i) 326 xa_erase(&guc->submission_state.exec_queue_lookup, q->guc->id + i); 327 328 xe_guc_id_mgr_release_locked(&guc->submission_state.idm, 329 q->guc->id, q->width); 330 331 if (xa_empty(&guc->submission_state.exec_queue_lookup)) 332 wake_up(&guc->submission_state.fini_wq); 333 } 334 335 static int alloc_guc_id(struct xe_guc *guc, struct xe_exec_queue *q) 336 { 337 int ret; 338 int i; 339 340 /* 341 * Must use GFP_NOWAIT as this lock is in the dma fence signalling path, 342 * worse case user gets -ENOMEM on engine create and has to try again. 343 * 344 * FIXME: Have caller pre-alloc or post-alloc /w GFP_KERNEL to prevent 345 * failure. 346 */ 347 lockdep_assert_held(&guc->submission_state.lock); 348 349 ret = xe_guc_id_mgr_reserve_locked(&guc->submission_state.idm, 350 q->width); 351 if (ret < 0) 352 return ret; 353 354 q->guc->id = ret; 355 356 for (i = 0; i < q->width; ++i) { 357 ret = xa_err(xa_store(&guc->submission_state.exec_queue_lookup, 358 q->guc->id + i, q, GFP_NOWAIT)); 359 if (ret) 360 goto err_release; 361 } 362 363 return 0; 364 365 err_release: 366 __release_guc_id(guc, q, i); 367 368 return ret; 369 } 370 371 static void release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q) 372 { 373 mutex_lock(&guc->submission_state.lock); 374 __release_guc_id(guc, q, q->width); 375 mutex_unlock(&guc->submission_state.lock); 376 } 377 378 struct exec_queue_policy { 379 u32 count; 380 struct guc_update_exec_queue_policy h2g; 381 }; 382 383 static u32 __guc_exec_queue_policy_action_size(struct exec_queue_policy *policy) 384 { 385 size_t bytes = sizeof(policy->h2g.header) + 386 (sizeof(policy->h2g.klv[0]) * policy->count); 387 388 return bytes / sizeof(u32); 389 } 390 391 static void __guc_exec_queue_policy_start_klv(struct exec_queue_policy *policy, 392 u16 guc_id) 393 { 394 policy->h2g.header.action = 395 XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES; 396 policy->h2g.header.guc_id = guc_id; 397 policy->count = 0; 398 } 399 400 #define MAKE_EXEC_QUEUE_POLICY_ADD(func, id) \ 401 static void __guc_exec_queue_policy_add_##func(struct exec_queue_policy *policy, \ 402 u32 data) \ 403 { \ 404 XE_WARN_ON(policy->count >= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \ 405 \ 406 policy->h2g.klv[policy->count].kl = \ 407 FIELD_PREP(GUC_KLV_0_KEY, \ 408 GUC_CONTEXT_POLICIES_KLV_ID_##id) | \ 409 FIELD_PREP(GUC_KLV_0_LEN, 1); \ 410 policy->h2g.klv[policy->count].value = data; \ 411 policy->count++; \ 412 } 413 414 MAKE_EXEC_QUEUE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM) 415 MAKE_EXEC_QUEUE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT) 416 MAKE_EXEC_QUEUE_POLICY_ADD(priority, SCHEDULING_PRIORITY) 417 MAKE_EXEC_QUEUE_POLICY_ADD(slpc_exec_queue_freq_req, SLPM_GT_FREQUENCY) 418 #undef MAKE_EXEC_QUEUE_POLICY_ADD 419 420 static const int xe_exec_queue_prio_to_guc[] = { 421 [XE_EXEC_QUEUE_PRIORITY_LOW] = GUC_CLIENT_PRIORITY_NORMAL, 422 [XE_EXEC_QUEUE_PRIORITY_NORMAL] = GUC_CLIENT_PRIORITY_KMD_NORMAL, 423 [XE_EXEC_QUEUE_PRIORITY_HIGH] = GUC_CLIENT_PRIORITY_HIGH, 424 [XE_EXEC_QUEUE_PRIORITY_KERNEL] = GUC_CLIENT_PRIORITY_KMD_HIGH, 425 }; 426 427 static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q) 428 { 429 struct exec_queue_policy policy; 430 enum xe_exec_queue_priority prio = q->sched_props.priority; 431 u32 timeslice_us = q->sched_props.timeslice_us; 432 u32 slpc_exec_queue_freq_req = 0; 433 u32 preempt_timeout_us = q->sched_props.preempt_timeout_us; 434 435 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 436 437 if (q->flags & EXEC_QUEUE_FLAG_LOW_LATENCY) 438 slpc_exec_queue_freq_req |= SLPC_CTX_FREQ_REQ_IS_COMPUTE; 439 440 __guc_exec_queue_policy_start_klv(&policy, q->guc->id); 441 __guc_exec_queue_policy_add_priority(&policy, xe_exec_queue_prio_to_guc[prio]); 442 __guc_exec_queue_policy_add_execution_quantum(&policy, timeslice_us); 443 __guc_exec_queue_policy_add_preemption_timeout(&policy, preempt_timeout_us); 444 __guc_exec_queue_policy_add_slpc_exec_queue_freq_req(&policy, 445 slpc_exec_queue_freq_req); 446 447 xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g, 448 __guc_exec_queue_policy_action_size(&policy), 0, 0); 449 } 450 451 static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue *q) 452 { 453 struct exec_queue_policy policy; 454 455 __guc_exec_queue_policy_start_klv(&policy, q->guc->id); 456 __guc_exec_queue_policy_add_preemption_timeout(&policy, 1); 457 458 xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g, 459 __guc_exec_queue_policy_action_size(&policy), 0, 0); 460 } 461 462 #define parallel_read(xe_, map_, field_) \ 463 xe_map_rd_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \ 464 field_) 465 #define parallel_write(xe_, map_, field_, val_) \ 466 xe_map_wr_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \ 467 field_, val_) 468 469 static void __register_mlrc_exec_queue(struct xe_guc *guc, 470 struct xe_exec_queue *q, 471 struct guc_ctxt_registration_info *info) 472 { 473 #define MAX_MLRC_REG_SIZE (13 + XE_HW_ENGINE_MAX_INSTANCE * 2) 474 u32 action[MAX_MLRC_REG_SIZE]; 475 int len = 0; 476 int i; 477 478 xe_gt_assert(guc_to_gt(guc), xe_exec_queue_is_parallel(q)); 479 480 action[len++] = XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC; 481 action[len++] = info->flags; 482 action[len++] = info->context_idx; 483 action[len++] = info->engine_class; 484 action[len++] = info->engine_submit_mask; 485 action[len++] = info->wq_desc_lo; 486 action[len++] = info->wq_desc_hi; 487 action[len++] = info->wq_base_lo; 488 action[len++] = info->wq_base_hi; 489 action[len++] = info->wq_size; 490 action[len++] = q->width; 491 action[len++] = info->hwlrca_lo; 492 action[len++] = info->hwlrca_hi; 493 494 for (i = 1; i < q->width; ++i) { 495 struct xe_lrc *lrc = q->lrc[i]; 496 497 action[len++] = lower_32_bits(xe_lrc_descriptor(lrc)); 498 action[len++] = upper_32_bits(xe_lrc_descriptor(lrc)); 499 } 500 501 xe_gt_assert(guc_to_gt(guc), len <= MAX_MLRC_REG_SIZE); 502 #undef MAX_MLRC_REG_SIZE 503 504 xe_guc_ct_send(&guc->ct, action, len, 0, 0); 505 } 506 507 static void __register_exec_queue(struct xe_guc *guc, 508 struct guc_ctxt_registration_info *info) 509 { 510 u32 action[] = { 511 XE_GUC_ACTION_REGISTER_CONTEXT, 512 info->flags, 513 info->context_idx, 514 info->engine_class, 515 info->engine_submit_mask, 516 info->wq_desc_lo, 517 info->wq_desc_hi, 518 info->wq_base_lo, 519 info->wq_base_hi, 520 info->wq_size, 521 info->hwlrca_lo, 522 info->hwlrca_hi, 523 }; 524 525 xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0); 526 } 527 528 static void register_exec_queue(struct xe_exec_queue *q) 529 { 530 struct xe_guc *guc = exec_queue_to_guc(q); 531 struct xe_device *xe = guc_to_xe(guc); 532 struct xe_lrc *lrc = q->lrc[0]; 533 struct guc_ctxt_registration_info info; 534 535 xe_gt_assert(guc_to_gt(guc), !exec_queue_registered(q)); 536 537 memset(&info, 0, sizeof(info)); 538 info.context_idx = q->guc->id; 539 info.engine_class = xe_engine_class_to_guc_class(q->class); 540 info.engine_submit_mask = q->logical_mask; 541 info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc)); 542 info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc)); 543 info.flags = CONTEXT_REGISTRATION_FLAG_KMD; 544 545 if (xe_exec_queue_is_parallel(q)) { 546 u64 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc); 547 struct iosys_map map = xe_lrc_parallel_map(lrc); 548 549 info.wq_desc_lo = lower_32_bits(ggtt_addr + 550 offsetof(struct guc_submit_parallel_scratch, wq_desc)); 551 info.wq_desc_hi = upper_32_bits(ggtt_addr + 552 offsetof(struct guc_submit_parallel_scratch, wq_desc)); 553 info.wq_base_lo = lower_32_bits(ggtt_addr + 554 offsetof(struct guc_submit_parallel_scratch, wq[0])); 555 info.wq_base_hi = upper_32_bits(ggtt_addr + 556 offsetof(struct guc_submit_parallel_scratch, wq[0])); 557 info.wq_size = WQ_SIZE; 558 559 q->guc->wqi_head = 0; 560 q->guc->wqi_tail = 0; 561 xe_map_memset(xe, &map, 0, 0, PARALLEL_SCRATCH_SIZE - WQ_SIZE); 562 parallel_write(xe, map, wq_desc.wq_status, WQ_STATUS_ACTIVE); 563 } 564 565 /* 566 * We must keep a reference for LR engines if engine is registered with 567 * the GuC as jobs signal immediately and can't destroy an engine if the 568 * GuC has a reference to it. 569 */ 570 if (xe_exec_queue_is_lr(q)) 571 xe_exec_queue_get(q); 572 573 set_exec_queue_registered(q); 574 trace_xe_exec_queue_register(q); 575 if (xe_exec_queue_is_parallel(q)) 576 __register_mlrc_exec_queue(guc, q, &info); 577 else 578 __register_exec_queue(guc, &info); 579 init_policies(guc, q); 580 } 581 582 static u32 wq_space_until_wrap(struct xe_exec_queue *q) 583 { 584 return (WQ_SIZE - q->guc->wqi_tail); 585 } 586 587 static int wq_wait_for_space(struct xe_exec_queue *q, u32 wqi_size) 588 { 589 struct xe_guc *guc = exec_queue_to_guc(q); 590 struct xe_device *xe = guc_to_xe(guc); 591 struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]); 592 unsigned int sleep_period_ms = 1; 593 594 #define AVAILABLE_SPACE \ 595 CIRC_SPACE(q->guc->wqi_tail, q->guc->wqi_head, WQ_SIZE) 596 if (wqi_size > AVAILABLE_SPACE) { 597 try_again: 598 q->guc->wqi_head = parallel_read(xe, map, wq_desc.head); 599 if (wqi_size > AVAILABLE_SPACE) { 600 if (sleep_period_ms == 1024) { 601 xe_gt_reset_async(q->gt); 602 return -ENODEV; 603 } 604 605 msleep(sleep_period_ms); 606 sleep_period_ms <<= 1; 607 goto try_again; 608 } 609 } 610 #undef AVAILABLE_SPACE 611 612 return 0; 613 } 614 615 static int wq_noop_append(struct xe_exec_queue *q) 616 { 617 struct xe_guc *guc = exec_queue_to_guc(q); 618 struct xe_device *xe = guc_to_xe(guc); 619 struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]); 620 u32 len_dw = wq_space_until_wrap(q) / sizeof(u32) - 1; 621 622 if (wq_wait_for_space(q, wq_space_until_wrap(q))) 623 return -ENODEV; 624 625 xe_gt_assert(guc_to_gt(guc), FIELD_FIT(WQ_LEN_MASK, len_dw)); 626 627 parallel_write(xe, map, wq[q->guc->wqi_tail / sizeof(u32)], 628 FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_NOOP) | 629 FIELD_PREP(WQ_LEN_MASK, len_dw)); 630 q->guc->wqi_tail = 0; 631 632 return 0; 633 } 634 635 static void wq_item_append(struct xe_exec_queue *q) 636 { 637 struct xe_guc *guc = exec_queue_to_guc(q); 638 struct xe_device *xe = guc_to_xe(guc); 639 struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]); 640 #define WQ_HEADER_SIZE 4 /* Includes 1 LRC address too */ 641 u32 wqi[XE_HW_ENGINE_MAX_INSTANCE + (WQ_HEADER_SIZE - 1)]; 642 u32 wqi_size = (q->width + (WQ_HEADER_SIZE - 1)) * sizeof(u32); 643 u32 len_dw = (wqi_size / sizeof(u32)) - 1; 644 int i = 0, j; 645 646 if (wqi_size > wq_space_until_wrap(q)) { 647 if (wq_noop_append(q)) 648 return; 649 } 650 if (wq_wait_for_space(q, wqi_size)) 651 return; 652 653 wqi[i++] = FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_MULTI_LRC) | 654 FIELD_PREP(WQ_LEN_MASK, len_dw); 655 wqi[i++] = xe_lrc_descriptor(q->lrc[0]); 656 wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, q->guc->id) | 657 FIELD_PREP(WQ_RING_TAIL_MASK, q->lrc[0]->ring.tail / sizeof(u64)); 658 wqi[i++] = 0; 659 for (j = 1; j < q->width; ++j) { 660 struct xe_lrc *lrc = q->lrc[j]; 661 662 wqi[i++] = lrc->ring.tail / sizeof(u64); 663 } 664 665 xe_gt_assert(guc_to_gt(guc), i == wqi_size / sizeof(u32)); 666 667 iosys_map_incr(&map, offsetof(struct guc_submit_parallel_scratch, 668 wq[q->guc->wqi_tail / sizeof(u32)])); 669 xe_map_memcpy_to(xe, &map, 0, wqi, wqi_size); 670 q->guc->wqi_tail += wqi_size; 671 xe_gt_assert(guc_to_gt(guc), q->guc->wqi_tail <= WQ_SIZE); 672 673 xe_device_wmb(xe); 674 675 map = xe_lrc_parallel_map(q->lrc[0]); 676 parallel_write(xe, map, wq_desc.tail, q->guc->wqi_tail); 677 } 678 679 #define RESUME_PENDING ~0x0ull 680 static void submit_exec_queue(struct xe_exec_queue *q) 681 { 682 struct xe_guc *guc = exec_queue_to_guc(q); 683 struct xe_lrc *lrc = q->lrc[0]; 684 u32 action[3]; 685 u32 g2h_len = 0; 686 u32 num_g2h = 0; 687 int len = 0; 688 bool extra_submit = false; 689 690 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 691 692 if (xe_exec_queue_is_parallel(q)) 693 wq_item_append(q); 694 else 695 xe_lrc_set_ring_tail(lrc, lrc->ring.tail); 696 697 if (exec_queue_suspended(q) && !xe_exec_queue_is_parallel(q)) 698 return; 699 700 if (!exec_queue_enabled(q) && !exec_queue_suspended(q)) { 701 action[len++] = XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET; 702 action[len++] = q->guc->id; 703 action[len++] = GUC_CONTEXT_ENABLE; 704 g2h_len = G2H_LEN_DW_SCHED_CONTEXT_MODE_SET; 705 num_g2h = 1; 706 if (xe_exec_queue_is_parallel(q)) 707 extra_submit = true; 708 709 q->guc->resume_time = RESUME_PENDING; 710 set_exec_queue_pending_enable(q); 711 set_exec_queue_enabled(q); 712 trace_xe_exec_queue_scheduling_enable(q); 713 } else { 714 action[len++] = XE_GUC_ACTION_SCHED_CONTEXT; 715 action[len++] = q->guc->id; 716 trace_xe_exec_queue_submit(q); 717 } 718 719 xe_guc_ct_send(&guc->ct, action, len, g2h_len, num_g2h); 720 721 if (extra_submit) { 722 len = 0; 723 action[len++] = XE_GUC_ACTION_SCHED_CONTEXT; 724 action[len++] = q->guc->id; 725 trace_xe_exec_queue_submit(q); 726 727 xe_guc_ct_send(&guc->ct, action, len, 0, 0); 728 } 729 } 730 731 static struct dma_fence * 732 guc_exec_queue_run_job(struct drm_sched_job *drm_job) 733 { 734 struct xe_sched_job *job = to_xe_sched_job(drm_job); 735 struct xe_exec_queue *q = job->q; 736 struct xe_guc *guc = exec_queue_to_guc(q); 737 struct dma_fence *fence = NULL; 738 bool lr = xe_exec_queue_is_lr(q); 739 740 xe_gt_assert(guc_to_gt(guc), !(exec_queue_destroyed(q) || exec_queue_pending_disable(q)) || 741 exec_queue_banned(q) || exec_queue_suspended(q)); 742 743 trace_xe_sched_job_run(job); 744 745 if (!exec_queue_killed_or_banned_or_wedged(q) && !xe_sched_job_is_error(job)) { 746 if (!exec_queue_registered(q)) 747 register_exec_queue(q); 748 if (!lr) /* LR jobs are emitted in the exec IOCTL */ 749 q->ring_ops->emit_job(job); 750 submit_exec_queue(q); 751 } 752 753 if (lr) { 754 xe_sched_job_set_error(job, -EOPNOTSUPP); 755 dma_fence_put(job->fence); /* Drop ref from xe_sched_job_arm */ 756 } else { 757 fence = job->fence; 758 } 759 760 return fence; 761 } 762 763 static void guc_exec_queue_free_job(struct drm_sched_job *drm_job) 764 { 765 struct xe_sched_job *job = to_xe_sched_job(drm_job); 766 767 trace_xe_sched_job_free(job); 768 xe_sched_job_put(job); 769 } 770 771 int xe_guc_read_stopped(struct xe_guc *guc) 772 { 773 return atomic_read(&guc->submission_state.stopped); 774 } 775 776 #define MAKE_SCHED_CONTEXT_ACTION(q, enable_disable) \ 777 u32 action[] = { \ 778 XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET, \ 779 q->guc->id, \ 780 GUC_CONTEXT_##enable_disable, \ 781 } 782 783 static void disable_scheduling_deregister(struct xe_guc *guc, 784 struct xe_exec_queue *q) 785 { 786 MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); 787 int ret; 788 789 set_min_preemption_timeout(guc, q); 790 smp_rmb(); 791 ret = wait_event_timeout(guc->ct.wq, 792 (!exec_queue_pending_enable(q) && 793 !exec_queue_pending_disable(q)) || 794 xe_guc_read_stopped(guc), 795 HZ * 5); 796 if (!ret) { 797 struct xe_gpu_scheduler *sched = &q->guc->sched; 798 799 xe_gt_warn(q->gt, "Pending enable/disable failed to respond\n"); 800 xe_sched_submission_start(sched); 801 xe_gt_reset_async(q->gt); 802 xe_sched_tdr_queue_imm(sched); 803 return; 804 } 805 806 clear_exec_queue_enabled(q); 807 set_exec_queue_pending_disable(q); 808 set_exec_queue_destroyed(q); 809 trace_xe_exec_queue_scheduling_disable(q); 810 811 /* 812 * Reserve space for both G2H here as the 2nd G2H is sent from a G2H 813 * handler and we are not allowed to reserved G2H space in handlers. 814 */ 815 xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 816 G2H_LEN_DW_SCHED_CONTEXT_MODE_SET + 817 G2H_LEN_DW_DEREGISTER_CONTEXT, 2); 818 } 819 820 static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q) 821 { 822 struct xe_guc *guc = exec_queue_to_guc(q); 823 struct xe_device *xe = guc_to_xe(guc); 824 825 /** to wakeup xe_wait_user_fence ioctl if exec queue is reset */ 826 wake_up_all(&xe->ufence_wq); 827 828 if (xe_exec_queue_is_lr(q)) 829 queue_work(guc_to_gt(guc)->ordered_wq, &q->guc->lr_tdr); 830 else 831 xe_sched_tdr_queue_imm(&q->guc->sched); 832 } 833 834 /** 835 * xe_guc_submit_wedge() - Wedge GuC submission 836 * @guc: the GuC object 837 * 838 * Save exec queue's registered with GuC state by taking a ref to each queue. 839 * Register a DRMM handler to drop refs upon driver unload. 840 */ 841 void xe_guc_submit_wedge(struct xe_guc *guc) 842 { 843 struct xe_gt *gt = guc_to_gt(guc); 844 struct xe_exec_queue *q; 845 unsigned long index; 846 int err; 847 848 xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode); 849 850 /* 851 * If device is being wedged even before submission_state is 852 * initialized, there's nothing to do here. 853 */ 854 if (!guc->submission_state.initialized) 855 return; 856 857 err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev, 858 guc_submit_wedged_fini, guc); 859 if (err) { 860 xe_gt_err(gt, "Failed to register clean-up on wedged.mode=2; " 861 "Although device is wedged.\n"); 862 return; 863 } 864 865 mutex_lock(&guc->submission_state.lock); 866 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) 867 if (xe_exec_queue_get_unless_zero(q)) 868 set_exec_queue_wedged(q); 869 mutex_unlock(&guc->submission_state.lock); 870 } 871 872 static bool guc_submit_hint_wedged(struct xe_guc *guc) 873 { 874 struct xe_device *xe = guc_to_xe(guc); 875 876 if (xe->wedged.mode != 2) 877 return false; 878 879 if (xe_device_wedged(xe)) 880 return true; 881 882 xe_device_declare_wedged(xe); 883 884 return true; 885 } 886 887 static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w) 888 { 889 struct xe_guc_exec_queue *ge = 890 container_of(w, struct xe_guc_exec_queue, lr_tdr); 891 struct xe_exec_queue *q = ge->q; 892 struct xe_guc *guc = exec_queue_to_guc(q); 893 struct xe_gpu_scheduler *sched = &ge->sched; 894 bool wedged = false; 895 896 xe_gt_assert(guc_to_gt(guc), xe_exec_queue_is_lr(q)); 897 trace_xe_exec_queue_lr_cleanup(q); 898 899 if (!exec_queue_killed(q)) 900 wedged = guc_submit_hint_wedged(exec_queue_to_guc(q)); 901 902 /* Kill the run_job / process_msg entry points */ 903 xe_sched_submission_stop(sched); 904 905 /* 906 * Engine state now mostly stable, disable scheduling / deregister if 907 * needed. This cleanup routine might be called multiple times, where 908 * the actual async engine deregister drops the final engine ref. 909 * Calling disable_scheduling_deregister will mark the engine as 910 * destroyed and fire off the CT requests to disable scheduling / 911 * deregister, which we only want to do once. We also don't want to mark 912 * the engine as pending_disable again as this may race with the 913 * xe_guc_deregister_done_handler() which treats it as an unexpected 914 * state. 915 */ 916 if (!wedged && exec_queue_registered(q) && !exec_queue_destroyed(q)) { 917 struct xe_guc *guc = exec_queue_to_guc(q); 918 int ret; 919 920 set_exec_queue_banned(q); 921 disable_scheduling_deregister(guc, q); 922 923 /* 924 * Must wait for scheduling to be disabled before signalling 925 * any fences, if GT broken the GT reset code should signal us. 926 */ 927 ret = wait_event_timeout(guc->ct.wq, 928 !exec_queue_pending_disable(q) || 929 xe_guc_read_stopped(guc), HZ * 5); 930 if (!ret) { 931 xe_gt_warn(q->gt, "Schedule disable failed to respond, guc_id=%d\n", 932 q->guc->id); 933 xe_devcoredump(q, NULL, "Schedule disable failed to respond, guc_id=%d\n", 934 q->guc->id); 935 xe_sched_submission_start(sched); 936 xe_gt_reset_async(q->gt); 937 return; 938 } 939 } 940 941 if (!exec_queue_killed(q) && !xe_lrc_ring_is_idle(q->lrc[0])) 942 xe_devcoredump(q, NULL, "LR job cleanup, guc_id=%d", q->guc->id); 943 944 xe_sched_submission_start(sched); 945 } 946 947 #define ADJUST_FIVE_PERCENT(__t) mul_u64_u32_div(__t, 105, 100) 948 949 static bool check_timeout(struct xe_exec_queue *q, struct xe_sched_job *job) 950 { 951 struct xe_gt *gt = guc_to_gt(exec_queue_to_guc(q)); 952 u32 ctx_timestamp, ctx_job_timestamp; 953 u32 timeout_ms = q->sched_props.job_timeout_ms; 954 u32 diff; 955 u64 running_time_ms; 956 957 if (!xe_sched_job_started(job)) { 958 xe_gt_warn(gt, "Check job timeout: seqno=%u, lrc_seqno=%u, guc_id=%d, not started", 959 xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job), 960 q->guc->id); 961 962 return xe_sched_invalidate_job(job, 2); 963 } 964 965 ctx_timestamp = lower_32_bits(xe_lrc_ctx_timestamp(q->lrc[0])); 966 ctx_job_timestamp = xe_lrc_ctx_job_timestamp(q->lrc[0]); 967 968 /* 969 * Counter wraps at ~223s at the usual 19.2MHz, be paranoid catch 970 * possible overflows with a high timeout. 971 */ 972 xe_gt_assert(gt, timeout_ms < 100 * MSEC_PER_SEC); 973 974 if (ctx_timestamp < ctx_job_timestamp) 975 diff = ctx_timestamp + U32_MAX - ctx_job_timestamp; 976 else 977 diff = ctx_timestamp - ctx_job_timestamp; 978 979 /* 980 * Ensure timeout is within 5% to account for an GuC scheduling latency 981 */ 982 running_time_ms = 983 ADJUST_FIVE_PERCENT(xe_gt_clock_interval_to_ms(gt, diff)); 984 985 xe_gt_dbg(gt, 986 "Check job timeout: seqno=%u, lrc_seqno=%u, guc_id=%d, running_time_ms=%llu, timeout_ms=%u, diff=0x%08x", 987 xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job), 988 q->guc->id, running_time_ms, timeout_ms, diff); 989 990 return running_time_ms >= timeout_ms; 991 } 992 993 static void enable_scheduling(struct xe_exec_queue *q) 994 { 995 MAKE_SCHED_CONTEXT_ACTION(q, ENABLE); 996 struct xe_guc *guc = exec_queue_to_guc(q); 997 int ret; 998 999 xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q)); 1000 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 1001 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q)); 1002 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q)); 1003 1004 set_exec_queue_pending_enable(q); 1005 set_exec_queue_enabled(q); 1006 trace_xe_exec_queue_scheduling_enable(q); 1007 1008 xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 1009 G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1); 1010 1011 ret = wait_event_timeout(guc->ct.wq, 1012 !exec_queue_pending_enable(q) || 1013 xe_guc_read_stopped(guc), HZ * 5); 1014 if (!ret || xe_guc_read_stopped(guc)) { 1015 xe_gt_warn(guc_to_gt(guc), "Schedule enable failed to respond"); 1016 set_exec_queue_banned(q); 1017 xe_gt_reset_async(q->gt); 1018 xe_sched_tdr_queue_imm(&q->guc->sched); 1019 } 1020 } 1021 1022 static void disable_scheduling(struct xe_exec_queue *q, bool immediate) 1023 { 1024 MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); 1025 struct xe_guc *guc = exec_queue_to_guc(q); 1026 1027 xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q)); 1028 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 1029 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q)); 1030 1031 if (immediate) 1032 set_min_preemption_timeout(guc, q); 1033 clear_exec_queue_enabled(q); 1034 set_exec_queue_pending_disable(q); 1035 trace_xe_exec_queue_scheduling_disable(q); 1036 1037 xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 1038 G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1); 1039 } 1040 1041 static void __deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q) 1042 { 1043 u32 action[] = { 1044 XE_GUC_ACTION_DEREGISTER_CONTEXT, 1045 q->guc->id, 1046 }; 1047 1048 xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q)); 1049 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 1050 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q)); 1051 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q)); 1052 1053 set_exec_queue_destroyed(q); 1054 trace_xe_exec_queue_deregister(q); 1055 1056 xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 1057 G2H_LEN_DW_DEREGISTER_CONTEXT, 1); 1058 } 1059 1060 static enum drm_gpu_sched_stat 1061 guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) 1062 { 1063 struct xe_sched_job *job = to_xe_sched_job(drm_job); 1064 struct xe_sched_job *tmp_job; 1065 struct xe_exec_queue *q = job->q; 1066 struct xe_gpu_scheduler *sched = &q->guc->sched; 1067 struct xe_guc *guc = exec_queue_to_guc(q); 1068 const char *process_name = "no process"; 1069 struct xe_device *xe = guc_to_xe(guc); 1070 unsigned int fw_ref; 1071 int err = -ETIME; 1072 pid_t pid = -1; 1073 int i = 0; 1074 bool wedged = false, skip_timeout_check; 1075 1076 /* 1077 * TDR has fired before free job worker. Common if exec queue 1078 * immediately closed after last fence signaled. Add back to pending 1079 * list so job can be freed and kick scheduler ensuring free job is not 1080 * lost. 1081 */ 1082 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &job->fence->flags)) { 1083 xe_sched_add_pending_job(sched, job); 1084 xe_sched_submission_start(sched); 1085 1086 return DRM_GPU_SCHED_STAT_NOMINAL; 1087 } 1088 1089 /* Kill the run_job entry point */ 1090 xe_sched_submission_stop(sched); 1091 1092 /* Must check all state after stopping scheduler */ 1093 skip_timeout_check = exec_queue_reset(q) || 1094 exec_queue_killed_or_banned_or_wedged(q) || 1095 exec_queue_destroyed(q); 1096 1097 /* 1098 * If devcoredump not captured and GuC capture for the job is not ready 1099 * do manual capture first and decide later if we need to use it 1100 */ 1101 if (!exec_queue_killed(q) && !xe->devcoredump.captured && 1102 !xe_guc_capture_get_matching_and_lock(q)) { 1103 /* take force wake before engine register manual capture */ 1104 fw_ref = xe_force_wake_get(gt_to_fw(q->gt), XE_FORCEWAKE_ALL); 1105 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) 1106 xe_gt_info(q->gt, "failed to get forcewake for coredump capture\n"); 1107 1108 xe_engine_snapshot_capture_for_queue(q); 1109 1110 xe_force_wake_put(gt_to_fw(q->gt), fw_ref); 1111 } 1112 1113 /* 1114 * XXX: Sampling timeout doesn't work in wedged mode as we have to 1115 * modify scheduling state to read timestamp. We could read the 1116 * timestamp from a register to accumulate current running time but this 1117 * doesn't work for SRIOV. For now assuming timeouts in wedged mode are 1118 * genuine timeouts. 1119 */ 1120 if (!exec_queue_killed(q)) 1121 wedged = guc_submit_hint_wedged(exec_queue_to_guc(q)); 1122 1123 /* Engine state now stable, disable scheduling to check timestamp */ 1124 if (!wedged && exec_queue_registered(q)) { 1125 int ret; 1126 1127 if (exec_queue_reset(q)) 1128 err = -EIO; 1129 1130 if (!exec_queue_destroyed(q)) { 1131 /* 1132 * Wait for any pending G2H to flush out before 1133 * modifying state 1134 */ 1135 ret = wait_event_timeout(guc->ct.wq, 1136 (!exec_queue_pending_enable(q) && 1137 !exec_queue_pending_disable(q)) || 1138 xe_guc_read_stopped(guc), HZ * 5); 1139 if (!ret || xe_guc_read_stopped(guc)) 1140 goto trigger_reset; 1141 1142 /* 1143 * Flag communicates to G2H handler that schedule 1144 * disable originated from a timeout check. The G2H then 1145 * avoid triggering cleanup or deregistering the exec 1146 * queue. 1147 */ 1148 set_exec_queue_check_timeout(q); 1149 disable_scheduling(q, skip_timeout_check); 1150 } 1151 1152 /* 1153 * Must wait for scheduling to be disabled before signalling 1154 * any fences, if GT broken the GT reset code should signal us. 1155 * 1156 * FIXME: Tests can generate a ton of 0x6000 (IOMMU CAT fault 1157 * error) messages which can cause the schedule disable to get 1158 * lost. If this occurs, trigger a GT reset to recover. 1159 */ 1160 smp_rmb(); 1161 ret = wait_event_timeout(guc->ct.wq, 1162 !exec_queue_pending_disable(q) || 1163 xe_guc_read_stopped(guc), HZ * 5); 1164 if (!ret || xe_guc_read_stopped(guc)) { 1165 trigger_reset: 1166 if (!ret) 1167 xe_gt_warn(guc_to_gt(guc), 1168 "Schedule disable failed to respond, guc_id=%d", 1169 q->guc->id); 1170 xe_devcoredump(q, job, 1171 "Schedule disable failed to respond, guc_id=%d, ret=%d, guc_read=%d", 1172 q->guc->id, ret, xe_guc_read_stopped(guc)); 1173 set_exec_queue_extra_ref(q); 1174 xe_exec_queue_get(q); /* GT reset owns this */ 1175 set_exec_queue_banned(q); 1176 xe_gt_reset_async(q->gt); 1177 xe_sched_tdr_queue_imm(sched); 1178 goto rearm; 1179 } 1180 } 1181 1182 /* 1183 * Check if job is actually timed out, if so restart job execution and TDR 1184 */ 1185 if (!wedged && !skip_timeout_check && !check_timeout(q, job) && 1186 !exec_queue_reset(q) && exec_queue_registered(q)) { 1187 clear_exec_queue_check_timeout(q); 1188 goto sched_enable; 1189 } 1190 1191 if (q->vm && q->vm->xef) { 1192 process_name = q->vm->xef->process_name; 1193 pid = q->vm->xef->pid; 1194 } 1195 1196 if (!exec_queue_killed(q)) 1197 xe_gt_notice(guc_to_gt(guc), 1198 "Timedout job: seqno=%u, lrc_seqno=%u, guc_id=%d, flags=0x%lx in %s [%d]", 1199 xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job), 1200 q->guc->id, q->flags, process_name, pid); 1201 1202 trace_xe_sched_job_timedout(job); 1203 1204 if (!exec_queue_killed(q)) 1205 xe_devcoredump(q, job, 1206 "Timedout job - seqno=%u, lrc_seqno=%u, guc_id=%d, flags=0x%lx", 1207 xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job), 1208 q->guc->id, q->flags); 1209 1210 /* 1211 * Kernel jobs should never fail, nor should VM jobs if they do 1212 * somethings has gone wrong and the GT needs a reset 1213 */ 1214 xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_KERNEL, 1215 "Kernel-submitted job timed out\n"); 1216 xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q), 1217 "VM job timed out on non-killed execqueue\n"); 1218 if (!wedged && (q->flags & EXEC_QUEUE_FLAG_KERNEL || 1219 (q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q)))) { 1220 if (!xe_sched_invalidate_job(job, 2)) { 1221 clear_exec_queue_check_timeout(q); 1222 xe_gt_reset_async(q->gt); 1223 goto rearm; 1224 } 1225 } 1226 1227 /* Finish cleaning up exec queue via deregister */ 1228 set_exec_queue_banned(q); 1229 if (!wedged && exec_queue_registered(q) && !exec_queue_destroyed(q)) { 1230 set_exec_queue_extra_ref(q); 1231 xe_exec_queue_get(q); 1232 __deregister_exec_queue(guc, q); 1233 } 1234 1235 /* Stop fence signaling */ 1236 xe_hw_fence_irq_stop(q->fence_irq); 1237 1238 /* 1239 * Fence state now stable, stop / start scheduler which cleans up any 1240 * fences that are complete 1241 */ 1242 xe_sched_add_pending_job(sched, job); 1243 xe_sched_submission_start(sched); 1244 1245 xe_guc_exec_queue_trigger_cleanup(q); 1246 1247 /* Mark all outstanding jobs as bad, thus completing them */ 1248 spin_lock(&sched->base.job_list_lock); 1249 list_for_each_entry(tmp_job, &sched->base.pending_list, drm.list) 1250 xe_sched_job_set_error(tmp_job, !i++ ? err : -ECANCELED); 1251 spin_unlock(&sched->base.job_list_lock); 1252 1253 /* Start fence signaling */ 1254 xe_hw_fence_irq_start(q->fence_irq); 1255 1256 return DRM_GPU_SCHED_STAT_NOMINAL; 1257 1258 sched_enable: 1259 enable_scheduling(q); 1260 rearm: 1261 /* 1262 * XXX: Ideally want to adjust timeout based on current execution time 1263 * but there is not currently an easy way to do in DRM scheduler. With 1264 * some thought, do this in a follow up. 1265 */ 1266 xe_sched_add_pending_job(sched, job); 1267 xe_sched_submission_start(sched); 1268 1269 return DRM_GPU_SCHED_STAT_NOMINAL; 1270 } 1271 1272 static void __guc_exec_queue_fini_async(struct work_struct *w) 1273 { 1274 struct xe_guc_exec_queue *ge = 1275 container_of(w, struct xe_guc_exec_queue, fini_async); 1276 struct xe_exec_queue *q = ge->q; 1277 struct xe_guc *guc = exec_queue_to_guc(q); 1278 1279 xe_pm_runtime_get(guc_to_xe(guc)); 1280 trace_xe_exec_queue_destroy(q); 1281 1282 release_guc_id(guc, q); 1283 if (xe_exec_queue_is_lr(q)) 1284 cancel_work_sync(&ge->lr_tdr); 1285 /* Confirm no work left behind accessing device structures */ 1286 cancel_delayed_work_sync(&ge->sched.base.work_tdr); 1287 xe_sched_entity_fini(&ge->entity); 1288 xe_sched_fini(&ge->sched); 1289 1290 kfree(ge); 1291 xe_exec_queue_fini(q); 1292 xe_pm_runtime_put(guc_to_xe(guc)); 1293 } 1294 1295 static void guc_exec_queue_fini_async(struct xe_exec_queue *q) 1296 { 1297 struct xe_guc *guc = exec_queue_to_guc(q); 1298 struct xe_device *xe = guc_to_xe(guc); 1299 1300 INIT_WORK(&q->guc->fini_async, __guc_exec_queue_fini_async); 1301 1302 /* We must block on kernel engines so slabs are empty on driver unload */ 1303 if (q->flags & EXEC_QUEUE_FLAG_PERMANENT || exec_queue_wedged(q)) 1304 __guc_exec_queue_fini_async(&q->guc->fini_async); 1305 else 1306 queue_work(xe->destroy_wq, &q->guc->fini_async); 1307 } 1308 1309 static void __guc_exec_queue_fini(struct xe_guc *guc, struct xe_exec_queue *q) 1310 { 1311 /* 1312 * Might be done from within the GPU scheduler, need to do async as we 1313 * fini the scheduler when the engine is fini'd, the scheduler can't 1314 * complete fini within itself (circular dependency). Async resolves 1315 * this we and don't really care when everything is fini'd, just that it 1316 * is. 1317 */ 1318 guc_exec_queue_fini_async(q); 1319 } 1320 1321 static void __guc_exec_queue_process_msg_cleanup(struct xe_sched_msg *msg) 1322 { 1323 struct xe_exec_queue *q = msg->private_data; 1324 struct xe_guc *guc = exec_queue_to_guc(q); 1325 1326 xe_gt_assert(guc_to_gt(guc), !(q->flags & EXEC_QUEUE_FLAG_PERMANENT)); 1327 trace_xe_exec_queue_cleanup_entity(q); 1328 1329 if (exec_queue_registered(q)) 1330 disable_scheduling_deregister(guc, q); 1331 else 1332 __guc_exec_queue_fini(guc, q); 1333 } 1334 1335 static bool guc_exec_queue_allowed_to_change_state(struct xe_exec_queue *q) 1336 { 1337 return !exec_queue_killed_or_banned_or_wedged(q) && exec_queue_registered(q); 1338 } 1339 1340 static void __guc_exec_queue_process_msg_set_sched_props(struct xe_sched_msg *msg) 1341 { 1342 struct xe_exec_queue *q = msg->private_data; 1343 struct xe_guc *guc = exec_queue_to_guc(q); 1344 1345 if (guc_exec_queue_allowed_to_change_state(q)) 1346 init_policies(guc, q); 1347 kfree(msg); 1348 } 1349 1350 static void __suspend_fence_signal(struct xe_exec_queue *q) 1351 { 1352 if (!q->guc->suspend_pending) 1353 return; 1354 1355 WRITE_ONCE(q->guc->suspend_pending, false); 1356 wake_up(&q->guc->suspend_wait); 1357 } 1358 1359 static void suspend_fence_signal(struct xe_exec_queue *q) 1360 { 1361 struct xe_guc *guc = exec_queue_to_guc(q); 1362 1363 xe_gt_assert(guc_to_gt(guc), exec_queue_suspended(q) || exec_queue_killed(q) || 1364 xe_guc_read_stopped(guc)); 1365 xe_gt_assert(guc_to_gt(guc), q->guc->suspend_pending); 1366 1367 __suspend_fence_signal(q); 1368 } 1369 1370 static void __guc_exec_queue_process_msg_suspend(struct xe_sched_msg *msg) 1371 { 1372 struct xe_exec_queue *q = msg->private_data; 1373 struct xe_guc *guc = exec_queue_to_guc(q); 1374 1375 if (guc_exec_queue_allowed_to_change_state(q) && !exec_queue_suspended(q) && 1376 exec_queue_enabled(q)) { 1377 wait_event(guc->ct.wq, (q->guc->resume_time != RESUME_PENDING || 1378 xe_guc_read_stopped(guc)) && !exec_queue_pending_disable(q)); 1379 1380 if (!xe_guc_read_stopped(guc)) { 1381 s64 since_resume_ms = 1382 ktime_ms_delta(ktime_get(), 1383 q->guc->resume_time); 1384 s64 wait_ms = q->vm->preempt.min_run_period_ms - 1385 since_resume_ms; 1386 1387 if (wait_ms > 0 && q->guc->resume_time) 1388 msleep(wait_ms); 1389 1390 set_exec_queue_suspended(q); 1391 disable_scheduling(q, false); 1392 } 1393 } else if (q->guc->suspend_pending) { 1394 set_exec_queue_suspended(q); 1395 suspend_fence_signal(q); 1396 } 1397 } 1398 1399 static void __guc_exec_queue_process_msg_resume(struct xe_sched_msg *msg) 1400 { 1401 struct xe_exec_queue *q = msg->private_data; 1402 1403 if (guc_exec_queue_allowed_to_change_state(q)) { 1404 clear_exec_queue_suspended(q); 1405 if (!exec_queue_enabled(q)) { 1406 q->guc->resume_time = RESUME_PENDING; 1407 enable_scheduling(q); 1408 } 1409 } else { 1410 clear_exec_queue_suspended(q); 1411 } 1412 } 1413 1414 #define CLEANUP 1 /* Non-zero values to catch uninitialized msg */ 1415 #define SET_SCHED_PROPS 2 1416 #define SUSPEND 3 1417 #define RESUME 4 1418 #define OPCODE_MASK 0xf 1419 #define MSG_LOCKED BIT(8) 1420 1421 static void guc_exec_queue_process_msg(struct xe_sched_msg *msg) 1422 { 1423 struct xe_device *xe = guc_to_xe(exec_queue_to_guc(msg->private_data)); 1424 1425 trace_xe_sched_msg_recv(msg); 1426 1427 switch (msg->opcode) { 1428 case CLEANUP: 1429 __guc_exec_queue_process_msg_cleanup(msg); 1430 break; 1431 case SET_SCHED_PROPS: 1432 __guc_exec_queue_process_msg_set_sched_props(msg); 1433 break; 1434 case SUSPEND: 1435 __guc_exec_queue_process_msg_suspend(msg); 1436 break; 1437 case RESUME: 1438 __guc_exec_queue_process_msg_resume(msg); 1439 break; 1440 default: 1441 XE_WARN_ON("Unknown message type"); 1442 } 1443 1444 xe_pm_runtime_put(xe); 1445 } 1446 1447 static const struct drm_sched_backend_ops drm_sched_ops = { 1448 .run_job = guc_exec_queue_run_job, 1449 .free_job = guc_exec_queue_free_job, 1450 .timedout_job = guc_exec_queue_timedout_job, 1451 }; 1452 1453 static const struct xe_sched_backend_ops xe_sched_ops = { 1454 .process_msg = guc_exec_queue_process_msg, 1455 }; 1456 1457 static int guc_exec_queue_init(struct xe_exec_queue *q) 1458 { 1459 struct xe_gpu_scheduler *sched; 1460 struct xe_guc *guc = exec_queue_to_guc(q); 1461 struct xe_guc_exec_queue *ge; 1462 long timeout; 1463 int err, i; 1464 1465 xe_gt_assert(guc_to_gt(guc), xe_device_uc_enabled(guc_to_xe(guc))); 1466 1467 ge = kzalloc(sizeof(*ge), GFP_KERNEL); 1468 if (!ge) 1469 return -ENOMEM; 1470 1471 q->guc = ge; 1472 ge->q = q; 1473 init_waitqueue_head(&ge->suspend_wait); 1474 1475 for (i = 0; i < MAX_STATIC_MSG_TYPE; ++i) 1476 INIT_LIST_HEAD(&ge->static_msgs[i].link); 1477 1478 timeout = (q->vm && xe_vm_in_lr_mode(q->vm)) ? MAX_SCHEDULE_TIMEOUT : 1479 msecs_to_jiffies(q->sched_props.job_timeout_ms); 1480 err = xe_sched_init(&ge->sched, &drm_sched_ops, &xe_sched_ops, 1481 NULL, q->lrc[0]->ring.size / MAX_JOB_SIZE_BYTES, 64, 1482 timeout, guc_to_gt(guc)->ordered_wq, NULL, 1483 q->name, gt_to_xe(q->gt)->drm.dev); 1484 if (err) 1485 goto err_free; 1486 1487 sched = &ge->sched; 1488 err = xe_sched_entity_init(&ge->entity, sched); 1489 if (err) 1490 goto err_sched; 1491 1492 if (xe_exec_queue_is_lr(q)) 1493 INIT_WORK(&q->guc->lr_tdr, xe_guc_exec_queue_lr_cleanup); 1494 1495 mutex_lock(&guc->submission_state.lock); 1496 1497 err = alloc_guc_id(guc, q); 1498 if (err) 1499 goto err_entity; 1500 1501 q->entity = &ge->entity; 1502 1503 if (xe_guc_read_stopped(guc)) 1504 xe_sched_stop(sched); 1505 1506 mutex_unlock(&guc->submission_state.lock); 1507 1508 xe_exec_queue_assign_name(q, q->guc->id); 1509 1510 trace_xe_exec_queue_create(q); 1511 1512 return 0; 1513 1514 err_entity: 1515 mutex_unlock(&guc->submission_state.lock); 1516 xe_sched_entity_fini(&ge->entity); 1517 err_sched: 1518 xe_sched_fini(&ge->sched); 1519 err_free: 1520 kfree(ge); 1521 1522 return err; 1523 } 1524 1525 static void guc_exec_queue_kill(struct xe_exec_queue *q) 1526 { 1527 trace_xe_exec_queue_kill(q); 1528 set_exec_queue_killed(q); 1529 __suspend_fence_signal(q); 1530 xe_guc_exec_queue_trigger_cleanup(q); 1531 } 1532 1533 static void guc_exec_queue_add_msg(struct xe_exec_queue *q, struct xe_sched_msg *msg, 1534 u32 opcode) 1535 { 1536 xe_pm_runtime_get_noresume(guc_to_xe(exec_queue_to_guc(q))); 1537 1538 INIT_LIST_HEAD(&msg->link); 1539 msg->opcode = opcode & OPCODE_MASK; 1540 msg->private_data = q; 1541 1542 trace_xe_sched_msg_add(msg); 1543 if (opcode & MSG_LOCKED) 1544 xe_sched_add_msg_locked(&q->guc->sched, msg); 1545 else 1546 xe_sched_add_msg(&q->guc->sched, msg); 1547 } 1548 1549 static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q, 1550 struct xe_sched_msg *msg, 1551 u32 opcode) 1552 { 1553 if (!list_empty(&msg->link)) 1554 return false; 1555 1556 guc_exec_queue_add_msg(q, msg, opcode | MSG_LOCKED); 1557 1558 return true; 1559 } 1560 1561 #define STATIC_MSG_CLEANUP 0 1562 #define STATIC_MSG_SUSPEND 1 1563 #define STATIC_MSG_RESUME 2 1564 static void guc_exec_queue_fini(struct xe_exec_queue *q) 1565 { 1566 struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP; 1567 1568 if (!(q->flags & EXEC_QUEUE_FLAG_PERMANENT) && !exec_queue_wedged(q)) 1569 guc_exec_queue_add_msg(q, msg, CLEANUP); 1570 else 1571 __guc_exec_queue_fini(exec_queue_to_guc(q), q); 1572 } 1573 1574 static int guc_exec_queue_set_priority(struct xe_exec_queue *q, 1575 enum xe_exec_queue_priority priority) 1576 { 1577 struct xe_sched_msg *msg; 1578 1579 if (q->sched_props.priority == priority || 1580 exec_queue_killed_or_banned_or_wedged(q)) 1581 return 0; 1582 1583 msg = kmalloc(sizeof(*msg), GFP_KERNEL); 1584 if (!msg) 1585 return -ENOMEM; 1586 1587 q->sched_props.priority = priority; 1588 guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); 1589 1590 return 0; 1591 } 1592 1593 static int guc_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us) 1594 { 1595 struct xe_sched_msg *msg; 1596 1597 if (q->sched_props.timeslice_us == timeslice_us || 1598 exec_queue_killed_or_banned_or_wedged(q)) 1599 return 0; 1600 1601 msg = kmalloc(sizeof(*msg), GFP_KERNEL); 1602 if (!msg) 1603 return -ENOMEM; 1604 1605 q->sched_props.timeslice_us = timeslice_us; 1606 guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); 1607 1608 return 0; 1609 } 1610 1611 static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q, 1612 u32 preempt_timeout_us) 1613 { 1614 struct xe_sched_msg *msg; 1615 1616 if (q->sched_props.preempt_timeout_us == preempt_timeout_us || 1617 exec_queue_killed_or_banned_or_wedged(q)) 1618 return 0; 1619 1620 msg = kmalloc(sizeof(*msg), GFP_KERNEL); 1621 if (!msg) 1622 return -ENOMEM; 1623 1624 q->sched_props.preempt_timeout_us = preempt_timeout_us; 1625 guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); 1626 1627 return 0; 1628 } 1629 1630 static int guc_exec_queue_suspend(struct xe_exec_queue *q) 1631 { 1632 struct xe_gpu_scheduler *sched = &q->guc->sched; 1633 struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_SUSPEND; 1634 1635 if (exec_queue_killed_or_banned_or_wedged(q)) 1636 return -EINVAL; 1637 1638 xe_sched_msg_lock(sched); 1639 if (guc_exec_queue_try_add_msg(q, msg, SUSPEND)) 1640 q->guc->suspend_pending = true; 1641 xe_sched_msg_unlock(sched); 1642 1643 return 0; 1644 } 1645 1646 static int guc_exec_queue_suspend_wait(struct xe_exec_queue *q) 1647 { 1648 struct xe_guc *guc = exec_queue_to_guc(q); 1649 int ret; 1650 1651 /* 1652 * Likely don't need to check exec_queue_killed() as we clear 1653 * suspend_pending upon kill but to be paranoid but races in which 1654 * suspend_pending is set after kill also check kill here. 1655 */ 1656 ret = wait_event_interruptible_timeout(q->guc->suspend_wait, 1657 !READ_ONCE(q->guc->suspend_pending) || 1658 exec_queue_killed(q) || 1659 xe_guc_read_stopped(guc), 1660 HZ * 5); 1661 1662 if (!ret) { 1663 xe_gt_warn(guc_to_gt(guc), 1664 "Suspend fence, guc_id=%d, failed to respond", 1665 q->guc->id); 1666 /* XXX: Trigger GT reset? */ 1667 return -ETIME; 1668 } 1669 1670 return ret < 0 ? ret : 0; 1671 } 1672 1673 static void guc_exec_queue_resume(struct xe_exec_queue *q) 1674 { 1675 struct xe_gpu_scheduler *sched = &q->guc->sched; 1676 struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_RESUME; 1677 struct xe_guc *guc = exec_queue_to_guc(q); 1678 1679 xe_gt_assert(guc_to_gt(guc), !q->guc->suspend_pending); 1680 1681 xe_sched_msg_lock(sched); 1682 guc_exec_queue_try_add_msg(q, msg, RESUME); 1683 xe_sched_msg_unlock(sched); 1684 } 1685 1686 static bool guc_exec_queue_reset_status(struct xe_exec_queue *q) 1687 { 1688 return exec_queue_reset(q) || exec_queue_killed_or_banned_or_wedged(q); 1689 } 1690 1691 /* 1692 * All of these functions are an abstraction layer which other parts of XE can 1693 * use to trap into the GuC backend. All of these functions, aside from init, 1694 * really shouldn't do much other than trap into the DRM scheduler which 1695 * synchronizes these operations. 1696 */ 1697 static const struct xe_exec_queue_ops guc_exec_queue_ops = { 1698 .init = guc_exec_queue_init, 1699 .kill = guc_exec_queue_kill, 1700 .fini = guc_exec_queue_fini, 1701 .set_priority = guc_exec_queue_set_priority, 1702 .set_timeslice = guc_exec_queue_set_timeslice, 1703 .set_preempt_timeout = guc_exec_queue_set_preempt_timeout, 1704 .suspend = guc_exec_queue_suspend, 1705 .suspend_wait = guc_exec_queue_suspend_wait, 1706 .resume = guc_exec_queue_resume, 1707 .reset_status = guc_exec_queue_reset_status, 1708 }; 1709 1710 static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q) 1711 { 1712 struct xe_gpu_scheduler *sched = &q->guc->sched; 1713 1714 /* Stop scheduling + flush any DRM scheduler operations */ 1715 xe_sched_submission_stop(sched); 1716 1717 /* Clean up lost G2H + reset engine state */ 1718 if (exec_queue_registered(q)) { 1719 if (exec_queue_extra_ref(q) || xe_exec_queue_is_lr(q)) 1720 xe_exec_queue_put(q); 1721 else if (exec_queue_destroyed(q)) 1722 __guc_exec_queue_fini(guc, q); 1723 } 1724 if (q->guc->suspend_pending) { 1725 set_exec_queue_suspended(q); 1726 suspend_fence_signal(q); 1727 } 1728 atomic_and(EXEC_QUEUE_STATE_WEDGED | EXEC_QUEUE_STATE_BANNED | 1729 EXEC_QUEUE_STATE_KILLED | EXEC_QUEUE_STATE_DESTROYED | 1730 EXEC_QUEUE_STATE_SUSPENDED, 1731 &q->guc->state); 1732 q->guc->resume_time = 0; 1733 trace_xe_exec_queue_stop(q); 1734 1735 /* 1736 * Ban any engine (aside from kernel and engines used for VM ops) with a 1737 * started but not complete job or if a job has gone through a GT reset 1738 * more than twice. 1739 */ 1740 if (!(q->flags & (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM))) { 1741 struct xe_sched_job *job = xe_sched_first_pending_job(sched); 1742 bool ban = false; 1743 1744 if (job) { 1745 if ((xe_sched_job_started(job) && 1746 !xe_sched_job_completed(job)) || 1747 xe_sched_invalidate_job(job, 2)) { 1748 trace_xe_sched_job_ban(job); 1749 ban = true; 1750 } 1751 } else if (xe_exec_queue_is_lr(q) && 1752 !xe_lrc_ring_is_idle(q->lrc[0])) { 1753 ban = true; 1754 } 1755 1756 if (ban) { 1757 set_exec_queue_banned(q); 1758 xe_guc_exec_queue_trigger_cleanup(q); 1759 } 1760 } 1761 } 1762 1763 int xe_guc_submit_reset_prepare(struct xe_guc *guc) 1764 { 1765 int ret; 1766 1767 if (!guc->submission_state.initialized) 1768 return 0; 1769 1770 /* 1771 * Using an atomic here rather than submission_state.lock as this 1772 * function can be called while holding the CT lock (engine reset 1773 * failure). submission_state.lock needs the CT lock to resubmit jobs. 1774 * Atomic is not ideal, but it works to prevent against concurrent reset 1775 * and releasing any TDRs waiting on guc->submission_state.stopped. 1776 */ 1777 ret = atomic_fetch_or(1, &guc->submission_state.stopped); 1778 smp_wmb(); 1779 wake_up_all(&guc->ct.wq); 1780 1781 return ret; 1782 } 1783 1784 void xe_guc_submit_reset_wait(struct xe_guc *guc) 1785 { 1786 wait_event(guc->ct.wq, xe_device_wedged(guc_to_xe(guc)) || 1787 !xe_guc_read_stopped(guc)); 1788 } 1789 1790 void xe_guc_submit_stop(struct xe_guc *guc) 1791 { 1792 struct xe_exec_queue *q; 1793 unsigned long index; 1794 1795 xe_gt_assert(guc_to_gt(guc), xe_guc_read_stopped(guc) == 1); 1796 1797 mutex_lock(&guc->submission_state.lock); 1798 1799 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) { 1800 /* Prevent redundant attempts to stop parallel queues */ 1801 if (q->guc->id != index) 1802 continue; 1803 1804 guc_exec_queue_stop(guc, q); 1805 } 1806 1807 mutex_unlock(&guc->submission_state.lock); 1808 1809 /* 1810 * No one can enter the backend at this point, aside from new engine 1811 * creation which is protected by guc->submission_state.lock. 1812 */ 1813 1814 } 1815 1816 static void guc_exec_queue_start(struct xe_exec_queue *q) 1817 { 1818 struct xe_gpu_scheduler *sched = &q->guc->sched; 1819 1820 if (!exec_queue_killed_or_banned_or_wedged(q)) { 1821 int i; 1822 1823 trace_xe_exec_queue_resubmit(q); 1824 for (i = 0; i < q->width; ++i) 1825 xe_lrc_set_ring_head(q->lrc[i], q->lrc[i]->ring.tail); 1826 xe_sched_resubmit_jobs(sched); 1827 } 1828 1829 xe_sched_submission_start(sched); 1830 xe_sched_submission_resume_tdr(sched); 1831 } 1832 1833 int xe_guc_submit_start(struct xe_guc *guc) 1834 { 1835 struct xe_exec_queue *q; 1836 unsigned long index; 1837 1838 xe_gt_assert(guc_to_gt(guc), xe_guc_read_stopped(guc) == 1); 1839 1840 mutex_lock(&guc->submission_state.lock); 1841 atomic_dec(&guc->submission_state.stopped); 1842 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) { 1843 /* Prevent redundant attempts to start parallel queues */ 1844 if (q->guc->id != index) 1845 continue; 1846 1847 guc_exec_queue_start(q); 1848 } 1849 mutex_unlock(&guc->submission_state.lock); 1850 1851 wake_up_all(&guc->ct.wq); 1852 1853 return 0; 1854 } 1855 1856 static struct xe_exec_queue * 1857 g2h_exec_queue_lookup(struct xe_guc *guc, u32 guc_id) 1858 { 1859 struct xe_gt *gt = guc_to_gt(guc); 1860 struct xe_exec_queue *q; 1861 1862 if (unlikely(guc_id >= GUC_ID_MAX)) { 1863 xe_gt_err(gt, "Invalid guc_id %u\n", guc_id); 1864 return NULL; 1865 } 1866 1867 q = xa_load(&guc->submission_state.exec_queue_lookup, guc_id); 1868 if (unlikely(!q)) { 1869 xe_gt_err(gt, "Not engine present for guc_id %u\n", guc_id); 1870 return NULL; 1871 } 1872 1873 xe_gt_assert(guc_to_gt(guc), guc_id >= q->guc->id); 1874 xe_gt_assert(guc_to_gt(guc), guc_id < (q->guc->id + q->width)); 1875 1876 return q; 1877 } 1878 1879 static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q) 1880 { 1881 u32 action[] = { 1882 XE_GUC_ACTION_DEREGISTER_CONTEXT, 1883 q->guc->id, 1884 }; 1885 1886 xe_gt_assert(guc_to_gt(guc), exec_queue_destroyed(q)); 1887 xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q)); 1888 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q)); 1889 xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q)); 1890 1891 trace_xe_exec_queue_deregister(q); 1892 1893 xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action)); 1894 } 1895 1896 static void handle_sched_done(struct xe_guc *guc, struct xe_exec_queue *q, 1897 u32 runnable_state) 1898 { 1899 trace_xe_exec_queue_scheduling_done(q); 1900 1901 if (runnable_state == 1) { 1902 xe_gt_assert(guc_to_gt(guc), exec_queue_pending_enable(q)); 1903 1904 q->guc->resume_time = ktime_get(); 1905 clear_exec_queue_pending_enable(q); 1906 smp_wmb(); 1907 wake_up_all(&guc->ct.wq); 1908 } else { 1909 bool check_timeout = exec_queue_check_timeout(q); 1910 1911 xe_gt_assert(guc_to_gt(guc), runnable_state == 0); 1912 xe_gt_assert(guc_to_gt(guc), exec_queue_pending_disable(q)); 1913 1914 if (q->guc->suspend_pending) { 1915 suspend_fence_signal(q); 1916 clear_exec_queue_pending_disable(q); 1917 } else { 1918 if (exec_queue_banned(q) || check_timeout) { 1919 smp_wmb(); 1920 wake_up_all(&guc->ct.wq); 1921 } 1922 if (!check_timeout && exec_queue_destroyed(q)) { 1923 /* 1924 * Make sure to clear the pending_disable only 1925 * after sampling the destroyed state. We want 1926 * to ensure we don't trigger the unregister too 1927 * early with something intending to only 1928 * disable scheduling. The caller doing the 1929 * destroy must wait for an ongoing 1930 * pending_disable before marking as destroyed. 1931 */ 1932 clear_exec_queue_pending_disable(q); 1933 deregister_exec_queue(guc, q); 1934 } else { 1935 clear_exec_queue_pending_disable(q); 1936 } 1937 } 1938 } 1939 } 1940 1941 int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len) 1942 { 1943 struct xe_exec_queue *q; 1944 u32 guc_id, runnable_state; 1945 1946 if (unlikely(len < 2)) 1947 return -EPROTO; 1948 1949 guc_id = msg[0]; 1950 runnable_state = msg[1]; 1951 1952 q = g2h_exec_queue_lookup(guc, guc_id); 1953 if (unlikely(!q)) 1954 return -EPROTO; 1955 1956 if (unlikely(!exec_queue_pending_enable(q) && 1957 !exec_queue_pending_disable(q))) { 1958 xe_gt_err(guc_to_gt(guc), 1959 "SCHED_DONE: Unexpected engine state 0x%04x, guc_id=%d, runnable_state=%u", 1960 atomic_read(&q->guc->state), q->guc->id, 1961 runnable_state); 1962 return -EPROTO; 1963 } 1964 1965 handle_sched_done(guc, q, runnable_state); 1966 1967 return 0; 1968 } 1969 1970 static void handle_deregister_done(struct xe_guc *guc, struct xe_exec_queue *q) 1971 { 1972 trace_xe_exec_queue_deregister_done(q); 1973 1974 clear_exec_queue_registered(q); 1975 1976 if (exec_queue_extra_ref(q) || xe_exec_queue_is_lr(q)) 1977 xe_exec_queue_put(q); 1978 else 1979 __guc_exec_queue_fini(guc, q); 1980 } 1981 1982 int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len) 1983 { 1984 struct xe_exec_queue *q; 1985 u32 guc_id; 1986 1987 if (unlikely(len < 1)) 1988 return -EPROTO; 1989 1990 guc_id = msg[0]; 1991 1992 q = g2h_exec_queue_lookup(guc, guc_id); 1993 if (unlikely(!q)) 1994 return -EPROTO; 1995 1996 if (!exec_queue_destroyed(q) || exec_queue_pending_disable(q) || 1997 exec_queue_pending_enable(q) || exec_queue_enabled(q)) { 1998 xe_gt_err(guc_to_gt(guc), 1999 "DEREGISTER_DONE: Unexpected engine state 0x%04x, guc_id=%d", 2000 atomic_read(&q->guc->state), q->guc->id); 2001 return -EPROTO; 2002 } 2003 2004 handle_deregister_done(guc, q); 2005 2006 return 0; 2007 } 2008 2009 int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) 2010 { 2011 struct xe_gt *gt = guc_to_gt(guc); 2012 struct xe_exec_queue *q; 2013 u32 guc_id; 2014 2015 if (unlikely(len < 1)) 2016 return -EPROTO; 2017 2018 guc_id = msg[0]; 2019 2020 q = g2h_exec_queue_lookup(guc, guc_id); 2021 if (unlikely(!q)) 2022 return -EPROTO; 2023 2024 xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: 0x%x, guc_id=%d", 2025 xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id); 2026 2027 trace_xe_exec_queue_reset(q); 2028 2029 /* 2030 * A banned engine is a NOP at this point (came from 2031 * guc_exec_queue_timedout_job). Otherwise, kick drm scheduler to cancel 2032 * jobs by setting timeout of the job to the minimum value kicking 2033 * guc_exec_queue_timedout_job. 2034 */ 2035 set_exec_queue_reset(q); 2036 if (!exec_queue_banned(q) && !exec_queue_check_timeout(q)) 2037 xe_guc_exec_queue_trigger_cleanup(q); 2038 2039 return 0; 2040 } 2041 2042 /* 2043 * xe_guc_error_capture_handler - Handler of GuC captured message 2044 * @guc: The GuC object 2045 * @msg: Point to the message 2046 * @len: The message length 2047 * 2048 * When GuC captured data is ready, GuC will send message 2049 * XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION to host, this function will be 2050 * called 1st to check status before process the data comes with the message. 2051 * 2052 * Returns: error code. 0 if success 2053 */ 2054 int xe_guc_error_capture_handler(struct xe_guc *guc, u32 *msg, u32 len) 2055 { 2056 u32 status; 2057 2058 if (unlikely(len != XE_GUC_ACTION_STATE_CAPTURE_NOTIFICATION_DATA_LEN)) 2059 return -EPROTO; 2060 2061 status = msg[0] & XE_GUC_STATE_CAPTURE_EVENT_STATUS_MASK; 2062 if (status == XE_GUC_STATE_CAPTURE_EVENT_STATUS_NOSPACE) 2063 xe_gt_warn(guc_to_gt(guc), "G2H-Error capture no space"); 2064 2065 xe_guc_capture_process(guc); 2066 2067 return 0; 2068 } 2069 2070 int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, 2071 u32 len) 2072 { 2073 struct xe_gt *gt = guc_to_gt(guc); 2074 struct xe_exec_queue *q; 2075 u32 guc_id; 2076 2077 if (unlikely(len < 1)) 2078 return -EPROTO; 2079 2080 guc_id = msg[0]; 2081 2082 if (guc_id == GUC_ID_UNKNOWN) { 2083 /* 2084 * GuC uses GUC_ID_UNKNOWN if it can not map the CAT fault to any PF/VF 2085 * context. In such case only PF will be notified about that fault. 2086 */ 2087 xe_gt_err_ratelimited(gt, "Memory CAT error reported by GuC!\n"); 2088 return 0; 2089 } 2090 2091 q = g2h_exec_queue_lookup(guc, guc_id); 2092 if (unlikely(!q)) 2093 return -EPROTO; 2094 2095 xe_gt_dbg(gt, "Engine memory cat error: engine_class=%s, logical_mask: 0x%x, guc_id=%d", 2096 xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id); 2097 2098 trace_xe_exec_queue_memory_cat_error(q); 2099 2100 /* Treat the same as engine reset */ 2101 set_exec_queue_reset(q); 2102 if (!exec_queue_banned(q) && !exec_queue_check_timeout(q)) 2103 xe_guc_exec_queue_trigger_cleanup(q); 2104 2105 return 0; 2106 } 2107 2108 int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len) 2109 { 2110 struct xe_gt *gt = guc_to_gt(guc); 2111 u8 guc_class, instance; 2112 u32 reason; 2113 2114 if (unlikely(len != 3)) 2115 return -EPROTO; 2116 2117 guc_class = msg[0]; 2118 instance = msg[1]; 2119 reason = msg[2]; 2120 2121 /* Unexpected failure of a hardware feature, log an actual error */ 2122 xe_gt_err(gt, "GuC engine reset request failed on %d:%d because 0x%08X", 2123 guc_class, instance, reason); 2124 2125 xe_gt_reset_async(gt); 2126 2127 return 0; 2128 } 2129 2130 static void 2131 guc_exec_queue_wq_snapshot_capture(struct xe_exec_queue *q, 2132 struct xe_guc_submit_exec_queue_snapshot *snapshot) 2133 { 2134 struct xe_guc *guc = exec_queue_to_guc(q); 2135 struct xe_device *xe = guc_to_xe(guc); 2136 struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]); 2137 int i; 2138 2139 snapshot->guc.wqi_head = q->guc->wqi_head; 2140 snapshot->guc.wqi_tail = q->guc->wqi_tail; 2141 snapshot->parallel.wq_desc.head = parallel_read(xe, map, wq_desc.head); 2142 snapshot->parallel.wq_desc.tail = parallel_read(xe, map, wq_desc.tail); 2143 snapshot->parallel.wq_desc.status = parallel_read(xe, map, 2144 wq_desc.wq_status); 2145 2146 if (snapshot->parallel.wq_desc.head != 2147 snapshot->parallel.wq_desc.tail) { 2148 for (i = snapshot->parallel.wq_desc.head; 2149 i != snapshot->parallel.wq_desc.tail; 2150 i = (i + sizeof(u32)) % WQ_SIZE) 2151 snapshot->parallel.wq[i / sizeof(u32)] = 2152 parallel_read(xe, map, wq[i / sizeof(u32)]); 2153 } 2154 } 2155 2156 static void 2157 guc_exec_queue_wq_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, 2158 struct drm_printer *p) 2159 { 2160 int i; 2161 2162 drm_printf(p, "\tWQ head: %u (internal), %d (memory)\n", 2163 snapshot->guc.wqi_head, snapshot->parallel.wq_desc.head); 2164 drm_printf(p, "\tWQ tail: %u (internal), %d (memory)\n", 2165 snapshot->guc.wqi_tail, snapshot->parallel.wq_desc.tail); 2166 drm_printf(p, "\tWQ status: %u\n", snapshot->parallel.wq_desc.status); 2167 2168 if (snapshot->parallel.wq_desc.head != 2169 snapshot->parallel.wq_desc.tail) { 2170 for (i = snapshot->parallel.wq_desc.head; 2171 i != snapshot->parallel.wq_desc.tail; 2172 i = (i + sizeof(u32)) % WQ_SIZE) 2173 drm_printf(p, "\tWQ[%zu]: 0x%08x\n", i / sizeof(u32), 2174 snapshot->parallel.wq[i / sizeof(u32)]); 2175 } 2176 } 2177 2178 /** 2179 * xe_guc_exec_queue_snapshot_capture - Take a quick snapshot of the GuC Engine. 2180 * @q: faulty exec queue 2181 * 2182 * This can be printed out in a later stage like during dev_coredump 2183 * analysis. 2184 * 2185 * Returns: a GuC Submit Engine snapshot object that must be freed by the 2186 * caller, using `xe_guc_exec_queue_snapshot_free`. 2187 */ 2188 struct xe_guc_submit_exec_queue_snapshot * 2189 xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q) 2190 { 2191 struct xe_gpu_scheduler *sched = &q->guc->sched; 2192 struct xe_guc_submit_exec_queue_snapshot *snapshot; 2193 int i; 2194 2195 snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); 2196 2197 if (!snapshot) 2198 return NULL; 2199 2200 snapshot->guc.id = q->guc->id; 2201 memcpy(&snapshot->name, &q->name, sizeof(snapshot->name)); 2202 snapshot->class = q->class; 2203 snapshot->logical_mask = q->logical_mask; 2204 snapshot->width = q->width; 2205 snapshot->refcount = kref_read(&q->refcount); 2206 snapshot->sched_timeout = sched->base.timeout; 2207 snapshot->sched_props.timeslice_us = q->sched_props.timeslice_us; 2208 snapshot->sched_props.preempt_timeout_us = 2209 q->sched_props.preempt_timeout_us; 2210 2211 snapshot->lrc = kmalloc_array(q->width, sizeof(struct xe_lrc_snapshot *), 2212 GFP_ATOMIC); 2213 2214 if (snapshot->lrc) { 2215 for (i = 0; i < q->width; ++i) { 2216 struct xe_lrc *lrc = q->lrc[i]; 2217 2218 snapshot->lrc[i] = xe_lrc_snapshot_capture(lrc); 2219 } 2220 } 2221 2222 snapshot->schedule_state = atomic_read(&q->guc->state); 2223 snapshot->exec_queue_flags = q->flags; 2224 2225 snapshot->parallel_execution = xe_exec_queue_is_parallel(q); 2226 if (snapshot->parallel_execution) 2227 guc_exec_queue_wq_snapshot_capture(q, snapshot); 2228 2229 spin_lock(&sched->base.job_list_lock); 2230 snapshot->pending_list_size = list_count_nodes(&sched->base.pending_list); 2231 snapshot->pending_list = kmalloc_array(snapshot->pending_list_size, 2232 sizeof(struct pending_list_snapshot), 2233 GFP_ATOMIC); 2234 2235 if (snapshot->pending_list) { 2236 struct xe_sched_job *job_iter; 2237 2238 i = 0; 2239 list_for_each_entry(job_iter, &sched->base.pending_list, drm.list) { 2240 snapshot->pending_list[i].seqno = 2241 xe_sched_job_seqno(job_iter); 2242 snapshot->pending_list[i].fence = 2243 dma_fence_is_signaled(job_iter->fence) ? 1 : 0; 2244 snapshot->pending_list[i].finished = 2245 dma_fence_is_signaled(&job_iter->drm.s_fence->finished) 2246 ? 1 : 0; 2247 i++; 2248 } 2249 } 2250 2251 spin_unlock(&sched->base.job_list_lock); 2252 2253 return snapshot; 2254 } 2255 2256 /** 2257 * xe_guc_exec_queue_snapshot_capture_delayed - Take delayed part of snapshot of the GuC Engine. 2258 * @snapshot: Previously captured snapshot of job. 2259 * 2260 * This captures some data that requires taking some locks, so it cannot be done in signaling path. 2261 */ 2262 void 2263 xe_guc_exec_queue_snapshot_capture_delayed(struct xe_guc_submit_exec_queue_snapshot *snapshot) 2264 { 2265 int i; 2266 2267 if (!snapshot || !snapshot->lrc) 2268 return; 2269 2270 for (i = 0; i < snapshot->width; ++i) 2271 xe_lrc_snapshot_capture_delayed(snapshot->lrc[i]); 2272 } 2273 2274 /** 2275 * xe_guc_exec_queue_snapshot_print - Print out a given GuC Engine snapshot. 2276 * @snapshot: GuC Submit Engine snapshot object. 2277 * @p: drm_printer where it will be printed out. 2278 * 2279 * This function prints out a given GuC Submit Engine snapshot object. 2280 */ 2281 void 2282 xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, 2283 struct drm_printer *p) 2284 { 2285 int i; 2286 2287 if (!snapshot) 2288 return; 2289 2290 drm_printf(p, "GuC ID: %d\n", snapshot->guc.id); 2291 drm_printf(p, "\tName: %s\n", snapshot->name); 2292 drm_printf(p, "\tClass: %d\n", snapshot->class); 2293 drm_printf(p, "\tLogical mask: 0x%x\n", snapshot->logical_mask); 2294 drm_printf(p, "\tWidth: %d\n", snapshot->width); 2295 drm_printf(p, "\tRef: %d\n", snapshot->refcount); 2296 drm_printf(p, "\tTimeout: %ld (ms)\n", snapshot->sched_timeout); 2297 drm_printf(p, "\tTimeslice: %u (us)\n", 2298 snapshot->sched_props.timeslice_us); 2299 drm_printf(p, "\tPreempt timeout: %u (us)\n", 2300 snapshot->sched_props.preempt_timeout_us); 2301 2302 for (i = 0; snapshot->lrc && i < snapshot->width; ++i) 2303 xe_lrc_snapshot_print(snapshot->lrc[i], p); 2304 2305 drm_printf(p, "\tSchedule State: 0x%x\n", snapshot->schedule_state); 2306 drm_printf(p, "\tFlags: 0x%lx\n", snapshot->exec_queue_flags); 2307 2308 if (snapshot->parallel_execution) 2309 guc_exec_queue_wq_snapshot_print(snapshot, p); 2310 2311 for (i = 0; snapshot->pending_list && i < snapshot->pending_list_size; 2312 i++) 2313 drm_printf(p, "\tJob: seqno=%d, fence=%d, finished=%d\n", 2314 snapshot->pending_list[i].seqno, 2315 snapshot->pending_list[i].fence, 2316 snapshot->pending_list[i].finished); 2317 } 2318 2319 /** 2320 * xe_guc_exec_queue_snapshot_free - Free all allocated objects for a given 2321 * snapshot. 2322 * @snapshot: GuC Submit Engine snapshot object. 2323 * 2324 * This function free all the memory that needed to be allocated at capture 2325 * time. 2326 */ 2327 void xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot) 2328 { 2329 int i; 2330 2331 if (!snapshot) 2332 return; 2333 2334 if (snapshot->lrc) { 2335 for (i = 0; i < snapshot->width; i++) 2336 xe_lrc_snapshot_free(snapshot->lrc[i]); 2337 kfree(snapshot->lrc); 2338 } 2339 kfree(snapshot->pending_list); 2340 kfree(snapshot); 2341 } 2342 2343 static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p) 2344 { 2345 struct xe_guc_submit_exec_queue_snapshot *snapshot; 2346 2347 snapshot = xe_guc_exec_queue_snapshot_capture(q); 2348 xe_guc_exec_queue_snapshot_print(snapshot, p); 2349 xe_guc_exec_queue_snapshot_free(snapshot); 2350 } 2351 2352 /** 2353 * xe_guc_submit_print - GuC Submit Print. 2354 * @guc: GuC. 2355 * @p: drm_printer where it will be printed out. 2356 * 2357 * This function capture and prints snapshots of **all** GuC Engines. 2358 */ 2359 void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p) 2360 { 2361 struct xe_exec_queue *q; 2362 unsigned long index; 2363 2364 if (!xe_device_uc_enabled(guc_to_xe(guc))) 2365 return; 2366 2367 mutex_lock(&guc->submission_state.lock); 2368 xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) 2369 guc_exec_queue_print(q, p); 2370 mutex_unlock(&guc->submission_state.lock); 2371 } 2372