xref: /linux/drivers/gpu/drm/xe/xe_guc_submit.c (revision 5c2e7736e20d9b348a44cafbfa639fe2653fbc34)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #include "xe_guc_submit.h"
7 
8 #include <linux/bitfield.h>
9 #include <linux/bitmap.h>
10 #include <linux/circ_buf.h>
11 #include <linux/delay.h>
12 #include <linux/dma-fence-array.h>
13 #include <linux/math64.h>
14 
15 #include <drm/drm_managed.h>
16 
17 #include "abi/guc_actions_abi.h"
18 #include "abi/guc_klvs_abi.h"
19 #include "regs/xe_lrc_layout.h"
20 #include "xe_assert.h"
21 #include "xe_devcoredump.h"
22 #include "xe_device.h"
23 #include "xe_exec_queue.h"
24 #include "xe_force_wake.h"
25 #include "xe_gpu_scheduler.h"
26 #include "xe_gt.h"
27 #include "xe_gt_clock.h"
28 #include "xe_gt_printk.h"
29 #include "xe_guc.h"
30 #include "xe_guc_ct.h"
31 #include "xe_guc_exec_queue_types.h"
32 #include "xe_guc_id_mgr.h"
33 #include "xe_guc_submit_types.h"
34 #include "xe_hw_engine.h"
35 #include "xe_hw_fence.h"
36 #include "xe_lrc.h"
37 #include "xe_macros.h"
38 #include "xe_map.h"
39 #include "xe_mocs.h"
40 #include "xe_pm.h"
41 #include "xe_ring_ops_types.h"
42 #include "xe_sched_job.h"
43 #include "xe_trace.h"
44 #include "xe_vm.h"
45 
46 static struct xe_guc *
47 exec_queue_to_guc(struct xe_exec_queue *q)
48 {
49 	return &q->gt->uc.guc;
50 }
51 
52 /*
53  * Helpers for engine state, using an atomic as some of the bits can transition
54  * as the same time (e.g. a suspend can be happning at the same time as schedule
55  * engine done being processed).
56  */
57 #define EXEC_QUEUE_STATE_REGISTERED		(1 << 0)
58 #define EXEC_QUEUE_STATE_ENABLED		(1 << 1)
59 #define EXEC_QUEUE_STATE_PENDING_ENABLE		(1 << 2)
60 #define EXEC_QUEUE_STATE_PENDING_DISABLE	(1 << 3)
61 #define EXEC_QUEUE_STATE_DESTROYED		(1 << 4)
62 #define EXEC_QUEUE_STATE_SUSPENDED		(1 << 5)
63 #define EXEC_QUEUE_STATE_RESET			(1 << 6)
64 #define EXEC_QUEUE_STATE_KILLED			(1 << 7)
65 #define EXEC_QUEUE_STATE_WEDGED			(1 << 8)
66 #define EXEC_QUEUE_STATE_BANNED			(1 << 9)
67 #define EXEC_QUEUE_STATE_CHECK_TIMEOUT		(1 << 10)
68 #define EXEC_QUEUE_STATE_EXTRA_REF		(1 << 11)
69 
70 static bool exec_queue_registered(struct xe_exec_queue *q)
71 {
72 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_REGISTERED;
73 }
74 
75 static void set_exec_queue_registered(struct xe_exec_queue *q)
76 {
77 	atomic_or(EXEC_QUEUE_STATE_REGISTERED, &q->guc->state);
78 }
79 
80 static void clear_exec_queue_registered(struct xe_exec_queue *q)
81 {
82 	atomic_and(~EXEC_QUEUE_STATE_REGISTERED, &q->guc->state);
83 }
84 
85 static bool exec_queue_enabled(struct xe_exec_queue *q)
86 {
87 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_ENABLED;
88 }
89 
90 static void set_exec_queue_enabled(struct xe_exec_queue *q)
91 {
92 	atomic_or(EXEC_QUEUE_STATE_ENABLED, &q->guc->state);
93 }
94 
95 static void clear_exec_queue_enabled(struct xe_exec_queue *q)
96 {
97 	atomic_and(~EXEC_QUEUE_STATE_ENABLED, &q->guc->state);
98 }
99 
100 static bool exec_queue_pending_enable(struct xe_exec_queue *q)
101 {
102 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_ENABLE;
103 }
104 
105 static void set_exec_queue_pending_enable(struct xe_exec_queue *q)
106 {
107 	atomic_or(EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state);
108 }
109 
110 static void clear_exec_queue_pending_enable(struct xe_exec_queue *q)
111 {
112 	atomic_and(~EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state);
113 }
114 
115 static bool exec_queue_pending_disable(struct xe_exec_queue *q)
116 {
117 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_DISABLE;
118 }
119 
120 static void set_exec_queue_pending_disable(struct xe_exec_queue *q)
121 {
122 	atomic_or(EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state);
123 }
124 
125 static void clear_exec_queue_pending_disable(struct xe_exec_queue *q)
126 {
127 	atomic_and(~EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state);
128 }
129 
130 static bool exec_queue_destroyed(struct xe_exec_queue *q)
131 {
132 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_DESTROYED;
133 }
134 
135 static void set_exec_queue_destroyed(struct xe_exec_queue *q)
136 {
137 	atomic_or(EXEC_QUEUE_STATE_DESTROYED, &q->guc->state);
138 }
139 
140 static bool exec_queue_banned(struct xe_exec_queue *q)
141 {
142 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_BANNED;
143 }
144 
145 static void set_exec_queue_banned(struct xe_exec_queue *q)
146 {
147 	atomic_or(EXEC_QUEUE_STATE_BANNED, &q->guc->state);
148 }
149 
150 static bool exec_queue_suspended(struct xe_exec_queue *q)
151 {
152 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_SUSPENDED;
153 }
154 
155 static void set_exec_queue_suspended(struct xe_exec_queue *q)
156 {
157 	atomic_or(EXEC_QUEUE_STATE_SUSPENDED, &q->guc->state);
158 }
159 
160 static void clear_exec_queue_suspended(struct xe_exec_queue *q)
161 {
162 	atomic_and(~EXEC_QUEUE_STATE_SUSPENDED, &q->guc->state);
163 }
164 
165 static bool exec_queue_reset(struct xe_exec_queue *q)
166 {
167 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_RESET;
168 }
169 
170 static void set_exec_queue_reset(struct xe_exec_queue *q)
171 {
172 	atomic_or(EXEC_QUEUE_STATE_RESET, &q->guc->state);
173 }
174 
175 static bool exec_queue_killed(struct xe_exec_queue *q)
176 {
177 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_KILLED;
178 }
179 
180 static void set_exec_queue_killed(struct xe_exec_queue *q)
181 {
182 	atomic_or(EXEC_QUEUE_STATE_KILLED, &q->guc->state);
183 }
184 
185 static bool exec_queue_wedged(struct xe_exec_queue *q)
186 {
187 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_WEDGED;
188 }
189 
190 static void set_exec_queue_wedged(struct xe_exec_queue *q)
191 {
192 	atomic_or(EXEC_QUEUE_STATE_WEDGED, &q->guc->state);
193 }
194 
195 static bool exec_queue_check_timeout(struct xe_exec_queue *q)
196 {
197 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_CHECK_TIMEOUT;
198 }
199 
200 static void set_exec_queue_check_timeout(struct xe_exec_queue *q)
201 {
202 	atomic_or(EXEC_QUEUE_STATE_CHECK_TIMEOUT, &q->guc->state);
203 }
204 
205 static void clear_exec_queue_check_timeout(struct xe_exec_queue *q)
206 {
207 	atomic_and(~EXEC_QUEUE_STATE_CHECK_TIMEOUT, &q->guc->state);
208 }
209 
210 static bool exec_queue_extra_ref(struct xe_exec_queue *q)
211 {
212 	return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_EXTRA_REF;
213 }
214 
215 static void set_exec_queue_extra_ref(struct xe_exec_queue *q)
216 {
217 	atomic_or(EXEC_QUEUE_STATE_EXTRA_REF, &q->guc->state);
218 }
219 
220 static bool exec_queue_killed_or_banned_or_wedged(struct xe_exec_queue *q)
221 {
222 	return (atomic_read(&q->guc->state) &
223 		(EXEC_QUEUE_STATE_WEDGED | EXEC_QUEUE_STATE_KILLED |
224 		 EXEC_QUEUE_STATE_BANNED));
225 }
226 
227 #ifdef CONFIG_PROVE_LOCKING
228 static int alloc_submit_wq(struct xe_guc *guc)
229 {
230 	int i;
231 
232 	for (i = 0; i < NUM_SUBMIT_WQ; ++i) {
233 		guc->submission_state.submit_wq_pool[i] =
234 			alloc_ordered_workqueue("submit_wq", 0);
235 		if (!guc->submission_state.submit_wq_pool[i])
236 			goto err_free;
237 	}
238 
239 	return 0;
240 
241 err_free:
242 	while (i)
243 		destroy_workqueue(guc->submission_state.submit_wq_pool[--i]);
244 
245 	return -ENOMEM;
246 }
247 
248 static void free_submit_wq(struct xe_guc *guc)
249 {
250 	int i;
251 
252 	for (i = 0; i < NUM_SUBMIT_WQ; ++i)
253 		destroy_workqueue(guc->submission_state.submit_wq_pool[i]);
254 }
255 
256 static struct workqueue_struct *get_submit_wq(struct xe_guc *guc)
257 {
258 	int idx = guc->submission_state.submit_wq_idx++ % NUM_SUBMIT_WQ;
259 
260 	return guc->submission_state.submit_wq_pool[idx];
261 }
262 #else
263 static int alloc_submit_wq(struct xe_guc *guc)
264 {
265 	return 0;
266 }
267 
268 static void free_submit_wq(struct xe_guc *guc)
269 {
270 
271 }
272 
273 static struct workqueue_struct *get_submit_wq(struct xe_guc *guc)
274 {
275 	return NULL;
276 }
277 #endif
278 
279 static void xe_guc_submit_fini(struct xe_guc *guc)
280 {
281 	struct xe_device *xe = guc_to_xe(guc);
282 	struct xe_gt *gt = guc_to_gt(guc);
283 	int ret;
284 
285 	ret = wait_event_timeout(guc->submission_state.fini_wq,
286 				 xa_empty(&guc->submission_state.exec_queue_lookup),
287 				 HZ * 5);
288 
289 	drain_workqueue(xe->destroy_wq);
290 
291 	xe_gt_assert(gt, ret);
292 }
293 
294 static void guc_submit_fini(struct drm_device *drm, void *arg)
295 {
296 	struct xe_guc *guc = arg;
297 
298 	xe_guc_submit_fini(guc);
299 	xa_destroy(&guc->submission_state.exec_queue_lookup);
300 	free_submit_wq(guc);
301 }
302 
303 static void guc_submit_wedged_fini(void *arg)
304 {
305 	struct xe_guc *guc = arg;
306 	struct xe_exec_queue *q;
307 	unsigned long index;
308 
309 	mutex_lock(&guc->submission_state.lock);
310 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) {
311 		if (exec_queue_wedged(q)) {
312 			mutex_unlock(&guc->submission_state.lock);
313 			xe_exec_queue_put(q);
314 			mutex_lock(&guc->submission_state.lock);
315 		}
316 	}
317 	mutex_unlock(&guc->submission_state.lock);
318 }
319 
320 static const struct xe_exec_queue_ops guc_exec_queue_ops;
321 
322 static void primelockdep(struct xe_guc *guc)
323 {
324 	if (!IS_ENABLED(CONFIG_LOCKDEP))
325 		return;
326 
327 	fs_reclaim_acquire(GFP_KERNEL);
328 
329 	mutex_lock(&guc->submission_state.lock);
330 	mutex_unlock(&guc->submission_state.lock);
331 
332 	fs_reclaim_release(GFP_KERNEL);
333 }
334 
335 /**
336  * xe_guc_submit_init() - Initialize GuC submission.
337  * @guc: the &xe_guc to initialize
338  * @num_ids: number of GuC context IDs to use
339  *
340  * The bare-metal or PF driver can pass ~0 as &num_ids to indicate that all
341  * GuC context IDs supported by the GuC firmware should be used for submission.
342  *
343  * Only VF drivers will have to provide explicit number of GuC context IDs
344  * that they can use for submission.
345  *
346  * Return: 0 on success or a negative error code on failure.
347  */
348 int xe_guc_submit_init(struct xe_guc *guc, unsigned int num_ids)
349 {
350 	struct xe_device *xe = guc_to_xe(guc);
351 	struct xe_gt *gt = guc_to_gt(guc);
352 	int err;
353 
354 	err = drmm_mutex_init(&xe->drm, &guc->submission_state.lock);
355 	if (err)
356 		return err;
357 
358 	err = xe_guc_id_mgr_init(&guc->submission_state.idm, num_ids);
359 	if (err)
360 		return err;
361 
362 	err = alloc_submit_wq(guc);
363 	if (err)
364 		return err;
365 
366 	gt->exec_queue_ops = &guc_exec_queue_ops;
367 
368 	xa_init(&guc->submission_state.exec_queue_lookup);
369 
370 	init_waitqueue_head(&guc->submission_state.fini_wq);
371 
372 	primelockdep(guc);
373 
374 	return drmm_add_action_or_reset(&xe->drm, guc_submit_fini, guc);
375 }
376 
377 static void __release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q, u32 xa_count)
378 {
379 	int i;
380 
381 	lockdep_assert_held(&guc->submission_state.lock);
382 
383 	for (i = 0; i < xa_count; ++i)
384 		xa_erase(&guc->submission_state.exec_queue_lookup, q->guc->id + i);
385 
386 	xe_guc_id_mgr_release_locked(&guc->submission_state.idm,
387 				     q->guc->id, q->width);
388 
389 	if (xa_empty(&guc->submission_state.exec_queue_lookup))
390 		wake_up(&guc->submission_state.fini_wq);
391 }
392 
393 static int alloc_guc_id(struct xe_guc *guc, struct xe_exec_queue *q)
394 {
395 	int ret;
396 	void *ptr;
397 	int i;
398 
399 	/*
400 	 * Must use GFP_NOWAIT as this lock is in the dma fence signalling path,
401 	 * worse case user gets -ENOMEM on engine create and has to try again.
402 	 *
403 	 * FIXME: Have caller pre-alloc or post-alloc /w GFP_KERNEL to prevent
404 	 * failure.
405 	 */
406 	lockdep_assert_held(&guc->submission_state.lock);
407 
408 	ret = xe_guc_id_mgr_reserve_locked(&guc->submission_state.idm,
409 					   q->width);
410 	if (ret < 0)
411 		return ret;
412 
413 	q->guc->id = ret;
414 
415 	for (i = 0; i < q->width; ++i) {
416 		ptr = xa_store(&guc->submission_state.exec_queue_lookup,
417 			       q->guc->id + i, q, GFP_NOWAIT);
418 		if (IS_ERR(ptr)) {
419 			ret = PTR_ERR(ptr);
420 			goto err_release;
421 		}
422 	}
423 
424 	return 0;
425 
426 err_release:
427 	__release_guc_id(guc, q, i);
428 
429 	return ret;
430 }
431 
432 static void release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q)
433 {
434 	mutex_lock(&guc->submission_state.lock);
435 	__release_guc_id(guc, q, q->width);
436 	mutex_unlock(&guc->submission_state.lock);
437 }
438 
439 struct exec_queue_policy {
440 	u32 count;
441 	struct guc_update_exec_queue_policy h2g;
442 };
443 
444 static u32 __guc_exec_queue_policy_action_size(struct exec_queue_policy *policy)
445 {
446 	size_t bytes = sizeof(policy->h2g.header) +
447 		       (sizeof(policy->h2g.klv[0]) * policy->count);
448 
449 	return bytes / sizeof(u32);
450 }
451 
452 static void __guc_exec_queue_policy_start_klv(struct exec_queue_policy *policy,
453 					      u16 guc_id)
454 {
455 	policy->h2g.header.action =
456 		XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES;
457 	policy->h2g.header.guc_id = guc_id;
458 	policy->count = 0;
459 }
460 
461 #define MAKE_EXEC_QUEUE_POLICY_ADD(func, id) \
462 static void __guc_exec_queue_policy_add_##func(struct exec_queue_policy *policy, \
463 					   u32 data) \
464 { \
465 	XE_WARN_ON(policy->count >= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \
466 \
467 	policy->h2g.klv[policy->count].kl = \
468 		FIELD_PREP(GUC_KLV_0_KEY, \
469 			   GUC_CONTEXT_POLICIES_KLV_ID_##id) | \
470 		FIELD_PREP(GUC_KLV_0_LEN, 1); \
471 	policy->h2g.klv[policy->count].value = data; \
472 	policy->count++; \
473 }
474 
475 MAKE_EXEC_QUEUE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM)
476 MAKE_EXEC_QUEUE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT)
477 MAKE_EXEC_QUEUE_POLICY_ADD(priority, SCHEDULING_PRIORITY)
478 #undef MAKE_EXEC_QUEUE_POLICY_ADD
479 
480 static const int xe_exec_queue_prio_to_guc[] = {
481 	[XE_EXEC_QUEUE_PRIORITY_LOW] = GUC_CLIENT_PRIORITY_NORMAL,
482 	[XE_EXEC_QUEUE_PRIORITY_NORMAL] = GUC_CLIENT_PRIORITY_KMD_NORMAL,
483 	[XE_EXEC_QUEUE_PRIORITY_HIGH] = GUC_CLIENT_PRIORITY_HIGH,
484 	[XE_EXEC_QUEUE_PRIORITY_KERNEL] = GUC_CLIENT_PRIORITY_KMD_HIGH,
485 };
486 
487 static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q)
488 {
489 	struct exec_queue_policy policy;
490 	struct xe_device *xe = guc_to_xe(guc);
491 	enum xe_exec_queue_priority prio = q->sched_props.priority;
492 	u32 timeslice_us = q->sched_props.timeslice_us;
493 	u32 preempt_timeout_us = q->sched_props.preempt_timeout_us;
494 
495 	xe_assert(xe, exec_queue_registered(q));
496 
497 	__guc_exec_queue_policy_start_klv(&policy, q->guc->id);
498 	__guc_exec_queue_policy_add_priority(&policy, xe_exec_queue_prio_to_guc[prio]);
499 	__guc_exec_queue_policy_add_execution_quantum(&policy, timeslice_us);
500 	__guc_exec_queue_policy_add_preemption_timeout(&policy, preempt_timeout_us);
501 
502 	xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g,
503 		       __guc_exec_queue_policy_action_size(&policy), 0, 0);
504 }
505 
506 static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue *q)
507 {
508 	struct exec_queue_policy policy;
509 
510 	__guc_exec_queue_policy_start_klv(&policy, q->guc->id);
511 	__guc_exec_queue_policy_add_preemption_timeout(&policy, 1);
512 
513 	xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g,
514 		       __guc_exec_queue_policy_action_size(&policy), 0, 0);
515 }
516 
517 #define parallel_read(xe_, map_, field_) \
518 	xe_map_rd_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \
519 			field_)
520 #define parallel_write(xe_, map_, field_, val_) \
521 	xe_map_wr_field(xe_, &map_, 0, struct guc_submit_parallel_scratch, \
522 			field_, val_)
523 
524 static void __register_mlrc_exec_queue(struct xe_guc *guc,
525 				       struct xe_exec_queue *q,
526 				       struct guc_ctxt_registration_info *info)
527 {
528 #define MAX_MLRC_REG_SIZE      (13 + XE_HW_ENGINE_MAX_INSTANCE * 2)
529 	struct xe_device *xe = guc_to_xe(guc);
530 	u32 action[MAX_MLRC_REG_SIZE];
531 	int len = 0;
532 	int i;
533 
534 	xe_assert(xe, xe_exec_queue_is_parallel(q));
535 
536 	action[len++] = XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC;
537 	action[len++] = info->flags;
538 	action[len++] = info->context_idx;
539 	action[len++] = info->engine_class;
540 	action[len++] = info->engine_submit_mask;
541 	action[len++] = info->wq_desc_lo;
542 	action[len++] = info->wq_desc_hi;
543 	action[len++] = info->wq_base_lo;
544 	action[len++] = info->wq_base_hi;
545 	action[len++] = info->wq_size;
546 	action[len++] = q->width;
547 	action[len++] = info->hwlrca_lo;
548 	action[len++] = info->hwlrca_hi;
549 
550 	for (i = 1; i < q->width; ++i) {
551 		struct xe_lrc *lrc = q->lrc[i];
552 
553 		action[len++] = lower_32_bits(xe_lrc_descriptor(lrc));
554 		action[len++] = upper_32_bits(xe_lrc_descriptor(lrc));
555 	}
556 
557 	xe_assert(xe, len <= MAX_MLRC_REG_SIZE);
558 #undef MAX_MLRC_REG_SIZE
559 
560 	xe_guc_ct_send(&guc->ct, action, len, 0, 0);
561 }
562 
563 static void __register_exec_queue(struct xe_guc *guc,
564 				  struct guc_ctxt_registration_info *info)
565 {
566 	u32 action[] = {
567 		XE_GUC_ACTION_REGISTER_CONTEXT,
568 		info->flags,
569 		info->context_idx,
570 		info->engine_class,
571 		info->engine_submit_mask,
572 		info->wq_desc_lo,
573 		info->wq_desc_hi,
574 		info->wq_base_lo,
575 		info->wq_base_hi,
576 		info->wq_size,
577 		info->hwlrca_lo,
578 		info->hwlrca_hi,
579 	};
580 
581 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0);
582 }
583 
584 static void register_exec_queue(struct xe_exec_queue *q)
585 {
586 	struct xe_guc *guc = exec_queue_to_guc(q);
587 	struct xe_device *xe = guc_to_xe(guc);
588 	struct xe_lrc *lrc = q->lrc[0];
589 	struct guc_ctxt_registration_info info;
590 
591 	xe_assert(xe, !exec_queue_registered(q));
592 
593 	memset(&info, 0, sizeof(info));
594 	info.context_idx = q->guc->id;
595 	info.engine_class = xe_engine_class_to_guc_class(q->class);
596 	info.engine_submit_mask = q->logical_mask;
597 	info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc));
598 	info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc));
599 	info.flags = CONTEXT_REGISTRATION_FLAG_KMD;
600 
601 	if (xe_exec_queue_is_parallel(q)) {
602 		u64 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc);
603 		struct iosys_map map = xe_lrc_parallel_map(lrc);
604 
605 		info.wq_desc_lo = lower_32_bits(ggtt_addr +
606 			offsetof(struct guc_submit_parallel_scratch, wq_desc));
607 		info.wq_desc_hi = upper_32_bits(ggtt_addr +
608 			offsetof(struct guc_submit_parallel_scratch, wq_desc));
609 		info.wq_base_lo = lower_32_bits(ggtt_addr +
610 			offsetof(struct guc_submit_parallel_scratch, wq[0]));
611 		info.wq_base_hi = upper_32_bits(ggtt_addr +
612 			offsetof(struct guc_submit_parallel_scratch, wq[0]));
613 		info.wq_size = WQ_SIZE;
614 
615 		q->guc->wqi_head = 0;
616 		q->guc->wqi_tail = 0;
617 		xe_map_memset(xe, &map, 0, 0, PARALLEL_SCRATCH_SIZE - WQ_SIZE);
618 		parallel_write(xe, map, wq_desc.wq_status, WQ_STATUS_ACTIVE);
619 	}
620 
621 	/*
622 	 * We must keep a reference for LR engines if engine is registered with
623 	 * the GuC as jobs signal immediately and can't destroy an engine if the
624 	 * GuC has a reference to it.
625 	 */
626 	if (xe_exec_queue_is_lr(q))
627 		xe_exec_queue_get(q);
628 
629 	set_exec_queue_registered(q);
630 	trace_xe_exec_queue_register(q);
631 	if (xe_exec_queue_is_parallel(q))
632 		__register_mlrc_exec_queue(guc, q, &info);
633 	else
634 		__register_exec_queue(guc, &info);
635 	init_policies(guc, q);
636 }
637 
638 static u32 wq_space_until_wrap(struct xe_exec_queue *q)
639 {
640 	return (WQ_SIZE - q->guc->wqi_tail);
641 }
642 
643 static int wq_wait_for_space(struct xe_exec_queue *q, u32 wqi_size)
644 {
645 	struct xe_guc *guc = exec_queue_to_guc(q);
646 	struct xe_device *xe = guc_to_xe(guc);
647 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
648 	unsigned int sleep_period_ms = 1;
649 
650 #define AVAILABLE_SPACE \
651 	CIRC_SPACE(q->guc->wqi_tail, q->guc->wqi_head, WQ_SIZE)
652 	if (wqi_size > AVAILABLE_SPACE) {
653 try_again:
654 		q->guc->wqi_head = parallel_read(xe, map, wq_desc.head);
655 		if (wqi_size > AVAILABLE_SPACE) {
656 			if (sleep_period_ms == 1024) {
657 				xe_gt_reset_async(q->gt);
658 				return -ENODEV;
659 			}
660 
661 			msleep(sleep_period_ms);
662 			sleep_period_ms <<= 1;
663 			goto try_again;
664 		}
665 	}
666 #undef AVAILABLE_SPACE
667 
668 	return 0;
669 }
670 
671 static int wq_noop_append(struct xe_exec_queue *q)
672 {
673 	struct xe_guc *guc = exec_queue_to_guc(q);
674 	struct xe_device *xe = guc_to_xe(guc);
675 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
676 	u32 len_dw = wq_space_until_wrap(q) / sizeof(u32) - 1;
677 
678 	if (wq_wait_for_space(q, wq_space_until_wrap(q)))
679 		return -ENODEV;
680 
681 	xe_assert(xe, FIELD_FIT(WQ_LEN_MASK, len_dw));
682 
683 	parallel_write(xe, map, wq[q->guc->wqi_tail / sizeof(u32)],
684 		       FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_NOOP) |
685 		       FIELD_PREP(WQ_LEN_MASK, len_dw));
686 	q->guc->wqi_tail = 0;
687 
688 	return 0;
689 }
690 
691 static void wq_item_append(struct xe_exec_queue *q)
692 {
693 	struct xe_guc *guc = exec_queue_to_guc(q);
694 	struct xe_device *xe = guc_to_xe(guc);
695 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
696 #define WQ_HEADER_SIZE	4	/* Includes 1 LRC address too */
697 	u32 wqi[XE_HW_ENGINE_MAX_INSTANCE + (WQ_HEADER_SIZE - 1)];
698 	u32 wqi_size = (q->width + (WQ_HEADER_SIZE - 1)) * sizeof(u32);
699 	u32 len_dw = (wqi_size / sizeof(u32)) - 1;
700 	int i = 0, j;
701 
702 	if (wqi_size > wq_space_until_wrap(q)) {
703 		if (wq_noop_append(q))
704 			return;
705 	}
706 	if (wq_wait_for_space(q, wqi_size))
707 		return;
708 
709 	wqi[i++] = FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_MULTI_LRC) |
710 		FIELD_PREP(WQ_LEN_MASK, len_dw);
711 	wqi[i++] = xe_lrc_descriptor(q->lrc[0]);
712 	wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, q->guc->id) |
713 		FIELD_PREP(WQ_RING_TAIL_MASK, q->lrc[0]->ring.tail / sizeof(u64));
714 	wqi[i++] = 0;
715 	for (j = 1; j < q->width; ++j) {
716 		struct xe_lrc *lrc = q->lrc[j];
717 
718 		wqi[i++] = lrc->ring.tail / sizeof(u64);
719 	}
720 
721 	xe_assert(xe, i == wqi_size / sizeof(u32));
722 
723 	iosys_map_incr(&map, offsetof(struct guc_submit_parallel_scratch,
724 				      wq[q->guc->wqi_tail / sizeof(u32)]));
725 	xe_map_memcpy_to(xe, &map, 0, wqi, wqi_size);
726 	q->guc->wqi_tail += wqi_size;
727 	xe_assert(xe, q->guc->wqi_tail <= WQ_SIZE);
728 
729 	xe_device_wmb(xe);
730 
731 	map = xe_lrc_parallel_map(q->lrc[0]);
732 	parallel_write(xe, map, wq_desc.tail, q->guc->wqi_tail);
733 }
734 
735 #define RESUME_PENDING	~0x0ull
736 static void submit_exec_queue(struct xe_exec_queue *q)
737 {
738 	struct xe_guc *guc = exec_queue_to_guc(q);
739 	struct xe_device *xe = guc_to_xe(guc);
740 	struct xe_lrc *lrc = q->lrc[0];
741 	u32 action[3];
742 	u32 g2h_len = 0;
743 	u32 num_g2h = 0;
744 	int len = 0;
745 	bool extra_submit = false;
746 
747 	xe_assert(xe, exec_queue_registered(q));
748 
749 	if (xe_exec_queue_is_parallel(q))
750 		wq_item_append(q);
751 	else
752 		xe_lrc_set_ring_tail(lrc, lrc->ring.tail);
753 
754 	if (exec_queue_suspended(q) && !xe_exec_queue_is_parallel(q))
755 		return;
756 
757 	if (!exec_queue_enabled(q) && !exec_queue_suspended(q)) {
758 		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET;
759 		action[len++] = q->guc->id;
760 		action[len++] = GUC_CONTEXT_ENABLE;
761 		g2h_len = G2H_LEN_DW_SCHED_CONTEXT_MODE_SET;
762 		num_g2h = 1;
763 		if (xe_exec_queue_is_parallel(q))
764 			extra_submit = true;
765 
766 		q->guc->resume_time = RESUME_PENDING;
767 		set_exec_queue_pending_enable(q);
768 		set_exec_queue_enabled(q);
769 		trace_xe_exec_queue_scheduling_enable(q);
770 	} else {
771 		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT;
772 		action[len++] = q->guc->id;
773 		trace_xe_exec_queue_submit(q);
774 	}
775 
776 	xe_guc_ct_send(&guc->ct, action, len, g2h_len, num_g2h);
777 
778 	if (extra_submit) {
779 		len = 0;
780 		action[len++] = XE_GUC_ACTION_SCHED_CONTEXT;
781 		action[len++] = q->guc->id;
782 		trace_xe_exec_queue_submit(q);
783 
784 		xe_guc_ct_send(&guc->ct, action, len, 0, 0);
785 	}
786 }
787 
788 static struct dma_fence *
789 guc_exec_queue_run_job(struct drm_sched_job *drm_job)
790 {
791 	struct xe_sched_job *job = to_xe_sched_job(drm_job);
792 	struct xe_exec_queue *q = job->q;
793 	struct xe_guc *guc = exec_queue_to_guc(q);
794 	struct xe_device *xe = guc_to_xe(guc);
795 	bool lr = xe_exec_queue_is_lr(q);
796 
797 	xe_assert(xe, !(exec_queue_destroyed(q) || exec_queue_pending_disable(q)) ||
798 		  exec_queue_banned(q) || exec_queue_suspended(q));
799 
800 	trace_xe_sched_job_run(job);
801 
802 	if (!exec_queue_killed_or_banned_or_wedged(q) && !xe_sched_job_is_error(job)) {
803 		if (!exec_queue_registered(q))
804 			register_exec_queue(q);
805 		if (!lr)	/* LR jobs are emitted in the exec IOCTL */
806 			q->ring_ops->emit_job(job);
807 		submit_exec_queue(q);
808 	}
809 
810 	if (lr) {
811 		xe_sched_job_set_error(job, -EOPNOTSUPP);
812 		return NULL;
813 	} else if (test_and_set_bit(JOB_FLAG_SUBMIT, &job->fence->flags)) {
814 		return job->fence;
815 	} else {
816 		return dma_fence_get(job->fence);
817 	}
818 }
819 
820 static void guc_exec_queue_free_job(struct drm_sched_job *drm_job)
821 {
822 	struct xe_sched_job *job = to_xe_sched_job(drm_job);
823 
824 	xe_exec_queue_update_run_ticks(job->q);
825 
826 	trace_xe_sched_job_free(job);
827 	xe_sched_job_put(job);
828 }
829 
830 static int guc_read_stopped(struct xe_guc *guc)
831 {
832 	return atomic_read(&guc->submission_state.stopped);
833 }
834 
835 #define MAKE_SCHED_CONTEXT_ACTION(q, enable_disable)			\
836 	u32 action[] = {						\
837 		XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET,			\
838 		q->guc->id,						\
839 		GUC_CONTEXT_##enable_disable,				\
840 	}
841 
842 static void disable_scheduling_deregister(struct xe_guc *guc,
843 					  struct xe_exec_queue *q)
844 {
845 	MAKE_SCHED_CONTEXT_ACTION(q, DISABLE);
846 	struct xe_device *xe = guc_to_xe(guc);
847 	int ret;
848 
849 	set_min_preemption_timeout(guc, q);
850 	smp_rmb();
851 	ret = wait_event_timeout(guc->ct.wq, !exec_queue_pending_enable(q) ||
852 				 guc_read_stopped(guc), HZ * 5);
853 	if (!ret) {
854 		struct xe_gpu_scheduler *sched = &q->guc->sched;
855 
856 		drm_warn(&xe->drm, "Pending enable failed to respond");
857 		xe_sched_submission_start(sched);
858 		xe_gt_reset_async(q->gt);
859 		xe_sched_tdr_queue_imm(sched);
860 		return;
861 	}
862 
863 	clear_exec_queue_enabled(q);
864 	set_exec_queue_pending_disable(q);
865 	set_exec_queue_destroyed(q);
866 	trace_xe_exec_queue_scheduling_disable(q);
867 
868 	/*
869 	 * Reserve space for both G2H here as the 2nd G2H is sent from a G2H
870 	 * handler and we are not allowed to reserved G2H space in handlers.
871 	 */
872 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
873 		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET +
874 		       G2H_LEN_DW_DEREGISTER_CONTEXT, 2);
875 }
876 
877 static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q)
878 {
879 	struct xe_guc *guc = exec_queue_to_guc(q);
880 	struct xe_device *xe = guc_to_xe(guc);
881 
882 	/** to wakeup xe_wait_user_fence ioctl if exec queue is reset */
883 	wake_up_all(&xe->ufence_wq);
884 
885 	if (xe_exec_queue_is_lr(q))
886 		queue_work(guc_to_gt(guc)->ordered_wq, &q->guc->lr_tdr);
887 	else
888 		xe_sched_tdr_queue_imm(&q->guc->sched);
889 }
890 
891 /**
892  * xe_guc_submit_wedge() - Wedge GuC submission
893  * @guc: the GuC object
894  *
895  * Save exec queue's registered with GuC state by taking a ref to each queue.
896  * Register a DRMM handler to drop refs upon driver unload.
897  */
898 void xe_guc_submit_wedge(struct xe_guc *guc)
899 {
900 	struct xe_device *xe = guc_to_xe(guc);
901 	struct xe_exec_queue *q;
902 	unsigned long index;
903 	int err;
904 
905 	xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode);
906 
907 	err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev,
908 				       guc_submit_wedged_fini, guc);
909 	if (err) {
910 		drm_err(&xe->drm, "Failed to register xe_guc_submit clean-up on wedged.mode=2. Although device is wedged.\n");
911 		return;
912 	}
913 
914 	mutex_lock(&guc->submission_state.lock);
915 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
916 		if (xe_exec_queue_get_unless_zero(q))
917 			set_exec_queue_wedged(q);
918 	mutex_unlock(&guc->submission_state.lock);
919 }
920 
921 static bool guc_submit_hint_wedged(struct xe_guc *guc)
922 {
923 	struct xe_device *xe = guc_to_xe(guc);
924 
925 	if (xe->wedged.mode != 2)
926 		return false;
927 
928 	if (xe_device_wedged(xe))
929 		return true;
930 
931 	xe_device_declare_wedged(xe);
932 
933 	return true;
934 }
935 
936 static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w)
937 {
938 	struct xe_guc_exec_queue *ge =
939 		container_of(w, struct xe_guc_exec_queue, lr_tdr);
940 	struct xe_exec_queue *q = ge->q;
941 	struct xe_guc *guc = exec_queue_to_guc(q);
942 	struct xe_device *xe = guc_to_xe(guc);
943 	struct xe_gpu_scheduler *sched = &ge->sched;
944 	bool wedged;
945 
946 	xe_assert(xe, xe_exec_queue_is_lr(q));
947 	trace_xe_exec_queue_lr_cleanup(q);
948 
949 	wedged = guc_submit_hint_wedged(exec_queue_to_guc(q));
950 
951 	/* Kill the run_job / process_msg entry points */
952 	xe_sched_submission_stop(sched);
953 
954 	/*
955 	 * Engine state now mostly stable, disable scheduling / deregister if
956 	 * needed. This cleanup routine might be called multiple times, where
957 	 * the actual async engine deregister drops the final engine ref.
958 	 * Calling disable_scheduling_deregister will mark the engine as
959 	 * destroyed and fire off the CT requests to disable scheduling /
960 	 * deregister, which we only want to do once. We also don't want to mark
961 	 * the engine as pending_disable again as this may race with the
962 	 * xe_guc_deregister_done_handler() which treats it as an unexpected
963 	 * state.
964 	 */
965 	if (!wedged && exec_queue_registered(q) && !exec_queue_destroyed(q)) {
966 		struct xe_guc *guc = exec_queue_to_guc(q);
967 		int ret;
968 
969 		set_exec_queue_banned(q);
970 		disable_scheduling_deregister(guc, q);
971 
972 		/*
973 		 * Must wait for scheduling to be disabled before signalling
974 		 * any fences, if GT broken the GT reset code should signal us.
975 		 */
976 		ret = wait_event_timeout(guc->ct.wq,
977 					 !exec_queue_pending_disable(q) ||
978 					 guc_read_stopped(guc), HZ * 5);
979 		if (!ret) {
980 			drm_warn(&xe->drm, "Schedule disable failed to respond");
981 			xe_sched_submission_start(sched);
982 			xe_gt_reset_async(q->gt);
983 			return;
984 		}
985 	}
986 
987 	xe_sched_submission_start(sched);
988 }
989 
990 #define ADJUST_FIVE_PERCENT(__t)	mul_u64_u32_div(__t, 105, 100)
991 
992 static bool check_timeout(struct xe_exec_queue *q, struct xe_sched_job *job)
993 {
994 	struct xe_gt *gt = guc_to_gt(exec_queue_to_guc(q));
995 	u32 ctx_timestamp = xe_lrc_ctx_timestamp(q->lrc[0]);
996 	u32 ctx_job_timestamp = xe_lrc_ctx_job_timestamp(q->lrc[0]);
997 	u32 timeout_ms = q->sched_props.job_timeout_ms;
998 	u32 diff;
999 	u64 running_time_ms;
1000 
1001 	/*
1002 	 * Counter wraps at ~223s at the usual 19.2MHz, be paranoid catch
1003 	 * possible overflows with a high timeout.
1004 	 */
1005 	xe_gt_assert(gt, timeout_ms < 100 * MSEC_PER_SEC);
1006 
1007 	if (ctx_timestamp < ctx_job_timestamp)
1008 		diff = ctx_timestamp + U32_MAX - ctx_job_timestamp;
1009 	else
1010 		diff = ctx_timestamp - ctx_job_timestamp;
1011 
1012 	/*
1013 	 * Ensure timeout is within 5% to account for an GuC scheduling latency
1014 	 */
1015 	running_time_ms =
1016 		ADJUST_FIVE_PERCENT(xe_gt_clock_interval_to_ms(gt, diff));
1017 
1018 	xe_gt_dbg(gt,
1019 		  "Check job timeout: seqno=%u, lrc_seqno=%u, guc_id=%d, running_time_ms=%llu, timeout_ms=%u, diff=0x%08x",
1020 		  xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job),
1021 		  q->guc->id, running_time_ms, timeout_ms, diff);
1022 
1023 	return running_time_ms >= timeout_ms;
1024 }
1025 
1026 static void enable_scheduling(struct xe_exec_queue *q)
1027 {
1028 	MAKE_SCHED_CONTEXT_ACTION(q, ENABLE);
1029 	struct xe_guc *guc = exec_queue_to_guc(q);
1030 	int ret;
1031 
1032 	xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q));
1033 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
1034 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
1035 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q));
1036 
1037 	set_exec_queue_pending_enable(q);
1038 	set_exec_queue_enabled(q);
1039 	trace_xe_exec_queue_scheduling_enable(q);
1040 
1041 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
1042 		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);
1043 
1044 	ret = wait_event_timeout(guc->ct.wq,
1045 				 !exec_queue_pending_enable(q) ||
1046 				 guc_read_stopped(guc), HZ * 5);
1047 	if (!ret || guc_read_stopped(guc)) {
1048 		xe_gt_warn(guc_to_gt(guc), "Schedule enable failed to respond");
1049 		set_exec_queue_banned(q);
1050 		xe_gt_reset_async(q->gt);
1051 		xe_sched_tdr_queue_imm(&q->guc->sched);
1052 	}
1053 }
1054 
1055 static void disable_scheduling(struct xe_exec_queue *q, bool immediate)
1056 {
1057 	MAKE_SCHED_CONTEXT_ACTION(q, DISABLE);
1058 	struct xe_guc *guc = exec_queue_to_guc(q);
1059 
1060 	xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q));
1061 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
1062 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
1063 
1064 	if (immediate)
1065 		set_min_preemption_timeout(guc, q);
1066 	clear_exec_queue_enabled(q);
1067 	set_exec_queue_pending_disable(q);
1068 	trace_xe_exec_queue_scheduling_disable(q);
1069 
1070 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
1071 		       G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1);
1072 }
1073 
1074 static void __deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
1075 {
1076 	u32 action[] = {
1077 		XE_GUC_ACTION_DEREGISTER_CONTEXT,
1078 		q->guc->id,
1079 	};
1080 
1081 	xe_gt_assert(guc_to_gt(guc), !exec_queue_destroyed(q));
1082 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
1083 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q));
1084 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
1085 
1086 	set_exec_queue_destroyed(q);
1087 	trace_xe_exec_queue_deregister(q);
1088 
1089 	xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action),
1090 		       G2H_LEN_DW_DEREGISTER_CONTEXT, 1);
1091 }
1092 
1093 static enum drm_gpu_sched_stat
1094 guc_exec_queue_timedout_job(struct drm_sched_job *drm_job)
1095 {
1096 	struct xe_sched_job *job = to_xe_sched_job(drm_job);
1097 	struct xe_sched_job *tmp_job;
1098 	struct xe_exec_queue *q = job->q;
1099 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1100 	struct xe_guc *guc = exec_queue_to_guc(q);
1101 	const char *process_name = "no process";
1102 	int err = -ETIME;
1103 	pid_t pid = -1;
1104 	int i = 0;
1105 	bool wedged, skip_timeout_check;
1106 
1107 	/*
1108 	 * TDR has fired before free job worker. Common if exec queue
1109 	 * immediately closed after last fence signaled.
1110 	 */
1111 	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &job->fence->flags)) {
1112 		guc_exec_queue_free_job(drm_job);
1113 
1114 		return DRM_GPU_SCHED_STAT_NOMINAL;
1115 	}
1116 
1117 	/* Kill the run_job entry point */
1118 	xe_sched_submission_stop(sched);
1119 
1120 	/* Must check all state after stopping scheduler */
1121 	skip_timeout_check = exec_queue_reset(q) ||
1122 		exec_queue_killed_or_banned_or_wedged(q) ||
1123 		exec_queue_destroyed(q);
1124 
1125 	/* Job hasn't started, can't be timed out */
1126 	if (!skip_timeout_check && !xe_sched_job_started(job))
1127 		goto rearm;
1128 
1129 	/*
1130 	 * XXX: Sampling timeout doesn't work in wedged mode as we have to
1131 	 * modify scheduling state to read timestamp. We could read the
1132 	 * timestamp from a register to accumulate current running time but this
1133 	 * doesn't work for SRIOV. For now assuming timeouts in wedged mode are
1134 	 * genuine timeouts.
1135 	 */
1136 	wedged = guc_submit_hint_wedged(exec_queue_to_guc(q));
1137 
1138 	/* Engine state now stable, disable scheduling to check timestamp */
1139 	if (!wedged && exec_queue_registered(q)) {
1140 		int ret;
1141 
1142 		if (exec_queue_reset(q))
1143 			err = -EIO;
1144 
1145 		if (!exec_queue_destroyed(q)) {
1146 			/*
1147 			 * Wait for any pending G2H to flush out before
1148 			 * modifying state
1149 			 */
1150 			ret = wait_event_timeout(guc->ct.wq,
1151 						 !exec_queue_pending_enable(q) ||
1152 						 guc_read_stopped(guc), HZ * 5);
1153 			if (!ret || guc_read_stopped(guc))
1154 				goto trigger_reset;
1155 
1156 			/*
1157 			 * Flag communicates to G2H handler that schedule
1158 			 * disable originated from a timeout check. The G2H then
1159 			 * avoid triggering cleanup or deregistering the exec
1160 			 * queue.
1161 			 */
1162 			set_exec_queue_check_timeout(q);
1163 			disable_scheduling(q, skip_timeout_check);
1164 		}
1165 
1166 		/*
1167 		 * Must wait for scheduling to be disabled before signalling
1168 		 * any fences, if GT broken the GT reset code should signal us.
1169 		 *
1170 		 * FIXME: Tests can generate a ton of 0x6000 (IOMMU CAT fault
1171 		 * error) messages which can cause the schedule disable to get
1172 		 * lost. If this occurs, trigger a GT reset to recover.
1173 		 */
1174 		smp_rmb();
1175 		ret = wait_event_timeout(guc->ct.wq,
1176 					 !exec_queue_pending_disable(q) ||
1177 					 guc_read_stopped(guc), HZ * 5);
1178 		if (!ret || guc_read_stopped(guc)) {
1179 trigger_reset:
1180 			if (!ret)
1181 				xe_gt_warn(guc_to_gt(guc), "Schedule disable failed to respond");
1182 			set_exec_queue_extra_ref(q);
1183 			xe_exec_queue_get(q);	/* GT reset owns this */
1184 			set_exec_queue_banned(q);
1185 			xe_gt_reset_async(q->gt);
1186 			xe_sched_tdr_queue_imm(sched);
1187 			goto rearm;
1188 		}
1189 	}
1190 
1191 	/*
1192 	 * Check if job is actually timed out, if so restart job execution and TDR
1193 	 */
1194 	if (!wedged && !skip_timeout_check && !check_timeout(q, job) &&
1195 	    !exec_queue_reset(q) && exec_queue_registered(q)) {
1196 		clear_exec_queue_check_timeout(q);
1197 		goto sched_enable;
1198 	}
1199 
1200 	if (q->vm && q->vm->xef) {
1201 		process_name = q->vm->xef->process_name;
1202 		pid = q->vm->xef->pid;
1203 	}
1204 	xe_gt_notice(guc_to_gt(guc), "Timedout job: seqno=%u, lrc_seqno=%u, guc_id=%d, flags=0x%lx in %s [%d]",
1205 		     xe_sched_job_seqno(job), xe_sched_job_lrc_seqno(job),
1206 		     q->guc->id, q->flags, process_name, pid);
1207 
1208 	trace_xe_sched_job_timedout(job);
1209 
1210 	if (!exec_queue_killed(q))
1211 		xe_devcoredump(job);
1212 
1213 	/*
1214 	 * Kernel jobs should never fail, nor should VM jobs if they do
1215 	 * somethings has gone wrong and the GT needs a reset
1216 	 */
1217 	xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_KERNEL,
1218 		   "Kernel-submitted job timed out\n");
1219 	xe_gt_WARN(q->gt, q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q),
1220 		   "VM job timed out on non-killed execqueue\n");
1221 	if (!wedged && (q->flags & EXEC_QUEUE_FLAG_KERNEL ||
1222 			(q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q)))) {
1223 		if (!xe_sched_invalidate_job(job, 2)) {
1224 			clear_exec_queue_check_timeout(q);
1225 			xe_gt_reset_async(q->gt);
1226 			goto rearm;
1227 		}
1228 	}
1229 
1230 	/* Finish cleaning up exec queue via deregister */
1231 	set_exec_queue_banned(q);
1232 	if (!wedged && exec_queue_registered(q) && !exec_queue_destroyed(q)) {
1233 		set_exec_queue_extra_ref(q);
1234 		xe_exec_queue_get(q);
1235 		__deregister_exec_queue(guc, q);
1236 	}
1237 
1238 	/* Stop fence signaling */
1239 	xe_hw_fence_irq_stop(q->fence_irq);
1240 
1241 	/*
1242 	 * Fence state now stable, stop / start scheduler which cleans up any
1243 	 * fences that are complete
1244 	 */
1245 	xe_sched_add_pending_job(sched, job);
1246 	xe_sched_submission_start(sched);
1247 
1248 	xe_guc_exec_queue_trigger_cleanup(q);
1249 
1250 	/* Mark all outstanding jobs as bad, thus completing them */
1251 	spin_lock(&sched->base.job_list_lock);
1252 	list_for_each_entry(tmp_job, &sched->base.pending_list, drm.list)
1253 		xe_sched_job_set_error(tmp_job, !i++ ? err : -ECANCELED);
1254 	spin_unlock(&sched->base.job_list_lock);
1255 
1256 	/* Start fence signaling */
1257 	xe_hw_fence_irq_start(q->fence_irq);
1258 
1259 	return DRM_GPU_SCHED_STAT_NOMINAL;
1260 
1261 sched_enable:
1262 	enable_scheduling(q);
1263 rearm:
1264 	/*
1265 	 * XXX: Ideally want to adjust timeout based on current exection time
1266 	 * but there is not currently an easy way to do in DRM scheduler. With
1267 	 * some thought, do this in a follow up.
1268 	 */
1269 	xe_sched_add_pending_job(sched, job);
1270 	xe_sched_submission_start(sched);
1271 
1272 	return DRM_GPU_SCHED_STAT_NOMINAL;
1273 }
1274 
1275 static void __guc_exec_queue_fini_async(struct work_struct *w)
1276 {
1277 	struct xe_guc_exec_queue *ge =
1278 		container_of(w, struct xe_guc_exec_queue, fini_async);
1279 	struct xe_exec_queue *q = ge->q;
1280 	struct xe_guc *guc = exec_queue_to_guc(q);
1281 
1282 	xe_pm_runtime_get(guc_to_xe(guc));
1283 	trace_xe_exec_queue_destroy(q);
1284 
1285 	if (xe_exec_queue_is_lr(q))
1286 		cancel_work_sync(&ge->lr_tdr);
1287 	release_guc_id(guc, q);
1288 	xe_sched_entity_fini(&ge->entity);
1289 	xe_sched_fini(&ge->sched);
1290 
1291 	kfree(ge);
1292 	xe_exec_queue_fini(q);
1293 	xe_pm_runtime_put(guc_to_xe(guc));
1294 }
1295 
1296 static void guc_exec_queue_fini_async(struct xe_exec_queue *q)
1297 {
1298 	struct xe_guc *guc = exec_queue_to_guc(q);
1299 	struct xe_device *xe = guc_to_xe(guc);
1300 
1301 	INIT_WORK(&q->guc->fini_async, __guc_exec_queue_fini_async);
1302 
1303 	/* We must block on kernel engines so slabs are empty on driver unload */
1304 	if (q->flags & EXEC_QUEUE_FLAG_PERMANENT || exec_queue_wedged(q))
1305 		__guc_exec_queue_fini_async(&q->guc->fini_async);
1306 	else
1307 		queue_work(xe->destroy_wq, &q->guc->fini_async);
1308 }
1309 
1310 static void __guc_exec_queue_fini(struct xe_guc *guc, struct xe_exec_queue *q)
1311 {
1312 	/*
1313 	 * Might be done from within the GPU scheduler, need to do async as we
1314 	 * fini the scheduler when the engine is fini'd, the scheduler can't
1315 	 * complete fini within itself (circular dependency). Async resolves
1316 	 * this we and don't really care when everything is fini'd, just that it
1317 	 * is.
1318 	 */
1319 	guc_exec_queue_fini_async(q);
1320 }
1321 
1322 static void __guc_exec_queue_process_msg_cleanup(struct xe_sched_msg *msg)
1323 {
1324 	struct xe_exec_queue *q = msg->private_data;
1325 	struct xe_guc *guc = exec_queue_to_guc(q);
1326 	struct xe_device *xe = guc_to_xe(guc);
1327 
1328 	xe_assert(xe, !(q->flags & EXEC_QUEUE_FLAG_PERMANENT));
1329 	trace_xe_exec_queue_cleanup_entity(q);
1330 
1331 	if (exec_queue_registered(q))
1332 		disable_scheduling_deregister(guc, q);
1333 	else
1334 		__guc_exec_queue_fini(guc, q);
1335 }
1336 
1337 static bool guc_exec_queue_allowed_to_change_state(struct xe_exec_queue *q)
1338 {
1339 	return !exec_queue_killed_or_banned_or_wedged(q) && exec_queue_registered(q);
1340 }
1341 
1342 static void __guc_exec_queue_process_msg_set_sched_props(struct xe_sched_msg *msg)
1343 {
1344 	struct xe_exec_queue *q = msg->private_data;
1345 	struct xe_guc *guc = exec_queue_to_guc(q);
1346 
1347 	if (guc_exec_queue_allowed_to_change_state(q))
1348 		init_policies(guc, q);
1349 	kfree(msg);
1350 }
1351 
1352 static void __suspend_fence_signal(struct xe_exec_queue *q)
1353 {
1354 	if (!q->guc->suspend_pending)
1355 		return;
1356 
1357 	WRITE_ONCE(q->guc->suspend_pending, false);
1358 	wake_up(&q->guc->suspend_wait);
1359 }
1360 
1361 static void suspend_fence_signal(struct xe_exec_queue *q)
1362 {
1363 	struct xe_guc *guc = exec_queue_to_guc(q);
1364 	struct xe_device *xe = guc_to_xe(guc);
1365 
1366 	xe_assert(xe, exec_queue_suspended(q) || exec_queue_killed(q) ||
1367 		  guc_read_stopped(guc));
1368 	xe_assert(xe, q->guc->suspend_pending);
1369 
1370 	__suspend_fence_signal(q);
1371 }
1372 
1373 static void __guc_exec_queue_process_msg_suspend(struct xe_sched_msg *msg)
1374 {
1375 	struct xe_exec_queue *q = msg->private_data;
1376 	struct xe_guc *guc = exec_queue_to_guc(q);
1377 
1378 	if (guc_exec_queue_allowed_to_change_state(q) && !exec_queue_suspended(q) &&
1379 	    exec_queue_enabled(q)) {
1380 		wait_event(guc->ct.wq, q->guc->resume_time != RESUME_PENDING ||
1381 			   guc_read_stopped(guc));
1382 
1383 		if (!guc_read_stopped(guc)) {
1384 			s64 since_resume_ms =
1385 				ktime_ms_delta(ktime_get(),
1386 					       q->guc->resume_time);
1387 			s64 wait_ms = q->vm->preempt.min_run_period_ms -
1388 				since_resume_ms;
1389 
1390 			if (wait_ms > 0 && q->guc->resume_time)
1391 				msleep(wait_ms);
1392 
1393 			set_exec_queue_suspended(q);
1394 			disable_scheduling(q, false);
1395 		}
1396 	} else if (q->guc->suspend_pending) {
1397 		set_exec_queue_suspended(q);
1398 		suspend_fence_signal(q);
1399 	}
1400 }
1401 
1402 static void __guc_exec_queue_process_msg_resume(struct xe_sched_msg *msg)
1403 {
1404 	struct xe_exec_queue *q = msg->private_data;
1405 
1406 	if (guc_exec_queue_allowed_to_change_state(q)) {
1407 		clear_exec_queue_suspended(q);
1408 		if (!exec_queue_enabled(q)) {
1409 			q->guc->resume_time = RESUME_PENDING;
1410 			enable_scheduling(q);
1411 		}
1412 	} else {
1413 		clear_exec_queue_suspended(q);
1414 	}
1415 }
1416 
1417 #define CLEANUP		1	/* Non-zero values to catch uninitialized msg */
1418 #define SET_SCHED_PROPS	2
1419 #define SUSPEND		3
1420 #define RESUME		4
1421 #define OPCODE_MASK	0xf
1422 #define MSG_LOCKED	BIT(8)
1423 
1424 static void guc_exec_queue_process_msg(struct xe_sched_msg *msg)
1425 {
1426 	struct xe_device *xe = guc_to_xe(exec_queue_to_guc(msg->private_data));
1427 
1428 	trace_xe_sched_msg_recv(msg);
1429 
1430 	switch (msg->opcode) {
1431 	case CLEANUP:
1432 		__guc_exec_queue_process_msg_cleanup(msg);
1433 		break;
1434 	case SET_SCHED_PROPS:
1435 		__guc_exec_queue_process_msg_set_sched_props(msg);
1436 		break;
1437 	case SUSPEND:
1438 		__guc_exec_queue_process_msg_suspend(msg);
1439 		break;
1440 	case RESUME:
1441 		__guc_exec_queue_process_msg_resume(msg);
1442 		break;
1443 	default:
1444 		XE_WARN_ON("Unknown message type");
1445 	}
1446 
1447 	xe_pm_runtime_put(xe);
1448 }
1449 
1450 static const struct drm_sched_backend_ops drm_sched_ops = {
1451 	.run_job = guc_exec_queue_run_job,
1452 	.free_job = guc_exec_queue_free_job,
1453 	.timedout_job = guc_exec_queue_timedout_job,
1454 };
1455 
1456 static const struct xe_sched_backend_ops xe_sched_ops = {
1457 	.process_msg = guc_exec_queue_process_msg,
1458 };
1459 
1460 static int guc_exec_queue_init(struct xe_exec_queue *q)
1461 {
1462 	struct xe_gpu_scheduler *sched;
1463 	struct xe_guc *guc = exec_queue_to_guc(q);
1464 	struct xe_device *xe = guc_to_xe(guc);
1465 	struct xe_guc_exec_queue *ge;
1466 	long timeout;
1467 	int err, i;
1468 
1469 	xe_assert(xe, xe_device_uc_enabled(guc_to_xe(guc)));
1470 
1471 	ge = kzalloc(sizeof(*ge), GFP_KERNEL);
1472 	if (!ge)
1473 		return -ENOMEM;
1474 
1475 	q->guc = ge;
1476 	ge->q = q;
1477 	init_waitqueue_head(&ge->suspend_wait);
1478 
1479 	for (i = 0; i < MAX_STATIC_MSG_TYPE; ++i)
1480 		INIT_LIST_HEAD(&ge->static_msgs[i].link);
1481 
1482 	timeout = (q->vm && xe_vm_in_lr_mode(q->vm)) ? MAX_SCHEDULE_TIMEOUT :
1483 		  msecs_to_jiffies(q->sched_props.job_timeout_ms);
1484 	err = xe_sched_init(&ge->sched, &drm_sched_ops, &xe_sched_ops,
1485 			    get_submit_wq(guc),
1486 			    q->lrc[0]->ring.size / MAX_JOB_SIZE_BYTES, 64,
1487 			    timeout, guc_to_gt(guc)->ordered_wq, NULL,
1488 			    q->name, gt_to_xe(q->gt)->drm.dev);
1489 	if (err)
1490 		goto err_free;
1491 
1492 	sched = &ge->sched;
1493 	err = xe_sched_entity_init(&ge->entity, sched);
1494 	if (err)
1495 		goto err_sched;
1496 
1497 	if (xe_exec_queue_is_lr(q))
1498 		INIT_WORK(&q->guc->lr_tdr, xe_guc_exec_queue_lr_cleanup);
1499 
1500 	mutex_lock(&guc->submission_state.lock);
1501 
1502 	err = alloc_guc_id(guc, q);
1503 	if (err)
1504 		goto err_entity;
1505 
1506 	q->entity = &ge->entity;
1507 
1508 	if (guc_read_stopped(guc))
1509 		xe_sched_stop(sched);
1510 
1511 	mutex_unlock(&guc->submission_state.lock);
1512 
1513 	xe_exec_queue_assign_name(q, q->guc->id);
1514 
1515 	trace_xe_exec_queue_create(q);
1516 
1517 	return 0;
1518 
1519 err_entity:
1520 	mutex_unlock(&guc->submission_state.lock);
1521 	xe_sched_entity_fini(&ge->entity);
1522 err_sched:
1523 	xe_sched_fini(&ge->sched);
1524 err_free:
1525 	kfree(ge);
1526 
1527 	return err;
1528 }
1529 
1530 static void guc_exec_queue_kill(struct xe_exec_queue *q)
1531 {
1532 	trace_xe_exec_queue_kill(q);
1533 	set_exec_queue_killed(q);
1534 	__suspend_fence_signal(q);
1535 	xe_guc_exec_queue_trigger_cleanup(q);
1536 }
1537 
1538 static void guc_exec_queue_add_msg(struct xe_exec_queue *q, struct xe_sched_msg *msg,
1539 				   u32 opcode)
1540 {
1541 	xe_pm_runtime_get_noresume(guc_to_xe(exec_queue_to_guc(q)));
1542 
1543 	INIT_LIST_HEAD(&msg->link);
1544 	msg->opcode = opcode & OPCODE_MASK;
1545 	msg->private_data = q;
1546 
1547 	trace_xe_sched_msg_add(msg);
1548 	if (opcode & MSG_LOCKED)
1549 		xe_sched_add_msg_locked(&q->guc->sched, msg);
1550 	else
1551 		xe_sched_add_msg(&q->guc->sched, msg);
1552 }
1553 
1554 static bool guc_exec_queue_try_add_msg(struct xe_exec_queue *q,
1555 				       struct xe_sched_msg *msg,
1556 				       u32 opcode)
1557 {
1558 	if (!list_empty(&msg->link))
1559 		return false;
1560 
1561 	guc_exec_queue_add_msg(q, msg, opcode | MSG_LOCKED);
1562 
1563 	return true;
1564 }
1565 
1566 #define STATIC_MSG_CLEANUP	0
1567 #define STATIC_MSG_SUSPEND	1
1568 #define STATIC_MSG_RESUME	2
1569 static void guc_exec_queue_fini(struct xe_exec_queue *q)
1570 {
1571 	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP;
1572 
1573 	if (!(q->flags & EXEC_QUEUE_FLAG_PERMANENT) && !exec_queue_wedged(q))
1574 		guc_exec_queue_add_msg(q, msg, CLEANUP);
1575 	else
1576 		__guc_exec_queue_fini(exec_queue_to_guc(q), q);
1577 }
1578 
1579 static int guc_exec_queue_set_priority(struct xe_exec_queue *q,
1580 				       enum xe_exec_queue_priority priority)
1581 {
1582 	struct xe_sched_msg *msg;
1583 
1584 	if (q->sched_props.priority == priority ||
1585 	    exec_queue_killed_or_banned_or_wedged(q))
1586 		return 0;
1587 
1588 	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
1589 	if (!msg)
1590 		return -ENOMEM;
1591 
1592 	q->sched_props.priority = priority;
1593 	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);
1594 
1595 	return 0;
1596 }
1597 
1598 static int guc_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us)
1599 {
1600 	struct xe_sched_msg *msg;
1601 
1602 	if (q->sched_props.timeslice_us == timeslice_us ||
1603 	    exec_queue_killed_or_banned_or_wedged(q))
1604 		return 0;
1605 
1606 	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
1607 	if (!msg)
1608 		return -ENOMEM;
1609 
1610 	q->sched_props.timeslice_us = timeslice_us;
1611 	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);
1612 
1613 	return 0;
1614 }
1615 
1616 static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q,
1617 					      u32 preempt_timeout_us)
1618 {
1619 	struct xe_sched_msg *msg;
1620 
1621 	if (q->sched_props.preempt_timeout_us == preempt_timeout_us ||
1622 	    exec_queue_killed_or_banned_or_wedged(q))
1623 		return 0;
1624 
1625 	msg = kmalloc(sizeof(*msg), GFP_KERNEL);
1626 	if (!msg)
1627 		return -ENOMEM;
1628 
1629 	q->sched_props.preempt_timeout_us = preempt_timeout_us;
1630 	guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS);
1631 
1632 	return 0;
1633 }
1634 
1635 static int guc_exec_queue_suspend(struct xe_exec_queue *q)
1636 {
1637 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1638 	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_SUSPEND;
1639 
1640 	if (exec_queue_killed_or_banned_or_wedged(q))
1641 		return -EINVAL;
1642 
1643 	xe_sched_msg_lock(sched);
1644 	if (guc_exec_queue_try_add_msg(q, msg, SUSPEND))
1645 		q->guc->suspend_pending = true;
1646 	xe_sched_msg_unlock(sched);
1647 
1648 	return 0;
1649 }
1650 
1651 static int guc_exec_queue_suspend_wait(struct xe_exec_queue *q)
1652 {
1653 	struct xe_guc *guc = exec_queue_to_guc(q);
1654 	int ret;
1655 
1656 	/*
1657 	 * Likely don't need to check exec_queue_killed() as we clear
1658 	 * suspend_pending upon kill but to be paranoid but races in which
1659 	 * suspend_pending is set after kill also check kill here.
1660 	 */
1661 	ret = wait_event_interruptible_timeout(q->guc->suspend_wait,
1662 					       !READ_ONCE(q->guc->suspend_pending) ||
1663 					       exec_queue_killed(q) ||
1664 					       guc_read_stopped(guc),
1665 					       HZ * 5);
1666 
1667 	if (!ret) {
1668 		xe_gt_warn(guc_to_gt(guc),
1669 			   "Suspend fence, guc_id=%d, failed to respond",
1670 			   q->guc->id);
1671 		/* XXX: Trigger GT reset? */
1672 		return -ETIME;
1673 	}
1674 
1675 	return ret < 0 ? ret : 0;
1676 }
1677 
1678 static void guc_exec_queue_resume(struct xe_exec_queue *q)
1679 {
1680 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1681 	struct xe_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_RESUME;
1682 	struct xe_guc *guc = exec_queue_to_guc(q);
1683 	struct xe_device *xe = guc_to_xe(guc);
1684 
1685 	xe_assert(xe, !q->guc->suspend_pending);
1686 
1687 	xe_sched_msg_lock(sched);
1688 	guc_exec_queue_try_add_msg(q, msg, RESUME);
1689 	xe_sched_msg_unlock(sched);
1690 }
1691 
1692 static bool guc_exec_queue_reset_status(struct xe_exec_queue *q)
1693 {
1694 	return exec_queue_reset(q) || exec_queue_killed_or_banned_or_wedged(q);
1695 }
1696 
1697 /*
1698  * All of these functions are an abstraction layer which other parts of XE can
1699  * use to trap into the GuC backend. All of these functions, aside from init,
1700  * really shouldn't do much other than trap into the DRM scheduler which
1701  * synchronizes these operations.
1702  */
1703 static const struct xe_exec_queue_ops guc_exec_queue_ops = {
1704 	.init = guc_exec_queue_init,
1705 	.kill = guc_exec_queue_kill,
1706 	.fini = guc_exec_queue_fini,
1707 	.set_priority = guc_exec_queue_set_priority,
1708 	.set_timeslice = guc_exec_queue_set_timeslice,
1709 	.set_preempt_timeout = guc_exec_queue_set_preempt_timeout,
1710 	.suspend = guc_exec_queue_suspend,
1711 	.suspend_wait = guc_exec_queue_suspend_wait,
1712 	.resume = guc_exec_queue_resume,
1713 	.reset_status = guc_exec_queue_reset_status,
1714 };
1715 
1716 static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q)
1717 {
1718 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1719 
1720 	/* Stop scheduling + flush any DRM scheduler operations */
1721 	xe_sched_submission_stop(sched);
1722 
1723 	/* Clean up lost G2H + reset engine state */
1724 	if (exec_queue_registered(q)) {
1725 		if (exec_queue_extra_ref(q) || xe_exec_queue_is_lr(q))
1726 			xe_exec_queue_put(q);
1727 		else if (exec_queue_destroyed(q))
1728 			__guc_exec_queue_fini(guc, q);
1729 	}
1730 	if (q->guc->suspend_pending) {
1731 		set_exec_queue_suspended(q);
1732 		suspend_fence_signal(q);
1733 	}
1734 	atomic_and(EXEC_QUEUE_STATE_WEDGED | EXEC_QUEUE_STATE_BANNED |
1735 		   EXEC_QUEUE_STATE_KILLED | EXEC_QUEUE_STATE_DESTROYED |
1736 		   EXEC_QUEUE_STATE_SUSPENDED,
1737 		   &q->guc->state);
1738 	q->guc->resume_time = 0;
1739 	trace_xe_exec_queue_stop(q);
1740 
1741 	/*
1742 	 * Ban any engine (aside from kernel and engines used for VM ops) with a
1743 	 * started but not complete job or if a job has gone through a GT reset
1744 	 * more than twice.
1745 	 */
1746 	if (!(q->flags & (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM))) {
1747 		struct xe_sched_job *job = xe_sched_first_pending_job(sched);
1748 		bool ban = false;
1749 
1750 		if (job) {
1751 			if ((xe_sched_job_started(job) &&
1752 			    !xe_sched_job_completed(job)) ||
1753 			    xe_sched_invalidate_job(job, 2)) {
1754 				trace_xe_sched_job_ban(job);
1755 				ban = true;
1756 			}
1757 		} else if (xe_exec_queue_is_lr(q) &&
1758 			   (xe_lrc_ring_head(q->lrc[0]) != xe_lrc_ring_tail(q->lrc[0]))) {
1759 			ban = true;
1760 		}
1761 
1762 		if (ban) {
1763 			set_exec_queue_banned(q);
1764 			xe_guc_exec_queue_trigger_cleanup(q);
1765 		}
1766 	}
1767 }
1768 
1769 int xe_guc_submit_reset_prepare(struct xe_guc *guc)
1770 {
1771 	int ret;
1772 
1773 	/*
1774 	 * Using an atomic here rather than submission_state.lock as this
1775 	 * function can be called while holding the CT lock (engine reset
1776 	 * failure). submission_state.lock needs the CT lock to resubmit jobs.
1777 	 * Atomic is not ideal, but it works to prevent against concurrent reset
1778 	 * and releasing any TDRs waiting on guc->submission_state.stopped.
1779 	 */
1780 	ret = atomic_fetch_or(1, &guc->submission_state.stopped);
1781 	smp_wmb();
1782 	wake_up_all(&guc->ct.wq);
1783 
1784 	return ret;
1785 }
1786 
1787 void xe_guc_submit_reset_wait(struct xe_guc *guc)
1788 {
1789 	wait_event(guc->ct.wq, xe_device_wedged(guc_to_xe(guc)) ||
1790 		   !guc_read_stopped(guc));
1791 }
1792 
1793 void xe_guc_submit_stop(struct xe_guc *guc)
1794 {
1795 	struct xe_exec_queue *q;
1796 	unsigned long index;
1797 	struct xe_device *xe = guc_to_xe(guc);
1798 
1799 	xe_assert(xe, guc_read_stopped(guc) == 1);
1800 
1801 	mutex_lock(&guc->submission_state.lock);
1802 
1803 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
1804 		guc_exec_queue_stop(guc, q);
1805 
1806 	mutex_unlock(&guc->submission_state.lock);
1807 
1808 	/*
1809 	 * No one can enter the backend at this point, aside from new engine
1810 	 * creation which is protected by guc->submission_state.lock.
1811 	 */
1812 
1813 }
1814 
1815 static void guc_exec_queue_start(struct xe_exec_queue *q)
1816 {
1817 	struct xe_gpu_scheduler *sched = &q->guc->sched;
1818 
1819 	if (!exec_queue_killed_or_banned_or_wedged(q)) {
1820 		int i;
1821 
1822 		trace_xe_exec_queue_resubmit(q);
1823 		for (i = 0; i < q->width; ++i)
1824 			xe_lrc_set_ring_head(q->lrc[i], q->lrc[i]->ring.tail);
1825 		xe_sched_resubmit_jobs(sched);
1826 	}
1827 
1828 	xe_sched_submission_start(sched);
1829 	xe_sched_submission_resume_tdr(sched);
1830 }
1831 
1832 int xe_guc_submit_start(struct xe_guc *guc)
1833 {
1834 	struct xe_exec_queue *q;
1835 	unsigned long index;
1836 	struct xe_device *xe = guc_to_xe(guc);
1837 
1838 	xe_assert(xe, guc_read_stopped(guc) == 1);
1839 
1840 	mutex_lock(&guc->submission_state.lock);
1841 	atomic_dec(&guc->submission_state.stopped);
1842 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
1843 		guc_exec_queue_start(q);
1844 	mutex_unlock(&guc->submission_state.lock);
1845 
1846 	wake_up_all(&guc->ct.wq);
1847 
1848 	return 0;
1849 }
1850 
1851 static struct xe_exec_queue *
1852 g2h_exec_queue_lookup(struct xe_guc *guc, u32 guc_id)
1853 {
1854 	struct xe_device *xe = guc_to_xe(guc);
1855 	struct xe_exec_queue *q;
1856 
1857 	if (unlikely(guc_id >= GUC_ID_MAX)) {
1858 		drm_err(&xe->drm, "Invalid guc_id %u", guc_id);
1859 		return NULL;
1860 	}
1861 
1862 	q = xa_load(&guc->submission_state.exec_queue_lookup, guc_id);
1863 	if (unlikely(!q)) {
1864 		drm_err(&xe->drm, "Not engine present for guc_id %u", guc_id);
1865 		return NULL;
1866 	}
1867 
1868 	xe_assert(xe, guc_id >= q->guc->id);
1869 	xe_assert(xe, guc_id < (q->guc->id + q->width));
1870 
1871 	return q;
1872 }
1873 
1874 static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q)
1875 {
1876 	u32 action[] = {
1877 		XE_GUC_ACTION_DEREGISTER_CONTEXT,
1878 		q->guc->id,
1879 	};
1880 
1881 	xe_gt_assert(guc_to_gt(guc), exec_queue_destroyed(q));
1882 	xe_gt_assert(guc_to_gt(guc), exec_queue_registered(q));
1883 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_disable(q));
1884 	xe_gt_assert(guc_to_gt(guc), !exec_queue_pending_enable(q));
1885 
1886 	trace_xe_exec_queue_deregister(q);
1887 
1888 	xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action));
1889 }
1890 
1891 static void handle_sched_done(struct xe_guc *guc, struct xe_exec_queue *q,
1892 			      u32 runnable_state)
1893 {
1894 	trace_xe_exec_queue_scheduling_done(q);
1895 
1896 	if (runnable_state == 1) {
1897 		xe_gt_assert(guc_to_gt(guc), exec_queue_pending_enable(q));
1898 
1899 		q->guc->resume_time = ktime_get();
1900 		clear_exec_queue_pending_enable(q);
1901 		smp_wmb();
1902 		wake_up_all(&guc->ct.wq);
1903 	} else {
1904 		bool check_timeout = exec_queue_check_timeout(q);
1905 
1906 		xe_gt_assert(guc_to_gt(guc), runnable_state == 0);
1907 		xe_gt_assert(guc_to_gt(guc), exec_queue_pending_disable(q));
1908 
1909 		clear_exec_queue_pending_disable(q);
1910 		if (q->guc->suspend_pending) {
1911 			suspend_fence_signal(q);
1912 		} else {
1913 			if (exec_queue_banned(q) || check_timeout) {
1914 				smp_wmb();
1915 				wake_up_all(&guc->ct.wq);
1916 			}
1917 			if (!check_timeout)
1918 				deregister_exec_queue(guc, q);
1919 		}
1920 	}
1921 }
1922 
1923 int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
1924 {
1925 	struct xe_device *xe = guc_to_xe(guc);
1926 	struct xe_exec_queue *q;
1927 	u32 guc_id = msg[0];
1928 	u32 runnable_state = msg[1];
1929 
1930 	if (unlikely(len < 2)) {
1931 		drm_err(&xe->drm, "Invalid length %u", len);
1932 		return -EPROTO;
1933 	}
1934 
1935 	q = g2h_exec_queue_lookup(guc, guc_id);
1936 	if (unlikely(!q))
1937 		return -EPROTO;
1938 
1939 	if (unlikely(!exec_queue_pending_enable(q) &&
1940 		     !exec_queue_pending_disable(q))) {
1941 		xe_gt_err(guc_to_gt(guc),
1942 			  "SCHED_DONE: Unexpected engine state 0x%04x, guc_id=%d, runnable_state=%u",
1943 			  atomic_read(&q->guc->state), q->guc->id,
1944 			  runnable_state);
1945 		return -EPROTO;
1946 	}
1947 
1948 	handle_sched_done(guc, q, runnable_state);
1949 
1950 	return 0;
1951 }
1952 
1953 static void handle_deregister_done(struct xe_guc *guc, struct xe_exec_queue *q)
1954 {
1955 	trace_xe_exec_queue_deregister_done(q);
1956 
1957 	clear_exec_queue_registered(q);
1958 
1959 	if (exec_queue_extra_ref(q) || xe_exec_queue_is_lr(q))
1960 		xe_exec_queue_put(q);
1961 	else
1962 		__guc_exec_queue_fini(guc, q);
1963 }
1964 
1965 int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len)
1966 {
1967 	struct xe_device *xe = guc_to_xe(guc);
1968 	struct xe_exec_queue *q;
1969 	u32 guc_id = msg[0];
1970 
1971 	if (unlikely(len < 1)) {
1972 		drm_err(&xe->drm, "Invalid length %u", len);
1973 		return -EPROTO;
1974 	}
1975 
1976 	q = g2h_exec_queue_lookup(guc, guc_id);
1977 	if (unlikely(!q))
1978 		return -EPROTO;
1979 
1980 	if (!exec_queue_destroyed(q) || exec_queue_pending_disable(q) ||
1981 	    exec_queue_pending_enable(q) || exec_queue_enabled(q)) {
1982 		xe_gt_err(guc_to_gt(guc),
1983 			  "DEREGISTER_DONE: Unexpected engine state 0x%04x, guc_id=%d",
1984 			  atomic_read(&q->guc->state), q->guc->id);
1985 		return -EPROTO;
1986 	}
1987 
1988 	handle_deregister_done(guc, q);
1989 
1990 	return 0;
1991 }
1992 
1993 int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len)
1994 {
1995 	struct xe_gt *gt = guc_to_gt(guc);
1996 	struct xe_device *xe = guc_to_xe(guc);
1997 	struct xe_exec_queue *q;
1998 	u32 guc_id = msg[0];
1999 
2000 	if (unlikely(len < 1)) {
2001 		drm_err(&xe->drm, "Invalid length %u", len);
2002 		return -EPROTO;
2003 	}
2004 
2005 	q = g2h_exec_queue_lookup(guc, guc_id);
2006 	if (unlikely(!q))
2007 		return -EPROTO;
2008 
2009 	xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: 0x%x, guc_id=%d",
2010 		   xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id);
2011 
2012 	/* FIXME: Do error capture, most likely async */
2013 
2014 	trace_xe_exec_queue_reset(q);
2015 
2016 	/*
2017 	 * A banned engine is a NOP at this point (came from
2018 	 * guc_exec_queue_timedout_job). Otherwise, kick drm scheduler to cancel
2019 	 * jobs by setting timeout of the job to the minimum value kicking
2020 	 * guc_exec_queue_timedout_job.
2021 	 */
2022 	set_exec_queue_reset(q);
2023 	if (!exec_queue_banned(q) && !exec_queue_check_timeout(q))
2024 		xe_guc_exec_queue_trigger_cleanup(q);
2025 
2026 	return 0;
2027 }
2028 
2029 int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg,
2030 					       u32 len)
2031 {
2032 	struct xe_gt *gt = guc_to_gt(guc);
2033 	struct xe_device *xe = guc_to_xe(guc);
2034 	struct xe_exec_queue *q;
2035 	u32 guc_id = msg[0];
2036 
2037 	if (unlikely(len < 1)) {
2038 		drm_err(&xe->drm, "Invalid length %u", len);
2039 		return -EPROTO;
2040 	}
2041 
2042 	q = g2h_exec_queue_lookup(guc, guc_id);
2043 	if (unlikely(!q))
2044 		return -EPROTO;
2045 
2046 	xe_gt_dbg(gt, "Engine memory cat error: engine_class=%s, logical_mask: 0x%x, guc_id=%d",
2047 		  xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id);
2048 
2049 	trace_xe_exec_queue_memory_cat_error(q);
2050 
2051 	/* Treat the same as engine reset */
2052 	set_exec_queue_reset(q);
2053 	if (!exec_queue_banned(q) && !exec_queue_check_timeout(q))
2054 		xe_guc_exec_queue_trigger_cleanup(q);
2055 
2056 	return 0;
2057 }
2058 
2059 int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len)
2060 {
2061 	struct xe_device *xe = guc_to_xe(guc);
2062 	u8 guc_class, instance;
2063 	u32 reason;
2064 
2065 	if (unlikely(len != 3)) {
2066 		drm_err(&xe->drm, "Invalid length %u", len);
2067 		return -EPROTO;
2068 	}
2069 
2070 	guc_class = msg[0];
2071 	instance = msg[1];
2072 	reason = msg[2];
2073 
2074 	/* Unexpected failure of a hardware feature, log an actual error */
2075 	drm_err(&xe->drm, "GuC engine reset request failed on %d:%d because 0x%08X",
2076 		guc_class, instance, reason);
2077 
2078 	xe_gt_reset_async(guc_to_gt(guc));
2079 
2080 	return 0;
2081 }
2082 
2083 static void
2084 guc_exec_queue_wq_snapshot_capture(struct xe_exec_queue *q,
2085 				   struct xe_guc_submit_exec_queue_snapshot *snapshot)
2086 {
2087 	struct xe_guc *guc = exec_queue_to_guc(q);
2088 	struct xe_device *xe = guc_to_xe(guc);
2089 	struct iosys_map map = xe_lrc_parallel_map(q->lrc[0]);
2090 	int i;
2091 
2092 	snapshot->guc.wqi_head = q->guc->wqi_head;
2093 	snapshot->guc.wqi_tail = q->guc->wqi_tail;
2094 	snapshot->parallel.wq_desc.head = parallel_read(xe, map, wq_desc.head);
2095 	snapshot->parallel.wq_desc.tail = parallel_read(xe, map, wq_desc.tail);
2096 	snapshot->parallel.wq_desc.status = parallel_read(xe, map,
2097 							  wq_desc.wq_status);
2098 
2099 	if (snapshot->parallel.wq_desc.head !=
2100 	    snapshot->parallel.wq_desc.tail) {
2101 		for (i = snapshot->parallel.wq_desc.head;
2102 		     i != snapshot->parallel.wq_desc.tail;
2103 		     i = (i + sizeof(u32)) % WQ_SIZE)
2104 			snapshot->parallel.wq[i / sizeof(u32)] =
2105 				parallel_read(xe, map, wq[i / sizeof(u32)]);
2106 	}
2107 }
2108 
2109 static void
2110 guc_exec_queue_wq_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot,
2111 				 struct drm_printer *p)
2112 {
2113 	int i;
2114 
2115 	drm_printf(p, "\tWQ head: %u (internal), %d (memory)\n",
2116 		   snapshot->guc.wqi_head, snapshot->parallel.wq_desc.head);
2117 	drm_printf(p, "\tWQ tail: %u (internal), %d (memory)\n",
2118 		   snapshot->guc.wqi_tail, snapshot->parallel.wq_desc.tail);
2119 	drm_printf(p, "\tWQ status: %u\n", snapshot->parallel.wq_desc.status);
2120 
2121 	if (snapshot->parallel.wq_desc.head !=
2122 	    snapshot->parallel.wq_desc.tail) {
2123 		for (i = snapshot->parallel.wq_desc.head;
2124 		     i != snapshot->parallel.wq_desc.tail;
2125 		     i = (i + sizeof(u32)) % WQ_SIZE)
2126 			drm_printf(p, "\tWQ[%zu]: 0x%08x\n", i / sizeof(u32),
2127 				   snapshot->parallel.wq[i / sizeof(u32)]);
2128 	}
2129 }
2130 
2131 /**
2132  * xe_guc_exec_queue_snapshot_capture - Take a quick snapshot of the GuC Engine.
2133  * @q: faulty exec queue
2134  *
2135  * This can be printed out in a later stage like during dev_coredump
2136  * analysis.
2137  *
2138  * Returns: a GuC Submit Engine snapshot object that must be freed by the
2139  * caller, using `xe_guc_exec_queue_snapshot_free`.
2140  */
2141 struct xe_guc_submit_exec_queue_snapshot *
2142 xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q)
2143 {
2144 	struct xe_gpu_scheduler *sched = &q->guc->sched;
2145 	struct xe_guc_submit_exec_queue_snapshot *snapshot;
2146 	int i;
2147 
2148 	snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC);
2149 
2150 	if (!snapshot)
2151 		return NULL;
2152 
2153 	snapshot->guc.id = q->guc->id;
2154 	memcpy(&snapshot->name, &q->name, sizeof(snapshot->name));
2155 	snapshot->class = q->class;
2156 	snapshot->logical_mask = q->logical_mask;
2157 	snapshot->width = q->width;
2158 	snapshot->refcount = kref_read(&q->refcount);
2159 	snapshot->sched_timeout = sched->base.timeout;
2160 	snapshot->sched_props.timeslice_us = q->sched_props.timeslice_us;
2161 	snapshot->sched_props.preempt_timeout_us =
2162 		q->sched_props.preempt_timeout_us;
2163 
2164 	snapshot->lrc = kmalloc_array(q->width, sizeof(struct xe_lrc_snapshot *),
2165 				      GFP_ATOMIC);
2166 
2167 	if (snapshot->lrc) {
2168 		for (i = 0; i < q->width; ++i) {
2169 			struct xe_lrc *lrc = q->lrc[i];
2170 
2171 			snapshot->lrc[i] = xe_lrc_snapshot_capture(lrc);
2172 		}
2173 	}
2174 
2175 	snapshot->schedule_state = atomic_read(&q->guc->state);
2176 	snapshot->exec_queue_flags = q->flags;
2177 
2178 	snapshot->parallel_execution = xe_exec_queue_is_parallel(q);
2179 	if (snapshot->parallel_execution)
2180 		guc_exec_queue_wq_snapshot_capture(q, snapshot);
2181 
2182 	spin_lock(&sched->base.job_list_lock);
2183 	snapshot->pending_list_size = list_count_nodes(&sched->base.pending_list);
2184 	snapshot->pending_list = kmalloc_array(snapshot->pending_list_size,
2185 					       sizeof(struct pending_list_snapshot),
2186 					       GFP_ATOMIC);
2187 
2188 	if (snapshot->pending_list) {
2189 		struct xe_sched_job *job_iter;
2190 
2191 		i = 0;
2192 		list_for_each_entry(job_iter, &sched->base.pending_list, drm.list) {
2193 			snapshot->pending_list[i].seqno =
2194 				xe_sched_job_seqno(job_iter);
2195 			snapshot->pending_list[i].fence =
2196 				dma_fence_is_signaled(job_iter->fence) ? 1 : 0;
2197 			snapshot->pending_list[i].finished =
2198 				dma_fence_is_signaled(&job_iter->drm.s_fence->finished)
2199 				? 1 : 0;
2200 			i++;
2201 		}
2202 	}
2203 
2204 	spin_unlock(&sched->base.job_list_lock);
2205 
2206 	return snapshot;
2207 }
2208 
2209 /**
2210  * xe_guc_exec_queue_snapshot_capture_delayed - Take delayed part of snapshot of the GuC Engine.
2211  * @snapshot: Previously captured snapshot of job.
2212  *
2213  * This captures some data that requires taking some locks, so it cannot be done in signaling path.
2214  */
2215 void
2216 xe_guc_exec_queue_snapshot_capture_delayed(struct xe_guc_submit_exec_queue_snapshot *snapshot)
2217 {
2218 	int i;
2219 
2220 	if (!snapshot || !snapshot->lrc)
2221 		return;
2222 
2223 	for (i = 0; i < snapshot->width; ++i)
2224 		xe_lrc_snapshot_capture_delayed(snapshot->lrc[i]);
2225 }
2226 
2227 /**
2228  * xe_guc_exec_queue_snapshot_print - Print out a given GuC Engine snapshot.
2229  * @snapshot: GuC Submit Engine snapshot object.
2230  * @p: drm_printer where it will be printed out.
2231  *
2232  * This function prints out a given GuC Submit Engine snapshot object.
2233  */
2234 void
2235 xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot,
2236 				 struct drm_printer *p)
2237 {
2238 	int i;
2239 
2240 	if (!snapshot)
2241 		return;
2242 
2243 	drm_printf(p, "\nGuC ID: %d\n", snapshot->guc.id);
2244 	drm_printf(p, "\tName: %s\n", snapshot->name);
2245 	drm_printf(p, "\tClass: %d\n", snapshot->class);
2246 	drm_printf(p, "\tLogical mask: 0x%x\n", snapshot->logical_mask);
2247 	drm_printf(p, "\tWidth: %d\n", snapshot->width);
2248 	drm_printf(p, "\tRef: %d\n", snapshot->refcount);
2249 	drm_printf(p, "\tTimeout: %ld (ms)\n", snapshot->sched_timeout);
2250 	drm_printf(p, "\tTimeslice: %u (us)\n",
2251 		   snapshot->sched_props.timeslice_us);
2252 	drm_printf(p, "\tPreempt timeout: %u (us)\n",
2253 		   snapshot->sched_props.preempt_timeout_us);
2254 
2255 	for (i = 0; snapshot->lrc && i < snapshot->width; ++i)
2256 		xe_lrc_snapshot_print(snapshot->lrc[i], p);
2257 
2258 	drm_printf(p, "\tSchedule State: 0x%x\n", snapshot->schedule_state);
2259 	drm_printf(p, "\tFlags: 0x%lx\n", snapshot->exec_queue_flags);
2260 
2261 	if (snapshot->parallel_execution)
2262 		guc_exec_queue_wq_snapshot_print(snapshot, p);
2263 
2264 	for (i = 0; snapshot->pending_list && i < snapshot->pending_list_size;
2265 	     i++)
2266 		drm_printf(p, "\tJob: seqno=%d, fence=%d, finished=%d\n",
2267 			   snapshot->pending_list[i].seqno,
2268 			   snapshot->pending_list[i].fence,
2269 			   snapshot->pending_list[i].finished);
2270 }
2271 
2272 /**
2273  * xe_guc_exec_queue_snapshot_free - Free all allocated objects for a given
2274  * snapshot.
2275  * @snapshot: GuC Submit Engine snapshot object.
2276  *
2277  * This function free all the memory that needed to be allocated at capture
2278  * time.
2279  */
2280 void xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot)
2281 {
2282 	int i;
2283 
2284 	if (!snapshot)
2285 		return;
2286 
2287 	if (snapshot->lrc) {
2288 		for (i = 0; i < snapshot->width; i++)
2289 			xe_lrc_snapshot_free(snapshot->lrc[i]);
2290 		kfree(snapshot->lrc);
2291 	}
2292 	kfree(snapshot->pending_list);
2293 	kfree(snapshot);
2294 }
2295 
2296 static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p)
2297 {
2298 	struct xe_guc_submit_exec_queue_snapshot *snapshot;
2299 
2300 	snapshot = xe_guc_exec_queue_snapshot_capture(q);
2301 	xe_guc_exec_queue_snapshot_print(snapshot, p);
2302 	xe_guc_exec_queue_snapshot_free(snapshot);
2303 }
2304 
2305 /**
2306  * xe_guc_submit_print - GuC Submit Print.
2307  * @guc: GuC.
2308  * @p: drm_printer where it will be printed out.
2309  *
2310  * This function capture and prints snapshots of **all** GuC Engines.
2311  */
2312 void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p)
2313 {
2314 	struct xe_exec_queue *q;
2315 	unsigned long index;
2316 
2317 	if (!xe_device_uc_enabled(guc_to_xe(guc)))
2318 		return;
2319 
2320 	mutex_lock(&guc->submission_state.lock);
2321 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
2322 		guc_exec_queue_print(q, p);
2323 	mutex_unlock(&guc->submission_state.lock);
2324 }
2325