1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc_pc.h" 7 8 #include <linux/delay.h> 9 10 #include <drm/drm_managed.h> 11 #include <drm/drm_print.h> 12 #include <generated/xe_wa_oob.h> 13 14 #include "abi/guc_actions_slpc_abi.h" 15 #include "regs/xe_gt_regs.h" 16 #include "regs/xe_regs.h" 17 #include "xe_bo.h" 18 #include "xe_device.h" 19 #include "xe_force_wake.h" 20 #include "xe_gt.h" 21 #include "xe_gt_idle.h" 22 #include "xe_gt_printk.h" 23 #include "xe_gt_types.h" 24 #include "xe_guc.h" 25 #include "xe_guc_ct.h" 26 #include "xe_map.h" 27 #include "xe_mmio.h" 28 #include "xe_pcode.h" 29 #include "xe_pm.h" 30 #include "xe_sriov.h" 31 #include "xe_wa.h" 32 33 #define MCHBAR_MIRROR_BASE_SNB 0x140000 34 35 #define RP_STATE_CAP XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998) 36 #define RP0_MASK REG_GENMASK(7, 0) 37 #define RP1_MASK REG_GENMASK(15, 8) 38 #define RPN_MASK REG_GENMASK(23, 16) 39 40 #define FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0) 41 #define RPE_MASK REG_GENMASK(15, 8) 42 #define RPA_MASK REG_GENMASK(31, 16) 43 44 #define GT_PERF_STATUS XE_REG(0x1381b4) 45 #define CAGF_MASK REG_GENMASK(19, 11) 46 47 #define GT_FREQUENCY_MULTIPLIER 50 48 #define GT_FREQUENCY_SCALER 3 49 50 #define LNL_MERT_FREQ_CAP 800 51 #define BMG_MERT_FREQ_CAP 2133 52 53 /** 54 * DOC: GuC Power Conservation (PC) 55 * 56 * GuC Power Conservation (PC) supports multiple features for the most 57 * efficient and performing use of the GT when GuC submission is enabled, 58 * including frequency management, Render-C states management, and various 59 * algorithms for power balancing. 60 * 61 * Single Loop Power Conservation (SLPC) is the name given to the suite of 62 * connected power conservation features in the GuC firmware. The firmware 63 * exposes a programming interface to the host for the control of SLPC. 64 * 65 * Frequency management: 66 * ===================== 67 * 68 * Xe driver enables SLPC with all of its defaults features and frequency 69 * selection, which varies per platform. 70 * 71 * Render-C States: 72 * ================ 73 * 74 * Render-C states is also a GuC PC feature that is now enabled in Xe for 75 * all platforms. 76 * 77 */ 78 79 static struct xe_guc *pc_to_guc(struct xe_guc_pc *pc) 80 { 81 return container_of(pc, struct xe_guc, pc); 82 } 83 84 static struct xe_guc_ct *pc_to_ct(struct xe_guc_pc *pc) 85 { 86 return &pc_to_guc(pc)->ct; 87 } 88 89 static struct xe_gt *pc_to_gt(struct xe_guc_pc *pc) 90 { 91 return guc_to_gt(pc_to_guc(pc)); 92 } 93 94 static struct xe_device *pc_to_xe(struct xe_guc_pc *pc) 95 { 96 return guc_to_xe(pc_to_guc(pc)); 97 } 98 99 static struct iosys_map *pc_to_maps(struct xe_guc_pc *pc) 100 { 101 return &pc->bo->vmap; 102 } 103 104 #define slpc_shared_data_read(pc_, field_) \ 105 xe_map_rd_field(pc_to_xe(pc_), pc_to_maps(pc_), 0, \ 106 struct slpc_shared_data, field_) 107 108 #define slpc_shared_data_write(pc_, field_, val_) \ 109 xe_map_wr_field(pc_to_xe(pc_), pc_to_maps(pc_), 0, \ 110 struct slpc_shared_data, field_, val_) 111 112 #define SLPC_EVENT(id, count) \ 113 (FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \ 114 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, count)) 115 116 static int wait_for_pc_state(struct xe_guc_pc *pc, 117 enum slpc_global_state state) 118 { 119 int timeout_us = 5000; /* rought 5ms, but no need for precision */ 120 int slept, wait = 10; 121 122 xe_device_assert_mem_access(pc_to_xe(pc)); 123 124 for (slept = 0; slept < timeout_us;) { 125 if (slpc_shared_data_read(pc, header.global_state) == state) 126 return 0; 127 128 usleep_range(wait, wait << 1); 129 slept += wait; 130 wait <<= 1; 131 if (slept + wait > timeout_us) 132 wait = timeout_us - slept; 133 } 134 135 return -ETIMEDOUT; 136 } 137 138 static int pc_action_reset(struct xe_guc_pc *pc) 139 { 140 struct xe_guc_ct *ct = pc_to_ct(pc); 141 u32 action[] = { 142 GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, 143 SLPC_EVENT(SLPC_EVENT_RESET, 2), 144 xe_bo_ggtt_addr(pc->bo), 145 0, 146 }; 147 int ret; 148 149 ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); 150 if (ret) 151 xe_gt_err(pc_to_gt(pc), "GuC PC reset failed: %pe\n", 152 ERR_PTR(ret)); 153 154 return ret; 155 } 156 157 static int pc_action_query_task_state(struct xe_guc_pc *pc) 158 { 159 struct xe_guc_ct *ct = pc_to_ct(pc); 160 u32 action[] = { 161 GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, 162 SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2), 163 xe_bo_ggtt_addr(pc->bo), 164 0, 165 }; 166 int ret; 167 168 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) 169 return -EAGAIN; 170 171 /* Blocking here to ensure the results are ready before reading them */ 172 ret = xe_guc_ct_send_block(ct, action, ARRAY_SIZE(action)); 173 if (ret) 174 xe_gt_err(pc_to_gt(pc), "GuC PC query task state failed: %pe\n", 175 ERR_PTR(ret)); 176 177 return ret; 178 } 179 180 static int pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value) 181 { 182 struct xe_guc_ct *ct = pc_to_ct(pc); 183 u32 action[] = { 184 GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, 185 SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2), 186 id, 187 value, 188 }; 189 int ret; 190 191 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) 192 return -EAGAIN; 193 194 ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); 195 if (ret) 196 xe_gt_err(pc_to_gt(pc), "GuC PC set param[%u]=%u failed: %pe\n", 197 id, value, ERR_PTR(ret)); 198 199 return ret; 200 } 201 202 static int pc_action_unset_param(struct xe_guc_pc *pc, u8 id) 203 { 204 u32 action[] = { 205 GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, 206 SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1), 207 id, 208 }; 209 struct xe_guc_ct *ct = &pc_to_guc(pc)->ct; 210 int ret; 211 212 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) 213 return -EAGAIN; 214 215 ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); 216 if (ret) 217 xe_gt_err(pc_to_gt(pc), "GuC PC unset param failed: %pe", 218 ERR_PTR(ret)); 219 220 return ret; 221 } 222 223 static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode) 224 { 225 struct xe_guc_ct *ct = pc_to_ct(pc); 226 u32 action[] = { 227 GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC, 228 mode, 229 }; 230 int ret; 231 232 ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); 233 if (ret) 234 xe_gt_err(pc_to_gt(pc), "GuC RC enable mode=%u failed: %pe\n", 235 mode, ERR_PTR(ret)); 236 return ret; 237 } 238 239 static u32 decode_freq(u32 raw) 240 { 241 return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER, 242 GT_FREQUENCY_SCALER); 243 } 244 245 static u32 encode_freq(u32 freq) 246 { 247 return DIV_ROUND_CLOSEST(freq * GT_FREQUENCY_SCALER, 248 GT_FREQUENCY_MULTIPLIER); 249 } 250 251 static u32 pc_get_min_freq(struct xe_guc_pc *pc) 252 { 253 u32 freq; 254 255 freq = FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK, 256 slpc_shared_data_read(pc, task_state_data.freq)); 257 258 return decode_freq(freq); 259 } 260 261 static void pc_set_manual_rp_ctrl(struct xe_guc_pc *pc, bool enable) 262 { 263 struct xe_gt *gt = pc_to_gt(pc); 264 u32 state = enable ? RPSWCTL_ENABLE : RPSWCTL_DISABLE; 265 266 /* Allow/Disallow punit to process software freq requests */ 267 xe_mmio_write32(>->mmio, RP_CONTROL, state); 268 } 269 270 static void pc_set_cur_freq(struct xe_guc_pc *pc, u32 freq) 271 { 272 struct xe_gt *gt = pc_to_gt(pc); 273 u32 rpnswreq; 274 275 pc_set_manual_rp_ctrl(pc, true); 276 277 /* Req freq is in units of 16.66 Mhz */ 278 rpnswreq = REG_FIELD_PREP(REQ_RATIO_MASK, encode_freq(freq)); 279 xe_mmio_write32(>->mmio, RPNSWREQ, rpnswreq); 280 281 /* Sleep for a small time to allow pcode to respond */ 282 usleep_range(100, 300); 283 284 pc_set_manual_rp_ctrl(pc, false); 285 } 286 287 static int pc_set_min_freq(struct xe_guc_pc *pc, u32 freq) 288 { 289 /* 290 * Let's only check for the rpn-rp0 range. If max < min, 291 * min becomes a fixed request. 292 */ 293 if (freq < pc->rpn_freq || freq > pc->rp0_freq) 294 return -EINVAL; 295 296 /* 297 * GuC policy is to elevate minimum frequency to the efficient levels 298 * Our goal is to have the admin choices respected. 299 */ 300 pc_action_set_param(pc, SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY, 301 freq < pc->rpe_freq); 302 303 return pc_action_set_param(pc, 304 SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, 305 freq); 306 } 307 308 static int pc_get_max_freq(struct xe_guc_pc *pc) 309 { 310 u32 freq; 311 312 freq = FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK, 313 slpc_shared_data_read(pc, task_state_data.freq)); 314 315 return decode_freq(freq); 316 } 317 318 static int pc_set_max_freq(struct xe_guc_pc *pc, u32 freq) 319 { 320 /* 321 * Let's only check for the rpn-rp0 range. If max < min, 322 * min becomes a fixed request. 323 * Also, overclocking is not supported. 324 */ 325 if (freq < pc->rpn_freq || freq > pc->rp0_freq) 326 return -EINVAL; 327 328 return pc_action_set_param(pc, 329 SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ, 330 freq); 331 } 332 333 static void mtl_update_rpa_value(struct xe_guc_pc *pc) 334 { 335 struct xe_gt *gt = pc_to_gt(pc); 336 u32 reg; 337 338 if (xe_gt_is_media_type(gt)) 339 reg = xe_mmio_read32(>->mmio, MTL_MPA_FREQUENCY); 340 else 341 reg = xe_mmio_read32(>->mmio, MTL_GT_RPA_FREQUENCY); 342 343 pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg)); 344 } 345 346 static void mtl_update_rpe_value(struct xe_guc_pc *pc) 347 { 348 struct xe_gt *gt = pc_to_gt(pc); 349 u32 reg; 350 351 if (xe_gt_is_media_type(gt)) 352 reg = xe_mmio_read32(>->mmio, MTL_MPE_FREQUENCY); 353 else 354 reg = xe_mmio_read32(>->mmio, MTL_GT_RPE_FREQUENCY); 355 356 pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg)); 357 } 358 359 static void tgl_update_rpa_value(struct xe_guc_pc *pc) 360 { 361 struct xe_gt *gt = pc_to_gt(pc); 362 struct xe_device *xe = gt_to_xe(gt); 363 u32 reg; 364 365 /* 366 * For PVC we still need to use fused RP0 as the approximation for RPa 367 * For other platforms than PVC we get the resolved RPa directly from 368 * PCODE at a different register 369 */ 370 if (xe->info.platform == XE_PVC) { 371 reg = xe_mmio_read32(>->mmio, PVC_RP_STATE_CAP); 372 pc->rpa_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER; 373 } else { 374 reg = xe_mmio_read32(>->mmio, FREQ_INFO_REC); 375 pc->rpa_freq = REG_FIELD_GET(RPA_MASK, reg) * GT_FREQUENCY_MULTIPLIER; 376 } 377 } 378 379 static void tgl_update_rpe_value(struct xe_guc_pc *pc) 380 { 381 struct xe_gt *gt = pc_to_gt(pc); 382 struct xe_device *xe = gt_to_xe(gt); 383 u32 reg; 384 385 /* 386 * For PVC we still need to use fused RP1 as the approximation for RPe 387 * For other platforms than PVC we get the resolved RPe directly from 388 * PCODE at a different register 389 */ 390 if (xe->info.platform == XE_PVC) { 391 reg = xe_mmio_read32(>->mmio, PVC_RP_STATE_CAP); 392 pc->rpe_freq = REG_FIELD_GET(RP1_MASK, reg) * GT_FREQUENCY_MULTIPLIER; 393 } else { 394 reg = xe_mmio_read32(>->mmio, FREQ_INFO_REC); 395 pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER; 396 } 397 } 398 399 static void pc_update_rp_values(struct xe_guc_pc *pc) 400 { 401 struct xe_gt *gt = pc_to_gt(pc); 402 struct xe_device *xe = gt_to_xe(gt); 403 404 if (GRAPHICS_VERx100(xe) >= 1270) { 405 mtl_update_rpa_value(pc); 406 mtl_update_rpe_value(pc); 407 } else { 408 tgl_update_rpa_value(pc); 409 tgl_update_rpe_value(pc); 410 } 411 412 /* 413 * RPe is decided at runtime by PCODE. In the rare case where that's 414 * smaller than the fused min, we will trust the PCODE and use that 415 * as our minimum one. 416 */ 417 pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq); 418 } 419 420 /** 421 * xe_guc_pc_get_act_freq - Get Actual running frequency 422 * @pc: The GuC PC 423 * 424 * Returns: The Actual running frequency. Which might be 0 if GT is in Render-C sleep state (RC6). 425 */ 426 u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc) 427 { 428 struct xe_gt *gt = pc_to_gt(pc); 429 struct xe_device *xe = gt_to_xe(gt); 430 u32 freq; 431 432 /* When in RC6, actual frequency reported will be 0. */ 433 if (GRAPHICS_VERx100(xe) >= 1270) { 434 freq = xe_mmio_read32(>->mmio, MTL_MIRROR_TARGET_WP1); 435 freq = REG_FIELD_GET(MTL_CAGF_MASK, freq); 436 } else { 437 freq = xe_mmio_read32(>->mmio, GT_PERF_STATUS); 438 freq = REG_FIELD_GET(CAGF_MASK, freq); 439 } 440 441 freq = decode_freq(freq); 442 443 return freq; 444 } 445 446 /** 447 * xe_guc_pc_get_cur_freq - Get Current requested frequency 448 * @pc: The GuC PC 449 * @freq: A pointer to a u32 where the freq value will be returned 450 * 451 * Returns: 0 on success, 452 * -EAGAIN if GuC PC not ready (likely in middle of a reset). 453 */ 454 int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq) 455 { 456 struct xe_gt *gt = pc_to_gt(pc); 457 unsigned int fw_ref; 458 459 /* 460 * GuC SLPC plays with cur freq request when GuCRC is enabled 461 * Block RC6 for a more reliable read. 462 */ 463 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 464 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FW_GT)) { 465 xe_force_wake_put(gt_to_fw(gt), fw_ref); 466 return -ETIMEDOUT; 467 } 468 469 *freq = xe_mmio_read32(>->mmio, RPNSWREQ); 470 471 *freq = REG_FIELD_GET(REQ_RATIO_MASK, *freq); 472 *freq = decode_freq(*freq); 473 474 xe_force_wake_put(gt_to_fw(gt), fw_ref); 475 return 0; 476 } 477 478 /** 479 * xe_guc_pc_get_rp0_freq - Get the RP0 freq 480 * @pc: The GuC PC 481 * 482 * Returns: RP0 freq. 483 */ 484 u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc) 485 { 486 return pc->rp0_freq; 487 } 488 489 /** 490 * xe_guc_pc_get_rpa_freq - Get the RPa freq 491 * @pc: The GuC PC 492 * 493 * Returns: RPa freq. 494 */ 495 u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc) 496 { 497 pc_update_rp_values(pc); 498 499 return pc->rpa_freq; 500 } 501 502 /** 503 * xe_guc_pc_get_rpe_freq - Get the RPe freq 504 * @pc: The GuC PC 505 * 506 * Returns: RPe freq. 507 */ 508 u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc) 509 { 510 pc_update_rp_values(pc); 511 512 return pc->rpe_freq; 513 } 514 515 /** 516 * xe_guc_pc_get_rpn_freq - Get the RPn freq 517 * @pc: The GuC PC 518 * 519 * Returns: RPn freq. 520 */ 521 u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc) 522 { 523 return pc->rpn_freq; 524 } 525 526 /** 527 * xe_guc_pc_get_min_freq - Get the min operational frequency 528 * @pc: The GuC PC 529 * @freq: A pointer to a u32 where the freq value will be returned 530 * 531 * Returns: 0 on success, 532 * -EAGAIN if GuC PC not ready (likely in middle of a reset). 533 */ 534 int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq) 535 { 536 int ret; 537 538 xe_device_assert_mem_access(pc_to_xe(pc)); 539 540 mutex_lock(&pc->freq_lock); 541 if (!pc->freq_ready) { 542 /* Might be in the middle of a gt reset */ 543 ret = -EAGAIN; 544 goto out; 545 } 546 547 ret = pc_action_query_task_state(pc); 548 if (ret) 549 goto out; 550 551 *freq = pc_get_min_freq(pc); 552 553 out: 554 mutex_unlock(&pc->freq_lock); 555 return ret; 556 } 557 558 /** 559 * xe_guc_pc_set_min_freq - Set the minimal operational frequency 560 * @pc: The GuC PC 561 * @freq: The selected minimal frequency 562 * 563 * Returns: 0 on success, 564 * -EAGAIN if GuC PC not ready (likely in middle of a reset), 565 * -EINVAL if value out of bounds. 566 */ 567 int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq) 568 { 569 int ret; 570 571 mutex_lock(&pc->freq_lock); 572 if (!pc->freq_ready) { 573 /* Might be in the middle of a gt reset */ 574 ret = -EAGAIN; 575 goto out; 576 } 577 578 ret = pc_set_min_freq(pc, freq); 579 if (ret) 580 goto out; 581 582 pc->user_requested_min = freq; 583 584 out: 585 mutex_unlock(&pc->freq_lock); 586 return ret; 587 } 588 589 /** 590 * xe_guc_pc_get_max_freq - Get Maximum operational frequency 591 * @pc: The GuC PC 592 * @freq: A pointer to a u32 where the freq value will be returned 593 * 594 * Returns: 0 on success, 595 * -EAGAIN if GuC PC not ready (likely in middle of a reset). 596 */ 597 int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq) 598 { 599 int ret; 600 601 mutex_lock(&pc->freq_lock); 602 if (!pc->freq_ready) { 603 /* Might be in the middle of a gt reset */ 604 ret = -EAGAIN; 605 goto out; 606 } 607 608 ret = pc_action_query_task_state(pc); 609 if (ret) 610 goto out; 611 612 *freq = pc_get_max_freq(pc); 613 614 out: 615 mutex_unlock(&pc->freq_lock); 616 return ret; 617 } 618 619 /** 620 * xe_guc_pc_set_max_freq - Set the maximum operational frequency 621 * @pc: The GuC PC 622 * @freq: The selected maximum frequency value 623 * 624 * Returns: 0 on success, 625 * -EAGAIN if GuC PC not ready (likely in middle of a reset), 626 * -EINVAL if value out of bounds. 627 */ 628 int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq) 629 { 630 int ret; 631 632 mutex_lock(&pc->freq_lock); 633 if (!pc->freq_ready) { 634 /* Might be in the middle of a gt reset */ 635 ret = -EAGAIN; 636 goto out; 637 } 638 639 ret = pc_set_max_freq(pc, freq); 640 if (ret) 641 goto out; 642 643 pc->user_requested_max = freq; 644 645 out: 646 mutex_unlock(&pc->freq_lock); 647 return ret; 648 } 649 650 /** 651 * xe_guc_pc_c_status - get the current GT C state 652 * @pc: XE_GuC_PC instance 653 */ 654 enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc) 655 { 656 struct xe_gt *gt = pc_to_gt(pc); 657 u32 reg, gt_c_state; 658 659 if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) { 660 reg = xe_mmio_read32(>->mmio, MTL_MIRROR_TARGET_WP1); 661 gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg); 662 } else { 663 reg = xe_mmio_read32(>->mmio, GT_CORE_STATUS); 664 gt_c_state = REG_FIELD_GET(RCN_MASK, reg); 665 } 666 667 switch (gt_c_state) { 668 case GT_C6: 669 return GT_IDLE_C6; 670 case GT_C0: 671 return GT_IDLE_C0; 672 default: 673 return GT_IDLE_UNKNOWN; 674 } 675 } 676 677 /** 678 * xe_guc_pc_rc6_residency - rc6 residency counter 679 * @pc: Xe_GuC_PC instance 680 */ 681 u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc) 682 { 683 struct xe_gt *gt = pc_to_gt(pc); 684 u32 reg; 685 686 reg = xe_mmio_read32(>->mmio, GT_GFX_RC6); 687 688 return reg; 689 } 690 691 /** 692 * xe_guc_pc_mc6_residency - mc6 residency counter 693 * @pc: Xe_GuC_PC instance 694 */ 695 u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc) 696 { 697 struct xe_gt *gt = pc_to_gt(pc); 698 u64 reg; 699 700 reg = xe_mmio_read32(>->mmio, MTL_MEDIA_MC6); 701 702 return reg; 703 } 704 705 static void mtl_init_fused_rp_values(struct xe_guc_pc *pc) 706 { 707 struct xe_gt *gt = pc_to_gt(pc); 708 u32 reg; 709 710 xe_device_assert_mem_access(pc_to_xe(pc)); 711 712 if (xe_gt_is_media_type(gt)) 713 reg = xe_mmio_read32(>->mmio, MTL_MEDIAP_STATE_CAP); 714 else 715 reg = xe_mmio_read32(>->mmio, MTL_RP_STATE_CAP); 716 717 pc->rp0_freq = decode_freq(REG_FIELD_GET(MTL_RP0_CAP_MASK, reg)); 718 719 pc->rpn_freq = decode_freq(REG_FIELD_GET(MTL_RPN_CAP_MASK, reg)); 720 } 721 722 static void tgl_init_fused_rp_values(struct xe_guc_pc *pc) 723 { 724 struct xe_gt *gt = pc_to_gt(pc); 725 struct xe_device *xe = gt_to_xe(gt); 726 u32 reg; 727 728 xe_device_assert_mem_access(pc_to_xe(pc)); 729 730 if (xe->info.platform == XE_PVC) 731 reg = xe_mmio_read32(>->mmio, PVC_RP_STATE_CAP); 732 else 733 reg = xe_mmio_read32(>->mmio, RP_STATE_CAP); 734 pc->rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER; 735 pc->rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER; 736 } 737 738 static void pc_init_fused_rp_values(struct xe_guc_pc *pc) 739 { 740 struct xe_gt *gt = pc_to_gt(pc); 741 struct xe_device *xe = gt_to_xe(gt); 742 743 if (GRAPHICS_VERx100(xe) >= 1270) 744 mtl_init_fused_rp_values(pc); 745 else 746 tgl_init_fused_rp_values(pc); 747 } 748 749 static u32 pc_max_freq_cap(struct xe_guc_pc *pc) 750 { 751 struct xe_gt *gt = pc_to_gt(pc); 752 753 if (XE_WA(gt, 22019338487)) { 754 if (xe_gt_is_media_type(gt)) 755 return min(LNL_MERT_FREQ_CAP, pc->rp0_freq); 756 else 757 return min(BMG_MERT_FREQ_CAP, pc->rp0_freq); 758 } else { 759 return pc->rp0_freq; 760 } 761 } 762 763 /** 764 * xe_guc_pc_raise_unslice - Initialize RPx values and request a higher GT 765 * frequency to allow faster GuC load times 766 * @pc: Xe_GuC_PC instance 767 */ 768 void xe_guc_pc_raise_unslice(struct xe_guc_pc *pc) 769 { 770 struct xe_gt *gt = pc_to_gt(pc); 771 772 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 773 pc_set_cur_freq(pc, pc_max_freq_cap(pc)); 774 } 775 776 /** 777 * xe_guc_pc_init_early - Initialize RPx values 778 * @pc: Xe_GuC_PC instance 779 */ 780 void xe_guc_pc_init_early(struct xe_guc_pc *pc) 781 { 782 struct xe_gt *gt = pc_to_gt(pc); 783 784 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 785 pc_init_fused_rp_values(pc); 786 } 787 788 static int pc_adjust_freq_bounds(struct xe_guc_pc *pc) 789 { 790 int ret; 791 792 lockdep_assert_held(&pc->freq_lock); 793 794 ret = pc_action_query_task_state(pc); 795 if (ret) 796 goto out; 797 798 /* 799 * GuC defaults to some RPmax that is not actually achievable without 800 * overclocking. Let's adjust it to the Hardware RP0, which is the 801 * regular maximum 802 */ 803 if (pc_get_max_freq(pc) > pc->rp0_freq) { 804 ret = pc_set_max_freq(pc, pc->rp0_freq); 805 if (ret) 806 goto out; 807 } 808 809 /* 810 * Same thing happens for Server platforms where min is listed as 811 * RPMax 812 */ 813 if (pc_get_min_freq(pc) > pc->rp0_freq) 814 ret = pc_set_min_freq(pc, pc->rp0_freq); 815 816 out: 817 return ret; 818 } 819 820 static int pc_adjust_requested_freq(struct xe_guc_pc *pc) 821 { 822 int ret = 0; 823 824 lockdep_assert_held(&pc->freq_lock); 825 826 if (pc->user_requested_min != 0) { 827 ret = pc_set_min_freq(pc, pc->user_requested_min); 828 if (ret) 829 return ret; 830 } 831 832 if (pc->user_requested_max != 0) { 833 ret = pc_set_max_freq(pc, pc->user_requested_max); 834 if (ret) 835 return ret; 836 } 837 838 return ret; 839 } 840 841 static int pc_set_mert_freq_cap(struct xe_guc_pc *pc) 842 { 843 int ret = 0; 844 845 if (XE_WA(pc_to_gt(pc), 22019338487)) { 846 /* 847 * Get updated min/max and stash them. 848 */ 849 ret = xe_guc_pc_get_min_freq(pc, &pc->stashed_min_freq); 850 if (!ret) 851 ret = xe_guc_pc_get_max_freq(pc, &pc->stashed_max_freq); 852 if (ret) 853 return ret; 854 855 /* 856 * Ensure min and max are bound by MERT_FREQ_CAP until driver loads. 857 */ 858 mutex_lock(&pc->freq_lock); 859 ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc))); 860 if (!ret) 861 ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc))); 862 mutex_unlock(&pc->freq_lock); 863 } 864 865 return ret; 866 } 867 868 /** 869 * xe_guc_pc_restore_stashed_freq - Set min/max back to stashed values 870 * @pc: The GuC PC 871 * 872 * Returns: 0 on success, 873 * error code on failure 874 */ 875 int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc) 876 { 877 int ret = 0; 878 879 if (IS_SRIOV_VF(pc_to_xe(pc)) || pc_to_xe(pc)->info.skip_guc_pc) 880 return 0; 881 882 mutex_lock(&pc->freq_lock); 883 ret = pc_set_max_freq(pc, pc->stashed_max_freq); 884 if (!ret) 885 ret = pc_set_min_freq(pc, pc->stashed_min_freq); 886 mutex_unlock(&pc->freq_lock); 887 888 return ret; 889 } 890 891 /** 892 * xe_guc_pc_gucrc_disable - Disable GuC RC 893 * @pc: Xe_GuC_PC instance 894 * 895 * Disables GuC RC by taking control of RC6 back from GuC. 896 * 897 * Return: 0 on success, negative error code on error. 898 */ 899 int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc) 900 { 901 struct xe_device *xe = pc_to_xe(pc); 902 struct xe_gt *gt = pc_to_gt(pc); 903 unsigned int fw_ref; 904 int ret = 0; 905 906 if (xe->info.skip_guc_pc) 907 return 0; 908 909 ret = pc_action_setup_gucrc(pc, GUCRC_HOST_CONTROL); 910 if (ret) 911 return ret; 912 913 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 914 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 915 xe_force_wake_put(gt_to_fw(gt), fw_ref); 916 return -ETIMEDOUT; 917 } 918 919 xe_gt_idle_disable_c6(gt); 920 921 xe_force_wake_put(gt_to_fw(gt), fw_ref); 922 923 return 0; 924 } 925 926 /** 927 * xe_guc_pc_override_gucrc_mode - override GUCRC mode 928 * @pc: Xe_GuC_PC instance 929 * @mode: new value of the mode. 930 * 931 * Return: 0 on success, negative error code on error 932 */ 933 int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode) 934 { 935 int ret; 936 937 xe_pm_runtime_get(pc_to_xe(pc)); 938 ret = pc_action_set_param(pc, SLPC_PARAM_PWRGATE_RC_MODE, mode); 939 xe_pm_runtime_put(pc_to_xe(pc)); 940 941 return ret; 942 } 943 944 /** 945 * xe_guc_pc_unset_gucrc_mode - unset GUCRC mode override 946 * @pc: Xe_GuC_PC instance 947 * 948 * Return: 0 on success, negative error code on error 949 */ 950 int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc) 951 { 952 int ret; 953 954 xe_pm_runtime_get(pc_to_xe(pc)); 955 ret = pc_action_unset_param(pc, SLPC_PARAM_PWRGATE_RC_MODE); 956 xe_pm_runtime_put(pc_to_xe(pc)); 957 958 return ret; 959 } 960 961 static void pc_init_pcode_freq(struct xe_guc_pc *pc) 962 { 963 u32 min = DIV_ROUND_CLOSEST(pc->rpn_freq, GT_FREQUENCY_MULTIPLIER); 964 u32 max = DIV_ROUND_CLOSEST(pc->rp0_freq, GT_FREQUENCY_MULTIPLIER); 965 966 XE_WARN_ON(xe_pcode_init_min_freq_table(gt_to_tile(pc_to_gt(pc)), min, max)); 967 } 968 969 static int pc_init_freqs(struct xe_guc_pc *pc) 970 { 971 int ret; 972 973 mutex_lock(&pc->freq_lock); 974 975 ret = pc_adjust_freq_bounds(pc); 976 if (ret) 977 goto out; 978 979 ret = pc_adjust_requested_freq(pc); 980 if (ret) 981 goto out; 982 983 pc_update_rp_values(pc); 984 985 pc_init_pcode_freq(pc); 986 987 /* 988 * The frequencies are really ready for use only after the user 989 * requested ones got restored. 990 */ 991 pc->freq_ready = true; 992 993 out: 994 mutex_unlock(&pc->freq_lock); 995 return ret; 996 } 997 998 static int pc_action_set_strategy(struct xe_guc_pc *pc, u32 val) 999 { 1000 int ret = 0; 1001 1002 ret = pc_action_set_param(pc, 1003 SLPC_PARAM_STRATEGIES, 1004 val); 1005 1006 return ret; 1007 } 1008 1009 /** 1010 * xe_guc_pc_start - Start GuC's Power Conservation component 1011 * @pc: Xe_GuC_PC instance 1012 */ 1013 int xe_guc_pc_start(struct xe_guc_pc *pc) 1014 { 1015 struct xe_device *xe = pc_to_xe(pc); 1016 struct xe_gt *gt = pc_to_gt(pc); 1017 u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data)); 1018 unsigned int fw_ref; 1019 int ret; 1020 1021 xe_gt_assert(gt, xe_device_uc_enabled(xe)); 1022 1023 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1024 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FW_GT)) { 1025 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1026 return -ETIMEDOUT; 1027 } 1028 1029 if (xe->info.skip_guc_pc) { 1030 if (xe->info.platform != XE_PVC) 1031 xe_gt_idle_enable_c6(gt); 1032 1033 /* Request max possible since dynamic freq mgmt is not enabled */ 1034 pc_set_cur_freq(pc, UINT_MAX); 1035 1036 ret = 0; 1037 goto out; 1038 } 1039 1040 memset(pc->bo->vmap.vaddr, 0, size); 1041 slpc_shared_data_write(pc, header.size, size); 1042 1043 ret = pc_action_reset(pc); 1044 if (ret) 1045 goto out; 1046 1047 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) { 1048 xe_gt_err(gt, "GuC PC Start failed\n"); 1049 ret = -EIO; 1050 goto out; 1051 } 1052 1053 ret = pc_init_freqs(pc); 1054 if (ret) 1055 goto out; 1056 1057 ret = pc_set_mert_freq_cap(pc); 1058 if (ret) 1059 goto out; 1060 1061 if (xe->info.platform == XE_PVC) { 1062 xe_guc_pc_gucrc_disable(pc); 1063 ret = 0; 1064 goto out; 1065 } 1066 1067 ret = pc_action_setup_gucrc(pc, GUCRC_FIRMWARE_CONTROL); 1068 if (ret) 1069 goto out; 1070 1071 /* Enable SLPC Optimized Strategy for compute */ 1072 ret = pc_action_set_strategy(pc, SLPC_OPTIMIZED_STRATEGY_COMPUTE); 1073 1074 out: 1075 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1076 return ret; 1077 } 1078 1079 /** 1080 * xe_guc_pc_stop - Stop GuC's Power Conservation component 1081 * @pc: Xe_GuC_PC instance 1082 */ 1083 int xe_guc_pc_stop(struct xe_guc_pc *pc) 1084 { 1085 struct xe_device *xe = pc_to_xe(pc); 1086 1087 if (xe->info.skip_guc_pc) { 1088 xe_gt_idle_disable_c6(pc_to_gt(pc)); 1089 return 0; 1090 } 1091 1092 mutex_lock(&pc->freq_lock); 1093 pc->freq_ready = false; 1094 mutex_unlock(&pc->freq_lock); 1095 1096 return 0; 1097 } 1098 1099 /** 1100 * xe_guc_pc_fini_hw - Finalize GuC's Power Conservation component 1101 * @arg: opaque pointer that should point to Xe_GuC_PC instance 1102 */ 1103 static void xe_guc_pc_fini_hw(void *arg) 1104 { 1105 struct xe_guc_pc *pc = arg; 1106 struct xe_device *xe = pc_to_xe(pc); 1107 unsigned int fw_ref; 1108 1109 if (xe_device_wedged(xe)) 1110 return; 1111 1112 fw_ref = xe_force_wake_get(gt_to_fw(pc_to_gt(pc)), XE_FORCEWAKE_ALL); 1113 xe_guc_pc_gucrc_disable(pc); 1114 XE_WARN_ON(xe_guc_pc_stop(pc)); 1115 1116 /* Bind requested freq to mert_freq_cap before unload */ 1117 pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), pc->rpe_freq)); 1118 1119 xe_force_wake_put(gt_to_fw(pc_to_gt(pc)), fw_ref); 1120 } 1121 1122 /** 1123 * xe_guc_pc_init - Initialize GuC's Power Conservation component 1124 * @pc: Xe_GuC_PC instance 1125 */ 1126 int xe_guc_pc_init(struct xe_guc_pc *pc) 1127 { 1128 struct xe_gt *gt = pc_to_gt(pc); 1129 struct xe_tile *tile = gt_to_tile(gt); 1130 struct xe_device *xe = gt_to_xe(gt); 1131 struct xe_bo *bo; 1132 u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data)); 1133 int err; 1134 1135 if (xe->info.skip_guc_pc) 1136 return 0; 1137 1138 err = drmm_mutex_init(&xe->drm, &pc->freq_lock); 1139 if (err) 1140 return err; 1141 1142 bo = xe_managed_bo_create_pin_map(xe, tile, size, 1143 XE_BO_FLAG_VRAM_IF_DGFX(tile) | 1144 XE_BO_FLAG_GGTT | 1145 XE_BO_FLAG_GGTT_INVALIDATE); 1146 if (IS_ERR(bo)) 1147 return PTR_ERR(bo); 1148 1149 pc->bo = bo; 1150 1151 return devm_add_action_or_reset(xe->drm.dev, xe_guc_pc_fini_hw, pc); 1152 } 1153 1154 static const char *pc_get_state_string(struct xe_guc_pc *pc) 1155 { 1156 switch (slpc_shared_data_read(pc, header.global_state)) { 1157 case SLPC_GLOBAL_STATE_NOT_RUNNING: 1158 return "not running"; 1159 case SLPC_GLOBAL_STATE_INITIALIZING: 1160 return "initializing"; 1161 case SLPC_GLOBAL_STATE_RESETTING: 1162 return "resetting"; 1163 case SLPC_GLOBAL_STATE_RUNNING: 1164 return "running"; 1165 case SLPC_GLOBAL_STATE_SHUTTING_DOWN: 1166 return "shutting down"; 1167 case SLPC_GLOBAL_STATE_ERROR: 1168 return "error"; 1169 default: 1170 return "unknown"; 1171 } 1172 } 1173 1174 /** 1175 * xe_guc_pc_print - Print GuC's Power Conservation information for debug 1176 * @pc: Xe_GuC_PC instance 1177 * @p: drm_printer 1178 */ 1179 void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p) 1180 { 1181 drm_printf(p, "SLPC Shared Data Header:\n"); 1182 drm_printf(p, "\tSize: %x\n", slpc_shared_data_read(pc, header.size)); 1183 drm_printf(p, "\tGlobal State: %s\n", pc_get_state_string(pc)); 1184 1185 if (pc_action_query_task_state(pc)) 1186 return; 1187 1188 drm_printf(p, "\nSLPC Tasks Status:\n"); 1189 drm_printf(p, "\tGTPERF enabled: %s\n", 1190 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1191 SLPC_GTPERF_TASK_ENABLED)); 1192 drm_printf(p, "\tDCC enabled: %s\n", 1193 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1194 SLPC_DCC_TASK_ENABLED)); 1195 drm_printf(p, "\tDCC in use: %s\n", 1196 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1197 SLPC_IN_DCC)); 1198 drm_printf(p, "\tBalancer enabled: %s\n", 1199 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1200 SLPC_BALANCER_ENABLED)); 1201 drm_printf(p, "\tIBC enabled: %s\n", 1202 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1203 SLPC_IBC_TASK_ENABLED)); 1204 drm_printf(p, "\tBalancer IA LMT enabled: %s\n", 1205 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1206 SLPC_BALANCER_IA_LMT_ENABLED)); 1207 drm_printf(p, "\tBalancer IA LMT active: %s\n", 1208 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1209 SLPC_BALANCER_IA_LMT_ACTIVE)); 1210 } 1211