1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc_pc.h" 7 8 #include <linux/delay.h> 9 10 #include <drm/drm_managed.h> 11 #include <drm/drm_print.h> 12 #include <generated/xe_wa_oob.h> 13 14 #include "abi/guc_actions_slpc_abi.h" 15 #include "regs/xe_gt_regs.h" 16 #include "regs/xe_regs.h" 17 #include "xe_bo.h" 18 #include "xe_device.h" 19 #include "xe_force_wake.h" 20 #include "xe_gt.h" 21 #include "xe_gt_idle.h" 22 #include "xe_gt_printk.h" 23 #include "xe_gt_types.h" 24 #include "xe_guc.h" 25 #include "xe_guc_ct.h" 26 #include "xe_map.h" 27 #include "xe_mmio.h" 28 #include "xe_pcode.h" 29 #include "xe_pm.h" 30 #include "xe_sriov.h" 31 #include "xe_wa.h" 32 33 #define MCHBAR_MIRROR_BASE_SNB 0x140000 34 35 #define RP_STATE_CAP XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998) 36 #define RP0_MASK REG_GENMASK(7, 0) 37 #define RP1_MASK REG_GENMASK(15, 8) 38 #define RPN_MASK REG_GENMASK(23, 16) 39 40 #define FREQ_INFO_REC XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0) 41 #define RPE_MASK REG_GENMASK(15, 8) 42 #define RPA_MASK REG_GENMASK(31, 16) 43 44 #define GT_PERF_STATUS XE_REG(0x1381b4) 45 #define CAGF_MASK REG_GENMASK(19, 11) 46 47 #define GT_FREQUENCY_MULTIPLIER 50 48 #define GT_FREQUENCY_SCALER 3 49 50 #define LNL_MERT_FREQ_CAP 800 51 #define BMG_MERT_FREQ_CAP 2133 52 53 /** 54 * DOC: GuC Power Conservation (PC) 55 * 56 * GuC Power Conservation (PC) supports multiple features for the most 57 * efficient and performing use of the GT when GuC submission is enabled, 58 * including frequency management, Render-C states management, and various 59 * algorithms for power balancing. 60 * 61 * Single Loop Power Conservation (SLPC) is the name given to the suite of 62 * connected power conservation features in the GuC firmware. The firmware 63 * exposes a programming interface to the host for the control of SLPC. 64 * 65 * Frequency management: 66 * ===================== 67 * 68 * Xe driver enables SLPC with all of its defaults features and frequency 69 * selection, which varies per platform. 70 * 71 * Render-C States: 72 * ================ 73 * 74 * Render-C states is also a GuC PC feature that is now enabled in Xe for 75 * all platforms. 76 * 77 */ 78 79 static struct xe_guc *pc_to_guc(struct xe_guc_pc *pc) 80 { 81 return container_of(pc, struct xe_guc, pc); 82 } 83 84 static struct xe_guc_ct *pc_to_ct(struct xe_guc_pc *pc) 85 { 86 return &pc_to_guc(pc)->ct; 87 } 88 89 static struct xe_gt *pc_to_gt(struct xe_guc_pc *pc) 90 { 91 return guc_to_gt(pc_to_guc(pc)); 92 } 93 94 static struct xe_device *pc_to_xe(struct xe_guc_pc *pc) 95 { 96 return guc_to_xe(pc_to_guc(pc)); 97 } 98 99 static struct iosys_map *pc_to_maps(struct xe_guc_pc *pc) 100 { 101 return &pc->bo->vmap; 102 } 103 104 #define slpc_shared_data_read(pc_, field_) \ 105 xe_map_rd_field(pc_to_xe(pc_), pc_to_maps(pc_), 0, \ 106 struct slpc_shared_data, field_) 107 108 #define slpc_shared_data_write(pc_, field_, val_) \ 109 xe_map_wr_field(pc_to_xe(pc_), pc_to_maps(pc_), 0, \ 110 struct slpc_shared_data, field_, val_) 111 112 #define SLPC_EVENT(id, count) \ 113 (FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \ 114 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, count)) 115 116 static int wait_for_pc_state(struct xe_guc_pc *pc, 117 enum slpc_global_state state) 118 { 119 int timeout_us = 5000; /* rought 5ms, but no need for precision */ 120 int slept, wait = 10; 121 122 xe_device_assert_mem_access(pc_to_xe(pc)); 123 124 for (slept = 0; slept < timeout_us;) { 125 if (slpc_shared_data_read(pc, header.global_state) == state) 126 return 0; 127 128 usleep_range(wait, wait << 1); 129 slept += wait; 130 wait <<= 1; 131 if (slept + wait > timeout_us) 132 wait = timeout_us - slept; 133 } 134 135 return -ETIMEDOUT; 136 } 137 138 static int pc_action_reset(struct xe_guc_pc *pc) 139 { 140 struct xe_guc_ct *ct = pc_to_ct(pc); 141 u32 action[] = { 142 GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, 143 SLPC_EVENT(SLPC_EVENT_RESET, 2), 144 xe_bo_ggtt_addr(pc->bo), 145 0, 146 }; 147 int ret; 148 149 ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); 150 if (ret) 151 xe_gt_err(pc_to_gt(pc), "GuC PC reset failed: %pe\n", 152 ERR_PTR(ret)); 153 154 return ret; 155 } 156 157 static int pc_action_query_task_state(struct xe_guc_pc *pc) 158 { 159 struct xe_guc_ct *ct = pc_to_ct(pc); 160 u32 action[] = { 161 GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, 162 SLPC_EVENT(SLPC_EVENT_QUERY_TASK_STATE, 2), 163 xe_bo_ggtt_addr(pc->bo), 164 0, 165 }; 166 int ret; 167 168 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) 169 return -EAGAIN; 170 171 /* Blocking here to ensure the results are ready before reading them */ 172 ret = xe_guc_ct_send_block(ct, action, ARRAY_SIZE(action)); 173 if (ret) 174 xe_gt_err(pc_to_gt(pc), "GuC PC query task state failed: %pe\n", 175 ERR_PTR(ret)); 176 177 return ret; 178 } 179 180 static int pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value) 181 { 182 struct xe_guc_ct *ct = pc_to_ct(pc); 183 u32 action[] = { 184 GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, 185 SLPC_EVENT(SLPC_EVENT_PARAMETER_SET, 2), 186 id, 187 value, 188 }; 189 int ret; 190 191 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) 192 return -EAGAIN; 193 194 ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); 195 if (ret) 196 xe_gt_err(pc_to_gt(pc), "GuC PC set param[%u]=%u failed: %pe\n", 197 id, value, ERR_PTR(ret)); 198 199 return ret; 200 } 201 202 static int pc_action_unset_param(struct xe_guc_pc *pc, u8 id) 203 { 204 u32 action[] = { 205 GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, 206 SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1), 207 id, 208 }; 209 struct xe_guc_ct *ct = &pc_to_guc(pc)->ct; 210 int ret; 211 212 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) 213 return -EAGAIN; 214 215 ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); 216 if (ret) 217 xe_gt_err(pc_to_gt(pc), "GuC PC unset param failed: %pe", 218 ERR_PTR(ret)); 219 220 return ret; 221 } 222 223 static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode) 224 { 225 struct xe_guc_ct *ct = pc_to_ct(pc); 226 u32 action[] = { 227 GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC, 228 mode, 229 }; 230 int ret; 231 232 ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); 233 if (ret) 234 xe_gt_err(pc_to_gt(pc), "GuC RC enable mode=%u failed: %pe\n", 235 mode, ERR_PTR(ret)); 236 return ret; 237 } 238 239 static u32 decode_freq(u32 raw) 240 { 241 return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER, 242 GT_FREQUENCY_SCALER); 243 } 244 245 static u32 encode_freq(u32 freq) 246 { 247 return DIV_ROUND_CLOSEST(freq * GT_FREQUENCY_SCALER, 248 GT_FREQUENCY_MULTIPLIER); 249 } 250 251 static u32 pc_get_min_freq(struct xe_guc_pc *pc) 252 { 253 u32 freq; 254 255 freq = FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK, 256 slpc_shared_data_read(pc, task_state_data.freq)); 257 258 return decode_freq(freq); 259 } 260 261 static void pc_set_manual_rp_ctrl(struct xe_guc_pc *pc, bool enable) 262 { 263 struct xe_gt *gt = pc_to_gt(pc); 264 u32 state = enable ? RPSWCTL_ENABLE : RPSWCTL_DISABLE; 265 266 /* Allow/Disallow punit to process software freq requests */ 267 xe_mmio_write32(>->mmio, RP_CONTROL, state); 268 } 269 270 static void pc_set_cur_freq(struct xe_guc_pc *pc, u32 freq) 271 { 272 struct xe_gt *gt = pc_to_gt(pc); 273 u32 rpnswreq; 274 275 pc_set_manual_rp_ctrl(pc, true); 276 277 /* Req freq is in units of 16.66 Mhz */ 278 rpnswreq = REG_FIELD_PREP(REQ_RATIO_MASK, encode_freq(freq)); 279 xe_mmio_write32(>->mmio, RPNSWREQ, rpnswreq); 280 281 /* Sleep for a small time to allow pcode to respond */ 282 usleep_range(100, 300); 283 284 pc_set_manual_rp_ctrl(pc, false); 285 } 286 287 static int pc_set_min_freq(struct xe_guc_pc *pc, u32 freq) 288 { 289 /* 290 * Let's only check for the rpn-rp0 range. If max < min, 291 * min becomes a fixed request. 292 */ 293 if (freq < pc->rpn_freq || freq > pc->rp0_freq) 294 return -EINVAL; 295 296 /* 297 * GuC policy is to elevate minimum frequency to the efficient levels 298 * Our goal is to have the admin choices respected. 299 */ 300 pc_action_set_param(pc, SLPC_PARAM_IGNORE_EFFICIENT_FREQUENCY, 301 freq < pc->rpe_freq); 302 303 return pc_action_set_param(pc, 304 SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ, 305 freq); 306 } 307 308 static int pc_get_max_freq(struct xe_guc_pc *pc) 309 { 310 u32 freq; 311 312 freq = FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK, 313 slpc_shared_data_read(pc, task_state_data.freq)); 314 315 return decode_freq(freq); 316 } 317 318 static int pc_set_max_freq(struct xe_guc_pc *pc, u32 freq) 319 { 320 /* 321 * Let's only check for the rpn-rp0 range. If max < min, 322 * min becomes a fixed request. 323 * Also, overclocking is not supported. 324 */ 325 if (freq < pc->rpn_freq || freq > pc->rp0_freq) 326 return -EINVAL; 327 328 return pc_action_set_param(pc, 329 SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ, 330 freq); 331 } 332 333 static void mtl_update_rpa_value(struct xe_guc_pc *pc) 334 { 335 struct xe_gt *gt = pc_to_gt(pc); 336 u32 reg; 337 338 if (xe_gt_is_media_type(gt)) 339 reg = xe_mmio_read32(>->mmio, MTL_MPA_FREQUENCY); 340 else 341 reg = xe_mmio_read32(>->mmio, MTL_GT_RPA_FREQUENCY); 342 343 pc->rpa_freq = decode_freq(REG_FIELD_GET(MTL_RPA_MASK, reg)); 344 } 345 346 static void mtl_update_rpe_value(struct xe_guc_pc *pc) 347 { 348 struct xe_gt *gt = pc_to_gt(pc); 349 u32 reg; 350 351 if (xe_gt_is_media_type(gt)) 352 reg = xe_mmio_read32(>->mmio, MTL_MPE_FREQUENCY); 353 else 354 reg = xe_mmio_read32(>->mmio, MTL_GT_RPE_FREQUENCY); 355 356 pc->rpe_freq = decode_freq(REG_FIELD_GET(MTL_RPE_MASK, reg)); 357 } 358 359 static void tgl_update_rpa_value(struct xe_guc_pc *pc) 360 { 361 struct xe_gt *gt = pc_to_gt(pc); 362 struct xe_device *xe = gt_to_xe(gt); 363 u32 reg; 364 365 /* 366 * For PVC we still need to use fused RP1 as the approximation for RPe 367 * For other platforms than PVC we get the resolved RPe directly from 368 * PCODE at a different register 369 */ 370 if (xe->info.platform == XE_PVC) 371 reg = xe_mmio_read32(>->mmio, PVC_RP_STATE_CAP); 372 else 373 reg = xe_mmio_read32(>->mmio, FREQ_INFO_REC); 374 375 pc->rpa_freq = REG_FIELD_GET(RPA_MASK, reg) * GT_FREQUENCY_MULTIPLIER; 376 } 377 378 static void tgl_update_rpe_value(struct xe_guc_pc *pc) 379 { 380 struct xe_gt *gt = pc_to_gt(pc); 381 struct xe_device *xe = gt_to_xe(gt); 382 u32 reg; 383 384 /* 385 * For PVC we still need to use fused RP1 as the approximation for RPe 386 * For other platforms than PVC we get the resolved RPe directly from 387 * PCODE at a different register 388 */ 389 if (xe->info.platform == XE_PVC) 390 reg = xe_mmio_read32(>->mmio, PVC_RP_STATE_CAP); 391 else 392 reg = xe_mmio_read32(>->mmio, FREQ_INFO_REC); 393 394 pc->rpe_freq = REG_FIELD_GET(RPE_MASK, reg) * GT_FREQUENCY_MULTIPLIER; 395 } 396 397 static void pc_update_rp_values(struct xe_guc_pc *pc) 398 { 399 struct xe_gt *gt = pc_to_gt(pc); 400 struct xe_device *xe = gt_to_xe(gt); 401 402 if (GRAPHICS_VERx100(xe) >= 1270) { 403 mtl_update_rpa_value(pc); 404 mtl_update_rpe_value(pc); 405 } else { 406 tgl_update_rpa_value(pc); 407 tgl_update_rpe_value(pc); 408 } 409 410 /* 411 * RPe is decided at runtime by PCODE. In the rare case where that's 412 * smaller than the fused min, we will trust the PCODE and use that 413 * as our minimum one. 414 */ 415 pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq); 416 } 417 418 /** 419 * xe_guc_pc_get_act_freq - Get Actual running frequency 420 * @pc: The GuC PC 421 * 422 * Returns: The Actual running frequency. Which might be 0 if GT is in Render-C sleep state (RC6). 423 */ 424 u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc) 425 { 426 struct xe_gt *gt = pc_to_gt(pc); 427 struct xe_device *xe = gt_to_xe(gt); 428 u32 freq; 429 430 /* When in RC6, actual frequency reported will be 0. */ 431 if (GRAPHICS_VERx100(xe) >= 1270) { 432 freq = xe_mmio_read32(>->mmio, MTL_MIRROR_TARGET_WP1); 433 freq = REG_FIELD_GET(MTL_CAGF_MASK, freq); 434 } else { 435 freq = xe_mmio_read32(>->mmio, GT_PERF_STATUS); 436 freq = REG_FIELD_GET(CAGF_MASK, freq); 437 } 438 439 freq = decode_freq(freq); 440 441 return freq; 442 } 443 444 /** 445 * xe_guc_pc_get_cur_freq - Get Current requested frequency 446 * @pc: The GuC PC 447 * @freq: A pointer to a u32 where the freq value will be returned 448 * 449 * Returns: 0 on success, 450 * -EAGAIN if GuC PC not ready (likely in middle of a reset). 451 */ 452 int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq) 453 { 454 struct xe_gt *gt = pc_to_gt(pc); 455 unsigned int fw_ref; 456 457 /* 458 * GuC SLPC plays with cur freq request when GuCRC is enabled 459 * Block RC6 for a more reliable read. 460 */ 461 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 462 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FW_GT)) { 463 xe_force_wake_put(gt_to_fw(gt), fw_ref); 464 return -ETIMEDOUT; 465 } 466 467 *freq = xe_mmio_read32(>->mmio, RPNSWREQ); 468 469 *freq = REG_FIELD_GET(REQ_RATIO_MASK, *freq); 470 *freq = decode_freq(*freq); 471 472 xe_force_wake_put(gt_to_fw(gt), fw_ref); 473 return 0; 474 } 475 476 /** 477 * xe_guc_pc_get_rp0_freq - Get the RP0 freq 478 * @pc: The GuC PC 479 * 480 * Returns: RP0 freq. 481 */ 482 u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc) 483 { 484 return pc->rp0_freq; 485 } 486 487 /** 488 * xe_guc_pc_get_rpa_freq - Get the RPa freq 489 * @pc: The GuC PC 490 * 491 * Returns: RPa freq. 492 */ 493 u32 xe_guc_pc_get_rpa_freq(struct xe_guc_pc *pc) 494 { 495 pc_update_rp_values(pc); 496 497 return pc->rpa_freq; 498 } 499 500 /** 501 * xe_guc_pc_get_rpe_freq - Get the RPe freq 502 * @pc: The GuC PC 503 * 504 * Returns: RPe freq. 505 */ 506 u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc) 507 { 508 pc_update_rp_values(pc); 509 510 return pc->rpe_freq; 511 } 512 513 /** 514 * xe_guc_pc_get_rpn_freq - Get the RPn freq 515 * @pc: The GuC PC 516 * 517 * Returns: RPn freq. 518 */ 519 u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc) 520 { 521 return pc->rpn_freq; 522 } 523 524 /** 525 * xe_guc_pc_get_min_freq - Get the min operational frequency 526 * @pc: The GuC PC 527 * @freq: A pointer to a u32 where the freq value will be returned 528 * 529 * Returns: 0 on success, 530 * -EAGAIN if GuC PC not ready (likely in middle of a reset). 531 */ 532 int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq) 533 { 534 int ret; 535 536 xe_device_assert_mem_access(pc_to_xe(pc)); 537 538 mutex_lock(&pc->freq_lock); 539 if (!pc->freq_ready) { 540 /* Might be in the middle of a gt reset */ 541 ret = -EAGAIN; 542 goto out; 543 } 544 545 ret = pc_action_query_task_state(pc); 546 if (ret) 547 goto out; 548 549 *freq = pc_get_min_freq(pc); 550 551 out: 552 mutex_unlock(&pc->freq_lock); 553 return ret; 554 } 555 556 /** 557 * xe_guc_pc_set_min_freq - Set the minimal operational frequency 558 * @pc: The GuC PC 559 * @freq: The selected minimal frequency 560 * 561 * Returns: 0 on success, 562 * -EAGAIN if GuC PC not ready (likely in middle of a reset), 563 * -EINVAL if value out of bounds. 564 */ 565 int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq) 566 { 567 int ret; 568 569 mutex_lock(&pc->freq_lock); 570 if (!pc->freq_ready) { 571 /* Might be in the middle of a gt reset */ 572 ret = -EAGAIN; 573 goto out; 574 } 575 576 ret = pc_set_min_freq(pc, freq); 577 if (ret) 578 goto out; 579 580 pc->user_requested_min = freq; 581 582 out: 583 mutex_unlock(&pc->freq_lock); 584 return ret; 585 } 586 587 /** 588 * xe_guc_pc_get_max_freq - Get Maximum operational frequency 589 * @pc: The GuC PC 590 * @freq: A pointer to a u32 where the freq value will be returned 591 * 592 * Returns: 0 on success, 593 * -EAGAIN if GuC PC not ready (likely in middle of a reset). 594 */ 595 int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq) 596 { 597 int ret; 598 599 mutex_lock(&pc->freq_lock); 600 if (!pc->freq_ready) { 601 /* Might be in the middle of a gt reset */ 602 ret = -EAGAIN; 603 goto out; 604 } 605 606 ret = pc_action_query_task_state(pc); 607 if (ret) 608 goto out; 609 610 *freq = pc_get_max_freq(pc); 611 612 out: 613 mutex_unlock(&pc->freq_lock); 614 return ret; 615 } 616 617 /** 618 * xe_guc_pc_set_max_freq - Set the maximum operational frequency 619 * @pc: The GuC PC 620 * @freq: The selected maximum frequency value 621 * 622 * Returns: 0 on success, 623 * -EAGAIN if GuC PC not ready (likely in middle of a reset), 624 * -EINVAL if value out of bounds. 625 */ 626 int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq) 627 { 628 int ret; 629 630 mutex_lock(&pc->freq_lock); 631 if (!pc->freq_ready) { 632 /* Might be in the middle of a gt reset */ 633 ret = -EAGAIN; 634 goto out; 635 } 636 637 ret = pc_set_max_freq(pc, freq); 638 if (ret) 639 goto out; 640 641 pc->user_requested_max = freq; 642 643 out: 644 mutex_unlock(&pc->freq_lock); 645 return ret; 646 } 647 648 /** 649 * xe_guc_pc_c_status - get the current GT C state 650 * @pc: XE_GuC_PC instance 651 */ 652 enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc) 653 { 654 struct xe_gt *gt = pc_to_gt(pc); 655 u32 reg, gt_c_state; 656 657 if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) { 658 reg = xe_mmio_read32(>->mmio, MTL_MIRROR_TARGET_WP1); 659 gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg); 660 } else { 661 reg = xe_mmio_read32(>->mmio, GT_CORE_STATUS); 662 gt_c_state = REG_FIELD_GET(RCN_MASK, reg); 663 } 664 665 switch (gt_c_state) { 666 case GT_C6: 667 return GT_IDLE_C6; 668 case GT_C0: 669 return GT_IDLE_C0; 670 default: 671 return GT_IDLE_UNKNOWN; 672 } 673 } 674 675 /** 676 * xe_guc_pc_rc6_residency - rc6 residency counter 677 * @pc: Xe_GuC_PC instance 678 */ 679 u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc) 680 { 681 struct xe_gt *gt = pc_to_gt(pc); 682 u32 reg; 683 684 reg = xe_mmio_read32(>->mmio, GT_GFX_RC6); 685 686 return reg; 687 } 688 689 /** 690 * xe_guc_pc_mc6_residency - mc6 residency counter 691 * @pc: Xe_GuC_PC instance 692 */ 693 u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc) 694 { 695 struct xe_gt *gt = pc_to_gt(pc); 696 u64 reg; 697 698 reg = xe_mmio_read32(>->mmio, MTL_MEDIA_MC6); 699 700 return reg; 701 } 702 703 static void mtl_init_fused_rp_values(struct xe_guc_pc *pc) 704 { 705 struct xe_gt *gt = pc_to_gt(pc); 706 u32 reg; 707 708 xe_device_assert_mem_access(pc_to_xe(pc)); 709 710 if (xe_gt_is_media_type(gt)) 711 reg = xe_mmio_read32(>->mmio, MTL_MEDIAP_STATE_CAP); 712 else 713 reg = xe_mmio_read32(>->mmio, MTL_RP_STATE_CAP); 714 715 pc->rp0_freq = decode_freq(REG_FIELD_GET(MTL_RP0_CAP_MASK, reg)); 716 717 pc->rpn_freq = decode_freq(REG_FIELD_GET(MTL_RPN_CAP_MASK, reg)); 718 } 719 720 static void tgl_init_fused_rp_values(struct xe_guc_pc *pc) 721 { 722 struct xe_gt *gt = pc_to_gt(pc); 723 struct xe_device *xe = gt_to_xe(gt); 724 u32 reg; 725 726 xe_device_assert_mem_access(pc_to_xe(pc)); 727 728 if (xe->info.platform == XE_PVC) 729 reg = xe_mmio_read32(>->mmio, PVC_RP_STATE_CAP); 730 else 731 reg = xe_mmio_read32(>->mmio, RP_STATE_CAP); 732 pc->rp0_freq = REG_FIELD_GET(RP0_MASK, reg) * GT_FREQUENCY_MULTIPLIER; 733 pc->rpn_freq = REG_FIELD_GET(RPN_MASK, reg) * GT_FREQUENCY_MULTIPLIER; 734 } 735 736 static void pc_init_fused_rp_values(struct xe_guc_pc *pc) 737 { 738 struct xe_gt *gt = pc_to_gt(pc); 739 struct xe_device *xe = gt_to_xe(gt); 740 741 if (GRAPHICS_VERx100(xe) >= 1270) 742 mtl_init_fused_rp_values(pc); 743 else 744 tgl_init_fused_rp_values(pc); 745 } 746 747 static u32 pc_max_freq_cap(struct xe_guc_pc *pc) 748 { 749 struct xe_gt *gt = pc_to_gt(pc); 750 751 if (XE_WA(gt, 22019338487)) { 752 if (xe_gt_is_media_type(gt)) 753 return min(LNL_MERT_FREQ_CAP, pc->rp0_freq); 754 else 755 return min(BMG_MERT_FREQ_CAP, pc->rp0_freq); 756 } else { 757 return pc->rp0_freq; 758 } 759 } 760 761 /** 762 * xe_guc_pc_raise_unslice - Initialize RPx values and request a higher GT 763 * frequency to allow faster GuC load times 764 * @pc: Xe_GuC_PC instance 765 */ 766 void xe_guc_pc_raise_unslice(struct xe_guc_pc *pc) 767 { 768 struct xe_gt *gt = pc_to_gt(pc); 769 770 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 771 pc_set_cur_freq(pc, pc_max_freq_cap(pc)); 772 } 773 774 /** 775 * xe_guc_pc_init_early - Initialize RPx values 776 * @pc: Xe_GuC_PC instance 777 */ 778 void xe_guc_pc_init_early(struct xe_guc_pc *pc) 779 { 780 struct xe_gt *gt = pc_to_gt(pc); 781 782 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 783 pc_init_fused_rp_values(pc); 784 } 785 786 static int pc_adjust_freq_bounds(struct xe_guc_pc *pc) 787 { 788 int ret; 789 790 lockdep_assert_held(&pc->freq_lock); 791 792 ret = pc_action_query_task_state(pc); 793 if (ret) 794 goto out; 795 796 /* 797 * GuC defaults to some RPmax that is not actually achievable without 798 * overclocking. Let's adjust it to the Hardware RP0, which is the 799 * regular maximum 800 */ 801 if (pc_get_max_freq(pc) > pc->rp0_freq) { 802 ret = pc_set_max_freq(pc, pc->rp0_freq); 803 if (ret) 804 goto out; 805 } 806 807 /* 808 * Same thing happens for Server platforms where min is listed as 809 * RPMax 810 */ 811 if (pc_get_min_freq(pc) > pc->rp0_freq) 812 ret = pc_set_min_freq(pc, pc->rp0_freq); 813 814 out: 815 return ret; 816 } 817 818 static int pc_adjust_requested_freq(struct xe_guc_pc *pc) 819 { 820 int ret = 0; 821 822 lockdep_assert_held(&pc->freq_lock); 823 824 if (pc->user_requested_min != 0) { 825 ret = pc_set_min_freq(pc, pc->user_requested_min); 826 if (ret) 827 return ret; 828 } 829 830 if (pc->user_requested_max != 0) { 831 ret = pc_set_max_freq(pc, pc->user_requested_max); 832 if (ret) 833 return ret; 834 } 835 836 return ret; 837 } 838 839 static int pc_set_mert_freq_cap(struct xe_guc_pc *pc) 840 { 841 int ret = 0; 842 843 if (XE_WA(pc_to_gt(pc), 22019338487)) { 844 /* 845 * Get updated min/max and stash them. 846 */ 847 ret = xe_guc_pc_get_min_freq(pc, &pc->stashed_min_freq); 848 if (!ret) 849 ret = xe_guc_pc_get_max_freq(pc, &pc->stashed_max_freq); 850 if (ret) 851 return ret; 852 853 /* 854 * Ensure min and max are bound by MERT_FREQ_CAP until driver loads. 855 */ 856 mutex_lock(&pc->freq_lock); 857 ret = pc_set_min_freq(pc, min(pc->rpe_freq, pc_max_freq_cap(pc))); 858 if (!ret) 859 ret = pc_set_max_freq(pc, min(pc->rp0_freq, pc_max_freq_cap(pc))); 860 mutex_unlock(&pc->freq_lock); 861 } 862 863 return ret; 864 } 865 866 /** 867 * xe_guc_pc_restore_stashed_freq - Set min/max back to stashed values 868 * @pc: The GuC PC 869 * 870 * Returns: 0 on success, 871 * error code on failure 872 */ 873 int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc) 874 { 875 int ret = 0; 876 877 if (IS_SRIOV_VF(pc_to_xe(pc)) || pc_to_xe(pc)->info.skip_guc_pc) 878 return 0; 879 880 mutex_lock(&pc->freq_lock); 881 ret = pc_set_max_freq(pc, pc->stashed_max_freq); 882 if (!ret) 883 ret = pc_set_min_freq(pc, pc->stashed_min_freq); 884 mutex_unlock(&pc->freq_lock); 885 886 return ret; 887 } 888 889 /** 890 * xe_guc_pc_gucrc_disable - Disable GuC RC 891 * @pc: Xe_GuC_PC instance 892 * 893 * Disables GuC RC by taking control of RC6 back from GuC. 894 * 895 * Return: 0 on success, negative error code on error. 896 */ 897 int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc) 898 { 899 struct xe_device *xe = pc_to_xe(pc); 900 struct xe_gt *gt = pc_to_gt(pc); 901 unsigned int fw_ref; 902 int ret = 0; 903 904 if (xe->info.skip_guc_pc) 905 return 0; 906 907 ret = pc_action_setup_gucrc(pc, GUCRC_HOST_CONTROL); 908 if (ret) 909 return ret; 910 911 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 912 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 913 xe_force_wake_put(gt_to_fw(gt), fw_ref); 914 return -ETIMEDOUT; 915 } 916 917 xe_gt_idle_disable_c6(gt); 918 919 xe_force_wake_put(gt_to_fw(gt), fw_ref); 920 921 return 0; 922 } 923 924 /** 925 * xe_guc_pc_override_gucrc_mode - override GUCRC mode 926 * @pc: Xe_GuC_PC instance 927 * @mode: new value of the mode. 928 * 929 * Return: 0 on success, negative error code on error 930 */ 931 int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode) 932 { 933 int ret; 934 935 xe_pm_runtime_get(pc_to_xe(pc)); 936 ret = pc_action_set_param(pc, SLPC_PARAM_PWRGATE_RC_MODE, mode); 937 xe_pm_runtime_put(pc_to_xe(pc)); 938 939 return ret; 940 } 941 942 /** 943 * xe_guc_pc_unset_gucrc_mode - unset GUCRC mode override 944 * @pc: Xe_GuC_PC instance 945 * 946 * Return: 0 on success, negative error code on error 947 */ 948 int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc) 949 { 950 int ret; 951 952 xe_pm_runtime_get(pc_to_xe(pc)); 953 ret = pc_action_unset_param(pc, SLPC_PARAM_PWRGATE_RC_MODE); 954 xe_pm_runtime_put(pc_to_xe(pc)); 955 956 return ret; 957 } 958 959 static void pc_init_pcode_freq(struct xe_guc_pc *pc) 960 { 961 u32 min = DIV_ROUND_CLOSEST(pc->rpn_freq, GT_FREQUENCY_MULTIPLIER); 962 u32 max = DIV_ROUND_CLOSEST(pc->rp0_freq, GT_FREQUENCY_MULTIPLIER); 963 964 XE_WARN_ON(xe_pcode_init_min_freq_table(gt_to_tile(pc_to_gt(pc)), min, max)); 965 } 966 967 static int pc_init_freqs(struct xe_guc_pc *pc) 968 { 969 int ret; 970 971 mutex_lock(&pc->freq_lock); 972 973 ret = pc_adjust_freq_bounds(pc); 974 if (ret) 975 goto out; 976 977 ret = pc_adjust_requested_freq(pc); 978 if (ret) 979 goto out; 980 981 pc_update_rp_values(pc); 982 983 pc_init_pcode_freq(pc); 984 985 /* 986 * The frequencies are really ready for use only after the user 987 * requested ones got restored. 988 */ 989 pc->freq_ready = true; 990 991 out: 992 mutex_unlock(&pc->freq_lock); 993 return ret; 994 } 995 996 /** 997 * xe_guc_pc_start - Start GuC's Power Conservation component 998 * @pc: Xe_GuC_PC instance 999 */ 1000 int xe_guc_pc_start(struct xe_guc_pc *pc) 1001 { 1002 struct xe_device *xe = pc_to_xe(pc); 1003 struct xe_gt *gt = pc_to_gt(pc); 1004 u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data)); 1005 unsigned int fw_ref; 1006 int ret; 1007 1008 xe_gt_assert(gt, xe_device_uc_enabled(xe)); 1009 1010 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1011 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FW_GT)) { 1012 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1013 return -ETIMEDOUT; 1014 } 1015 1016 if (xe->info.skip_guc_pc) { 1017 if (xe->info.platform != XE_PVC) 1018 xe_gt_idle_enable_c6(gt); 1019 1020 /* Request max possible since dynamic freq mgmt is not enabled */ 1021 pc_set_cur_freq(pc, UINT_MAX); 1022 1023 ret = 0; 1024 goto out; 1025 } 1026 1027 memset(pc->bo->vmap.vaddr, 0, size); 1028 slpc_shared_data_write(pc, header.size, size); 1029 1030 ret = pc_action_reset(pc); 1031 if (ret) 1032 goto out; 1033 1034 if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) { 1035 xe_gt_err(gt, "GuC PC Start failed\n"); 1036 ret = -EIO; 1037 goto out; 1038 } 1039 1040 ret = pc_init_freqs(pc); 1041 if (ret) 1042 goto out; 1043 1044 ret = pc_set_mert_freq_cap(pc); 1045 if (ret) 1046 goto out; 1047 1048 if (xe->info.platform == XE_PVC) { 1049 xe_guc_pc_gucrc_disable(pc); 1050 ret = 0; 1051 goto out; 1052 } 1053 1054 ret = pc_action_setup_gucrc(pc, GUCRC_FIRMWARE_CONTROL); 1055 1056 out: 1057 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1058 return ret; 1059 } 1060 1061 /** 1062 * xe_guc_pc_stop - Stop GuC's Power Conservation component 1063 * @pc: Xe_GuC_PC instance 1064 */ 1065 int xe_guc_pc_stop(struct xe_guc_pc *pc) 1066 { 1067 struct xe_device *xe = pc_to_xe(pc); 1068 1069 if (xe->info.skip_guc_pc) { 1070 xe_gt_idle_disable_c6(pc_to_gt(pc)); 1071 return 0; 1072 } 1073 1074 mutex_lock(&pc->freq_lock); 1075 pc->freq_ready = false; 1076 mutex_unlock(&pc->freq_lock); 1077 1078 return 0; 1079 } 1080 1081 /** 1082 * xe_guc_pc_fini_hw - Finalize GuC's Power Conservation component 1083 * @arg: opaque pointer that should point to Xe_GuC_PC instance 1084 */ 1085 static void xe_guc_pc_fini_hw(void *arg) 1086 { 1087 struct xe_guc_pc *pc = arg; 1088 struct xe_device *xe = pc_to_xe(pc); 1089 unsigned int fw_ref; 1090 1091 if (xe_device_wedged(xe)) 1092 return; 1093 1094 fw_ref = xe_force_wake_get(gt_to_fw(pc_to_gt(pc)), XE_FORCEWAKE_ALL); 1095 xe_guc_pc_gucrc_disable(pc); 1096 XE_WARN_ON(xe_guc_pc_stop(pc)); 1097 1098 /* Bind requested freq to mert_freq_cap before unload */ 1099 pc_set_cur_freq(pc, min(pc_max_freq_cap(pc), pc->rpe_freq)); 1100 1101 xe_force_wake_put(gt_to_fw(pc_to_gt(pc)), fw_ref); 1102 } 1103 1104 /** 1105 * xe_guc_pc_init - Initialize GuC's Power Conservation component 1106 * @pc: Xe_GuC_PC instance 1107 */ 1108 int xe_guc_pc_init(struct xe_guc_pc *pc) 1109 { 1110 struct xe_gt *gt = pc_to_gt(pc); 1111 struct xe_tile *tile = gt_to_tile(gt); 1112 struct xe_device *xe = gt_to_xe(gt); 1113 struct xe_bo *bo; 1114 u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data)); 1115 int err; 1116 1117 if (xe->info.skip_guc_pc) 1118 return 0; 1119 1120 err = drmm_mutex_init(&xe->drm, &pc->freq_lock); 1121 if (err) 1122 return err; 1123 1124 bo = xe_managed_bo_create_pin_map(xe, tile, size, 1125 XE_BO_FLAG_VRAM_IF_DGFX(tile) | 1126 XE_BO_FLAG_GGTT | 1127 XE_BO_FLAG_GGTT_INVALIDATE); 1128 if (IS_ERR(bo)) 1129 return PTR_ERR(bo); 1130 1131 pc->bo = bo; 1132 1133 return devm_add_action_or_reset(xe->drm.dev, xe_guc_pc_fini_hw, pc); 1134 } 1135 1136 static const char *pc_get_state_string(struct xe_guc_pc *pc) 1137 { 1138 switch (slpc_shared_data_read(pc, header.global_state)) { 1139 case SLPC_GLOBAL_STATE_NOT_RUNNING: 1140 return "not running"; 1141 case SLPC_GLOBAL_STATE_INITIALIZING: 1142 return "initializing"; 1143 case SLPC_GLOBAL_STATE_RESETTING: 1144 return "resetting"; 1145 case SLPC_GLOBAL_STATE_RUNNING: 1146 return "running"; 1147 case SLPC_GLOBAL_STATE_SHUTTING_DOWN: 1148 return "shutting down"; 1149 case SLPC_GLOBAL_STATE_ERROR: 1150 return "error"; 1151 default: 1152 return "unknown"; 1153 } 1154 } 1155 1156 /** 1157 * xe_guc_pc_print - Print GuC's Power Conservation information for debug 1158 * @pc: Xe_GuC_PC instance 1159 * @p: drm_printer 1160 */ 1161 void xe_guc_pc_print(struct xe_guc_pc *pc, struct drm_printer *p) 1162 { 1163 drm_printf(p, "SLPC Shared Data Header:\n"); 1164 drm_printf(p, "\tSize: %x\n", slpc_shared_data_read(pc, header.size)); 1165 drm_printf(p, "\tGlobal State: %s\n", pc_get_state_string(pc)); 1166 1167 if (pc_action_query_task_state(pc)) 1168 return; 1169 1170 drm_printf(p, "\nSLPC Tasks Status:\n"); 1171 drm_printf(p, "\tGTPERF enabled: %s\n", 1172 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1173 SLPC_GTPERF_TASK_ENABLED)); 1174 drm_printf(p, "\tDCC enabled: %s\n", 1175 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1176 SLPC_DCC_TASK_ENABLED)); 1177 drm_printf(p, "\tDCC in use: %s\n", 1178 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1179 SLPC_IN_DCC)); 1180 drm_printf(p, "\tBalancer enabled: %s\n", 1181 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1182 SLPC_BALANCER_ENABLED)); 1183 drm_printf(p, "\tIBC enabled: %s\n", 1184 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1185 SLPC_IBC_TASK_ENABLED)); 1186 drm_printf(p, "\tBalancer IA LMT enabled: %s\n", 1187 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1188 SLPC_BALANCER_IA_LMT_ENABLED)); 1189 drm_printf(p, "\tBalancer IA LMT active: %s\n", 1190 str_yes_no(slpc_shared_data_read(pc, task_state_data.status) & 1191 SLPC_BALANCER_IA_LMT_ACTIVE)); 1192 } 1193