xref: /linux/drivers/gpu/drm/xe/xe_guc_log.c (revision e6a901a00822659181c93c86d8bbc2a17779fddc)
1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #include "xe_guc_log.h"
7 
8 #include <drm/drm_managed.h>
9 
10 #include "xe_bo.h"
11 #include "xe_gt.h"
12 #include "xe_map.h"
13 #include "xe_module.h"
14 
15 static struct xe_gt *
16 log_to_gt(struct xe_guc_log *log)
17 {
18 	return container_of(log, struct xe_gt, uc.guc.log);
19 }
20 
21 static struct xe_device *
22 log_to_xe(struct xe_guc_log *log)
23 {
24 	return gt_to_xe(log_to_gt(log));
25 }
26 
27 static size_t guc_log_size(void)
28 {
29 	/*
30 	 *  GuC Log buffer Layout
31 	 *
32 	 *  +===============================+ 00B
33 	 *  |    Crash dump state header    |
34 	 *  +-------------------------------+ 32B
35 	 *  |      Debug state header       |
36 	 *  +-------------------------------+ 64B
37 	 *  |     Capture state header      |
38 	 *  +-------------------------------+ 96B
39 	 *  |                               |
40 	 *  +===============================+ PAGE_SIZE (4KB)
41 	 *  |        Crash Dump logs        |
42 	 *  +===============================+ + CRASH_SIZE
43 	 *  |          Debug logs           |
44 	 *  +===============================+ + DEBUG_SIZE
45 	 *  |         Capture logs          |
46 	 *  +===============================+ + CAPTURE_SIZE
47 	 */
48 	return PAGE_SIZE + CRASH_BUFFER_SIZE + DEBUG_BUFFER_SIZE +
49 		CAPTURE_BUFFER_SIZE;
50 }
51 
52 void xe_guc_log_print(struct xe_guc_log *log, struct drm_printer *p)
53 {
54 	struct xe_device *xe = log_to_xe(log);
55 	size_t size;
56 	int i, j;
57 
58 	xe_assert(xe, log->bo);
59 
60 	size = log->bo->size;
61 
62 #define DW_PER_READ		128
63 	xe_assert(xe, !(size % (DW_PER_READ * sizeof(u32))));
64 	for (i = 0; i < size / sizeof(u32); i += DW_PER_READ) {
65 		u32 read[DW_PER_READ];
66 
67 		xe_map_memcpy_from(xe, read, &log->bo->vmap, i * sizeof(u32),
68 				   DW_PER_READ * sizeof(u32));
69 #define DW_PER_PRINT		4
70 		for (j = 0; j < DW_PER_READ / DW_PER_PRINT; ++j) {
71 			u32 *print = read + j * DW_PER_PRINT;
72 
73 			drm_printf(p, "0x%08x 0x%08x 0x%08x 0x%08x\n",
74 				   *(print + 0), *(print + 1),
75 				   *(print + 2), *(print + 3));
76 		}
77 	}
78 }
79 
80 int xe_guc_log_init(struct xe_guc_log *log)
81 {
82 	struct xe_device *xe = log_to_xe(log);
83 	struct xe_tile *tile = gt_to_tile(log_to_gt(log));
84 	struct xe_bo *bo;
85 
86 	bo = xe_managed_bo_create_pin_map(xe, tile, guc_log_size(),
87 					  XE_BO_CREATE_SYSTEM_BIT |
88 					  XE_BO_CREATE_GGTT_BIT);
89 	if (IS_ERR(bo))
90 		return PTR_ERR(bo);
91 
92 	xe_map_memset(xe, &bo->vmap, 0, 0, guc_log_size());
93 	log->bo = bo;
94 	log->level = xe_modparam.guc_log_level;
95 
96 	return 0;
97 }
98