1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc_ads.h" 7 8 #include <drm/drm_managed.h> 9 10 #include <generated/xe_wa_oob.h> 11 12 #include "regs/xe_engine_regs.h" 13 #include "regs/xe_gt_regs.h" 14 #include "regs/xe_guc_regs.h" 15 #include "xe_bo.h" 16 #include "xe_gt.h" 17 #include "xe_gt_ccs_mode.h" 18 #include "xe_guc.h" 19 #include "xe_hw_engine.h" 20 #include "xe_lrc.h" 21 #include "xe_map.h" 22 #include "xe_mmio.h" 23 #include "xe_platform_types.h" 24 #include "xe_wa.h" 25 26 /* Slack of a few additional entries per engine */ 27 #define ADS_REGSET_EXTRA_MAX 8 28 29 static struct xe_guc * 30 ads_to_guc(struct xe_guc_ads *ads) 31 { 32 return container_of(ads, struct xe_guc, ads); 33 } 34 35 static struct xe_gt * 36 ads_to_gt(struct xe_guc_ads *ads) 37 { 38 return container_of(ads, struct xe_gt, uc.guc.ads); 39 } 40 41 static struct xe_device * 42 ads_to_xe(struct xe_guc_ads *ads) 43 { 44 return gt_to_xe(ads_to_gt(ads)); 45 } 46 47 static struct iosys_map * 48 ads_to_map(struct xe_guc_ads *ads) 49 { 50 return &ads->bo->vmap; 51 } 52 53 /* UM Queue parameters: */ 54 #define GUC_UM_QUEUE_SIZE (SZ_64K) 55 #define GUC_PAGE_RES_TIMEOUT_US (-1) 56 57 /* 58 * The Additional Data Struct (ADS) has pointers for different buffers used by 59 * the GuC. One single gem object contains the ADS struct itself (guc_ads) and 60 * all the extra buffers indirectly linked via the ADS struct's entries. 61 * 62 * Layout of the ADS blob allocated for the GuC: 63 * 64 * +---------------------------------------+ <== base 65 * | guc_ads | 66 * +---------------------------------------+ 67 * | guc_policies | 68 * +---------------------------------------+ 69 * | guc_gt_system_info | 70 * +---------------------------------------+ 71 * | guc_engine_usage | 72 * +---------------------------------------+ 73 * | guc_um_init_params | 74 * +---------------------------------------+ <== static 75 * | guc_mmio_reg[countA] (engine 0.0) | 76 * | guc_mmio_reg[countB] (engine 0.1) | 77 * | guc_mmio_reg[countC] (engine 1.0) | 78 * | ... | 79 * +---------------------------------------+ <== dynamic 80 * | padding | 81 * +---------------------------------------+ <== 4K aligned 82 * | golden contexts | 83 * +---------------------------------------+ 84 * | padding | 85 * +---------------------------------------+ <== 4K aligned 86 * | w/a KLVs | 87 * +---------------------------------------+ 88 * | padding | 89 * +---------------------------------------+ <== 4K aligned 90 * | capture lists | 91 * +---------------------------------------+ 92 * | padding | 93 * +---------------------------------------+ <== 4K aligned 94 * | UM queues | 95 * +---------------------------------------+ 96 * | padding | 97 * +---------------------------------------+ <== 4K aligned 98 * | private data | 99 * +---------------------------------------+ 100 * | padding | 101 * +---------------------------------------+ <== 4K aligned 102 */ 103 struct __guc_ads_blob { 104 struct guc_ads ads; 105 struct guc_policies policies; 106 struct guc_gt_system_info system_info; 107 struct guc_engine_usage engine_usage; 108 struct guc_um_init_params um_init_params; 109 /* From here on, location is dynamic! Refer to above diagram. */ 110 struct guc_mmio_reg regset[]; 111 } __packed; 112 113 #define ads_blob_read(ads_, field_) \ 114 xe_map_rd_field(ads_to_xe(ads_), ads_to_map(ads_), 0, \ 115 struct __guc_ads_blob, field_) 116 117 #define ads_blob_write(ads_, field_, val_) \ 118 xe_map_wr_field(ads_to_xe(ads_), ads_to_map(ads_), 0, \ 119 struct __guc_ads_blob, field_, val_) 120 121 #define info_map_write(xe_, map_, field_, val_) \ 122 xe_map_wr_field(xe_, map_, 0, struct guc_gt_system_info, field_, val_) 123 124 #define info_map_read(xe_, map_, field_) \ 125 xe_map_rd_field(xe_, map_, 0, struct guc_gt_system_info, field_) 126 127 static size_t guc_ads_regset_size(struct xe_guc_ads *ads) 128 { 129 struct xe_device *xe = ads_to_xe(ads); 130 131 xe_assert(xe, ads->regset_size); 132 133 return ads->regset_size; 134 } 135 136 static size_t guc_ads_golden_lrc_size(struct xe_guc_ads *ads) 137 { 138 return PAGE_ALIGN(ads->golden_lrc_size); 139 } 140 141 static u32 guc_ads_waklv_size(struct xe_guc_ads *ads) 142 { 143 return PAGE_ALIGN(ads->ads_waklv_size); 144 } 145 146 static size_t guc_ads_capture_size(struct xe_guc_ads *ads) 147 { 148 /* FIXME: Allocate a proper capture list */ 149 return PAGE_ALIGN(PAGE_SIZE); 150 } 151 152 static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads) 153 { 154 struct xe_device *xe = ads_to_xe(ads); 155 156 if (!xe->info.has_usm) 157 return 0; 158 159 return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX; 160 } 161 162 static size_t guc_ads_private_data_size(struct xe_guc_ads *ads) 163 { 164 return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size); 165 } 166 167 static size_t guc_ads_regset_offset(struct xe_guc_ads *ads) 168 { 169 return offsetof(struct __guc_ads_blob, regset); 170 } 171 172 static size_t guc_ads_golden_lrc_offset(struct xe_guc_ads *ads) 173 { 174 size_t offset; 175 176 offset = guc_ads_regset_offset(ads) + 177 guc_ads_regset_size(ads); 178 179 return PAGE_ALIGN(offset); 180 } 181 182 static size_t guc_ads_waklv_offset(struct xe_guc_ads *ads) 183 { 184 u32 offset; 185 186 offset = guc_ads_golden_lrc_offset(ads) + 187 guc_ads_golden_lrc_size(ads); 188 189 return PAGE_ALIGN(offset); 190 } 191 192 static size_t guc_ads_capture_offset(struct xe_guc_ads *ads) 193 { 194 size_t offset; 195 196 offset = guc_ads_waklv_offset(ads) + 197 guc_ads_waklv_size(ads); 198 199 return PAGE_ALIGN(offset); 200 } 201 202 static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads) 203 { 204 u32 offset; 205 206 offset = guc_ads_capture_offset(ads) + 207 guc_ads_capture_size(ads); 208 209 return PAGE_ALIGN(offset); 210 } 211 212 static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads) 213 { 214 size_t offset; 215 216 offset = guc_ads_um_queues_offset(ads) + 217 guc_ads_um_queues_size(ads); 218 219 return PAGE_ALIGN(offset); 220 } 221 222 static size_t guc_ads_size(struct xe_guc_ads *ads) 223 { 224 return guc_ads_private_data_offset(ads) + 225 guc_ads_private_data_size(ads); 226 } 227 228 static bool needs_wa_1607983814(struct xe_device *xe) 229 { 230 return GRAPHICS_VERx100(xe) < 1250; 231 } 232 233 static size_t calculate_regset_size(struct xe_gt *gt) 234 { 235 struct xe_reg_sr_entry *sr_entry; 236 unsigned long sr_idx; 237 struct xe_hw_engine *hwe; 238 enum xe_hw_engine_id id; 239 unsigned int count = 0; 240 241 for_each_hw_engine(hwe, gt, id) 242 xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry) 243 count++; 244 245 count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES; 246 247 if (needs_wa_1607983814(gt_to_xe(gt))) 248 count += LNCFCMOCS_REG_COUNT; 249 250 return count * sizeof(struct guc_mmio_reg); 251 } 252 253 static u32 engine_enable_mask(struct xe_gt *gt, enum xe_engine_class class) 254 { 255 struct xe_hw_engine *hwe; 256 enum xe_hw_engine_id id; 257 u32 mask = 0; 258 259 for_each_hw_engine(hwe, gt, id) 260 if (hwe->class == class) 261 mask |= BIT(hwe->instance); 262 263 return mask; 264 } 265 266 static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads) 267 { 268 struct xe_device *xe = ads_to_xe(ads); 269 struct xe_gt *gt = ads_to_gt(ads); 270 size_t total_size = 0, alloc_size, real_size; 271 int class; 272 273 for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) { 274 if (!engine_enable_mask(gt, class)) 275 continue; 276 277 real_size = xe_lrc_size(xe, class); 278 alloc_size = PAGE_ALIGN(real_size); 279 total_size += alloc_size; 280 } 281 282 return total_size; 283 } 284 285 static void guc_waklv_enable_one_word(struct xe_guc_ads *ads, 286 enum xe_guc_klv_ids klv_id, 287 u32 value, 288 u32 *offset, u32 *remain) 289 { 290 u32 size; 291 u32 klv_entry[] = { 292 /* 16:16 key/length */ 293 FIELD_PREP(GUC_KLV_0_KEY, klv_id) | 294 FIELD_PREP(GUC_KLV_0_LEN, 1), 295 value, 296 /* 1 dword data */ 297 }; 298 299 size = sizeof(klv_entry); 300 301 if (*remain < size) { 302 drm_warn(&ads_to_xe(ads)->drm, 303 "w/a klv buffer too small to add klv id %d\n", klv_id); 304 } else { 305 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), *offset, 306 klv_entry, size); 307 *offset += size; 308 *remain -= size; 309 } 310 } 311 312 static void guc_waklv_enable_simple(struct xe_guc_ads *ads, 313 enum xe_guc_klv_ids klv_id, u32 *offset, u32 *remain) 314 { 315 u32 klv_entry[] = { 316 /* 16:16 key/length */ 317 FIELD_PREP(GUC_KLV_0_KEY, klv_id) | 318 FIELD_PREP(GUC_KLV_0_LEN, 0), 319 /* 0 dwords data */ 320 }; 321 u32 size; 322 323 size = sizeof(klv_entry); 324 325 if (xe_gt_WARN(ads_to_gt(ads), *remain < size, 326 "w/a klv buffer too small to add klv id %d\n", klv_id)) 327 return; 328 329 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), *offset, 330 klv_entry, size); 331 *offset += size; 332 *remain -= size; 333 } 334 335 static void guc_waklv_init(struct xe_guc_ads *ads) 336 { 337 struct xe_gt *gt = ads_to_gt(ads); 338 u64 addr_ggtt; 339 u32 offset, remain, size; 340 341 offset = guc_ads_waklv_offset(ads); 342 remain = guc_ads_waklv_size(ads); 343 344 if (XE_WA(gt, 14019882105)) 345 guc_waklv_enable_simple(ads, 346 GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED, 347 &offset, &remain); 348 if (XE_WA(gt, 18024947630)) 349 guc_waklv_enable_simple(ads, 350 GUC_WORKAROUND_KLV_ID_GAM_PFQ_SHADOW_TAIL_POLLING, 351 &offset, &remain); 352 if (XE_WA(gt, 16022287689)) 353 guc_waklv_enable_simple(ads, 354 GUC_WORKAROUND_KLV_ID_DISABLE_MTP_DURING_ASYNC_COMPUTE, 355 &offset, &remain); 356 357 /* 358 * On RC6 exit, GuC will write register 0xB04 with the default value provided. As of now, 359 * the default value for this register is determined to be 0xC40. This could change in the 360 * future, so GuC depends on KMD to send it the correct value. 361 */ 362 if (XE_WA(gt, 13011645652)) 363 guc_waklv_enable_one_word(ads, 364 GUC_WA_KLV_NP_RD_WRITE_TO_CLEAR_RCSM_AT_CGP_LATE_RESTORE, 365 0xC40, 366 &offset, &remain); 367 368 size = guc_ads_waklv_size(ads) - remain; 369 if (!size) 370 return; 371 372 offset = guc_ads_waklv_offset(ads); 373 addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset; 374 375 ads_blob_write(ads, ads.wa_klv_addr_lo, lower_32_bits(addr_ggtt)); 376 ads_blob_write(ads, ads.wa_klv_addr_hi, upper_32_bits(addr_ggtt)); 377 ads_blob_write(ads, ads.wa_klv_size, size); 378 } 379 380 static int calculate_waklv_size(struct xe_guc_ads *ads) 381 { 382 /* 383 * A single page is both the minimum size possible and 384 * is sufficiently large enough for all current platforms. 385 */ 386 return SZ_4K; 387 } 388 389 #define MAX_GOLDEN_LRC_SIZE (SZ_4K * 64) 390 391 int xe_guc_ads_init(struct xe_guc_ads *ads) 392 { 393 struct xe_device *xe = ads_to_xe(ads); 394 struct xe_gt *gt = ads_to_gt(ads); 395 struct xe_tile *tile = gt_to_tile(gt); 396 struct xe_bo *bo; 397 398 ads->golden_lrc_size = calculate_golden_lrc_size(ads); 399 ads->regset_size = calculate_regset_size(gt); 400 ads->ads_waklv_size = calculate_waklv_size(ads); 401 402 bo = xe_managed_bo_create_pin_map(xe, tile, guc_ads_size(ads) + MAX_GOLDEN_LRC_SIZE, 403 XE_BO_FLAG_SYSTEM | 404 XE_BO_FLAG_GGTT | 405 XE_BO_FLAG_GGTT_INVALIDATE); 406 if (IS_ERR(bo)) 407 return PTR_ERR(bo); 408 409 ads->bo = bo; 410 411 return 0; 412 } 413 414 /** 415 * xe_guc_ads_init_post_hwconfig - initialize ADS post hwconfig load 416 * @ads: Additional data structures object 417 * 418 * Recalcuate golden_lrc_size & regset_size as the number hardware engines may 419 * have changed after the hwconfig was loaded. Also verify the new sizes fit in 420 * the already allocated ADS buffer object. 421 * 422 * Return: 0 on success, negative error code on error. 423 */ 424 int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads) 425 { 426 struct xe_gt *gt = ads_to_gt(ads); 427 u32 prev_regset_size = ads->regset_size; 428 429 xe_gt_assert(gt, ads->bo); 430 431 ads->golden_lrc_size = calculate_golden_lrc_size(ads); 432 ads->regset_size = calculate_regset_size(gt); 433 434 xe_gt_assert(gt, ads->golden_lrc_size + 435 (ads->regset_size - prev_regset_size) <= 436 MAX_GOLDEN_LRC_SIZE); 437 438 return 0; 439 } 440 441 static void guc_policies_init(struct xe_guc_ads *ads) 442 { 443 ads_blob_write(ads, policies.dpc_promote_time, 444 GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US); 445 ads_blob_write(ads, policies.max_num_work_items, 446 GLOBAL_POLICY_MAX_NUM_WI); 447 ads_blob_write(ads, policies.global_flags, 0); 448 ads_blob_write(ads, policies.is_valid, 1); 449 } 450 451 static void fill_engine_enable_masks(struct xe_gt *gt, 452 struct iosys_map *info_map) 453 { 454 struct xe_device *xe = gt_to_xe(gt); 455 456 info_map_write(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS], 457 engine_enable_mask(gt, XE_ENGINE_CLASS_RENDER)); 458 info_map_write(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 459 engine_enable_mask(gt, XE_ENGINE_CLASS_COPY)); 460 info_map_write(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS], 461 engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_DECODE)); 462 info_map_write(xe, info_map, 463 engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], 464 engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE)); 465 info_map_write(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], 466 engine_enable_mask(gt, XE_ENGINE_CLASS_COMPUTE)); 467 info_map_write(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS], 468 engine_enable_mask(gt, XE_ENGINE_CLASS_OTHER)); 469 } 470 471 static void guc_prep_golden_lrc_null(struct xe_guc_ads *ads) 472 { 473 struct xe_device *xe = ads_to_xe(ads); 474 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 475 offsetof(struct __guc_ads_blob, system_info)); 476 u8 guc_class; 477 478 for (guc_class = 0; guc_class <= GUC_MAX_ENGINE_CLASSES; ++guc_class) { 479 if (!info_map_read(xe, &info_map, 480 engine_enabled_masks[guc_class])) 481 continue; 482 483 ads_blob_write(ads, ads.eng_state_size[guc_class], 484 guc_ads_golden_lrc_size(ads) - 485 xe_lrc_skip_size(xe)); 486 ads_blob_write(ads, ads.golden_context_lrca[guc_class], 487 xe_bo_ggtt_addr(ads->bo) + 488 guc_ads_golden_lrc_offset(ads)); 489 } 490 } 491 492 static void guc_mapping_table_init_invalid(struct xe_gt *gt, 493 struct iosys_map *info_map) 494 { 495 struct xe_device *xe = gt_to_xe(gt); 496 unsigned int i, j; 497 498 /* Table must be set to invalid values for entries not used */ 499 for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i) 500 for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; ++j) 501 info_map_write(xe, info_map, mapping_table[i][j], 502 GUC_MAX_INSTANCES_PER_CLASS); 503 } 504 505 static void guc_mapping_table_init(struct xe_gt *gt, 506 struct iosys_map *info_map) 507 { 508 struct xe_device *xe = gt_to_xe(gt); 509 struct xe_hw_engine *hwe; 510 enum xe_hw_engine_id id; 511 512 guc_mapping_table_init_invalid(gt, info_map); 513 514 for_each_hw_engine(hwe, gt, id) { 515 u8 guc_class; 516 517 guc_class = xe_engine_class_to_guc_class(hwe->class); 518 info_map_write(xe, info_map, 519 mapping_table[guc_class][hwe->logical_instance], 520 hwe->instance); 521 } 522 } 523 524 static void guc_capture_list_init(struct xe_guc_ads *ads) 525 { 526 int i, j; 527 u32 addr = xe_bo_ggtt_addr(ads->bo) + guc_ads_capture_offset(ads); 528 529 /* FIXME: Populate a proper capture list */ 530 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { 531 for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) { 532 ads_blob_write(ads, ads.capture_instance[i][j], addr); 533 ads_blob_write(ads, ads.capture_class[i][j], addr); 534 } 535 536 ads_blob_write(ads, ads.capture_global[i], addr); 537 } 538 } 539 540 static void guc_mmio_regset_write_one(struct xe_guc_ads *ads, 541 struct iosys_map *regset_map, 542 struct xe_reg reg, 543 unsigned int n_entry) 544 { 545 struct guc_mmio_reg entry = { 546 .offset = reg.addr, 547 .flags = reg.masked ? GUC_REGSET_MASKED : 0, 548 }; 549 550 xe_map_memcpy_to(ads_to_xe(ads), regset_map, n_entry * sizeof(entry), 551 &entry, sizeof(entry)); 552 } 553 554 static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads, 555 struct iosys_map *regset_map, 556 struct xe_hw_engine *hwe) 557 { 558 struct xe_device *xe = ads_to_xe(ads); 559 struct xe_hw_engine *hwe_rcs_reset_domain = 560 xe_gt_any_hw_engine_by_reset_domain(hwe->gt, XE_ENGINE_CLASS_RENDER); 561 struct xe_reg_sr_entry *entry; 562 unsigned long idx; 563 unsigned int count = 0; 564 const struct { 565 struct xe_reg reg; 566 bool skip; 567 } *e, extra_regs[] = { 568 { .reg = RING_MODE(hwe->mmio_base), }, 569 { .reg = RING_HWS_PGA(hwe->mmio_base), }, 570 { .reg = RING_IMR(hwe->mmio_base), }, 571 { .reg = RCU_MODE, .skip = hwe != hwe_rcs_reset_domain }, 572 { .reg = CCS_MODE, 573 .skip = hwe != hwe_rcs_reset_domain || !xe_gt_ccs_mode_enabled(hwe->gt) }, 574 }; 575 u32 i; 576 577 BUILD_BUG_ON(ARRAY_SIZE(extra_regs) > ADS_REGSET_EXTRA_MAX); 578 579 xa_for_each(&hwe->reg_sr.xa, idx, entry) 580 guc_mmio_regset_write_one(ads, regset_map, entry->reg, count++); 581 582 for (e = extra_regs; e < extra_regs + ARRAY_SIZE(extra_regs); e++) { 583 if (e->skip) 584 continue; 585 586 guc_mmio_regset_write_one(ads, regset_map, e->reg, count++); 587 } 588 589 /* Wa_1607983814 */ 590 if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) { 591 for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) { 592 guc_mmio_regset_write_one(ads, regset_map, 593 XELP_LNCFCMOCS(i), count++); 594 } 595 } 596 597 return count; 598 } 599 600 static void guc_mmio_reg_state_init(struct xe_guc_ads *ads) 601 { 602 size_t regset_offset = guc_ads_regset_offset(ads); 603 struct xe_gt *gt = ads_to_gt(ads); 604 struct xe_hw_engine *hwe; 605 enum xe_hw_engine_id id; 606 u32 addr = xe_bo_ggtt_addr(ads->bo) + regset_offset; 607 struct iosys_map regset_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 608 regset_offset); 609 unsigned int regset_used = 0; 610 611 for_each_hw_engine(hwe, gt, id) { 612 unsigned int count; 613 u8 gc; 614 615 /* 616 * 1. Write all MMIO entries for this exec queue to the table. No 617 * need to worry about fused-off engines and when there are 618 * entries in the regset: the reg_state_list has been zero'ed 619 * by xe_guc_ads_populate() 620 */ 621 count = guc_mmio_regset_write(ads, ®set_map, hwe); 622 if (!count) 623 continue; 624 625 /* 626 * 2. Record in the header (ads.reg_state_list) the address 627 * location and number of entries 628 */ 629 gc = xe_engine_class_to_guc_class(hwe->class); 630 ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].address, addr); 631 ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].count, count); 632 633 addr += count * sizeof(struct guc_mmio_reg); 634 iosys_map_incr(®set_map, count * sizeof(struct guc_mmio_reg)); 635 636 regset_used += count * sizeof(struct guc_mmio_reg); 637 } 638 639 xe_gt_assert(gt, regset_used <= ads->regset_size); 640 } 641 642 static void guc_um_init_params(struct xe_guc_ads *ads) 643 { 644 u32 um_queue_offset = guc_ads_um_queues_offset(ads); 645 u64 base_dpa; 646 u32 base_ggtt; 647 int i; 648 649 base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset; 650 base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset; 651 652 for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) { 653 ads_blob_write(ads, um_init_params.queue_params[i].base_dpa, 654 base_dpa + (i * GUC_UM_QUEUE_SIZE)); 655 ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address, 656 base_ggtt + (i * GUC_UM_QUEUE_SIZE)); 657 ads_blob_write(ads, um_init_params.queue_params[i].size_in_bytes, 658 GUC_UM_QUEUE_SIZE); 659 } 660 661 ads_blob_write(ads, um_init_params.page_response_timeout_in_us, 662 GUC_PAGE_RES_TIMEOUT_US); 663 } 664 665 static void guc_doorbell_init(struct xe_guc_ads *ads) 666 { 667 struct xe_device *xe = ads_to_xe(ads); 668 struct xe_gt *gt = ads_to_gt(ads); 669 670 if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) { 671 u32 distdbreg = 672 xe_mmio_read32(gt, DIST_DBS_POPULATED); 673 674 ads_blob_write(ads, 675 system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI], 676 REG_FIELD_GET(DOORBELLS_PER_SQIDI_MASK, distdbreg) + 1); 677 } 678 } 679 680 /** 681 * xe_guc_ads_populate_minimal - populate minimal ADS 682 * @ads: Additional data structures object 683 * 684 * This function populates a minimal ADS that does not support submissions but 685 * enough so the GuC can load and the hwconfig table can be read. 686 */ 687 void xe_guc_ads_populate_minimal(struct xe_guc_ads *ads) 688 { 689 struct xe_gt *gt = ads_to_gt(ads); 690 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 691 offsetof(struct __guc_ads_blob, system_info)); 692 u32 base = xe_bo_ggtt_addr(ads->bo); 693 694 xe_gt_assert(gt, ads->bo); 695 696 xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads->bo->size); 697 guc_policies_init(ads); 698 guc_prep_golden_lrc_null(ads); 699 guc_mapping_table_init_invalid(gt, &info_map); 700 guc_doorbell_init(ads); 701 702 ads_blob_write(ads, ads.scheduler_policies, base + 703 offsetof(struct __guc_ads_blob, policies)); 704 ads_blob_write(ads, ads.gt_system_info, base + 705 offsetof(struct __guc_ads_blob, system_info)); 706 ads_blob_write(ads, ads.private_data, base + 707 guc_ads_private_data_offset(ads)); 708 } 709 710 void xe_guc_ads_populate(struct xe_guc_ads *ads) 711 { 712 struct xe_device *xe = ads_to_xe(ads); 713 struct xe_gt *gt = ads_to_gt(ads); 714 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 715 offsetof(struct __guc_ads_blob, system_info)); 716 u32 base = xe_bo_ggtt_addr(ads->bo); 717 718 xe_gt_assert(gt, ads->bo); 719 720 xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads->bo->size); 721 guc_policies_init(ads); 722 fill_engine_enable_masks(gt, &info_map); 723 guc_mmio_reg_state_init(ads); 724 guc_prep_golden_lrc_null(ads); 725 guc_mapping_table_init(gt, &info_map); 726 guc_capture_list_init(ads); 727 guc_doorbell_init(ads); 728 guc_waklv_init(ads); 729 730 if (xe->info.has_usm) { 731 guc_um_init_params(ads); 732 ads_blob_write(ads, ads.um_init_data, base + 733 offsetof(struct __guc_ads_blob, um_init_params)); 734 } 735 736 ads_blob_write(ads, ads.scheduler_policies, base + 737 offsetof(struct __guc_ads_blob, policies)); 738 ads_blob_write(ads, ads.gt_system_info, base + 739 offsetof(struct __guc_ads_blob, system_info)); 740 ads_blob_write(ads, ads.private_data, base + 741 guc_ads_private_data_offset(ads)); 742 } 743 744 static void guc_populate_golden_lrc(struct xe_guc_ads *ads) 745 { 746 struct xe_device *xe = ads_to_xe(ads); 747 struct xe_gt *gt = ads_to_gt(ads); 748 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 749 offsetof(struct __guc_ads_blob, system_info)); 750 size_t total_size = 0, alloc_size, real_size; 751 u32 addr_ggtt, offset; 752 int class; 753 754 offset = guc_ads_golden_lrc_offset(ads); 755 addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset; 756 757 for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) { 758 u8 guc_class; 759 760 guc_class = xe_engine_class_to_guc_class(class); 761 762 if (!info_map_read(xe, &info_map, 763 engine_enabled_masks[guc_class])) 764 continue; 765 766 xe_gt_assert(gt, gt->default_lrc[class]); 767 768 real_size = xe_lrc_size(xe, class); 769 alloc_size = PAGE_ALIGN(real_size); 770 total_size += alloc_size; 771 772 /* 773 * This interface is slightly confusing. We need to pass the 774 * base address of the full golden context and the size of just 775 * the engine state, which is the section of the context image 776 * that starts after the execlists LRC registers. This is 777 * required to allow the GuC to restore just the engine state 778 * when a watchdog reset occurs. 779 * We calculate the engine state size by removing the size of 780 * what comes before it in the context image (which is identical 781 * on all engines). 782 */ 783 ads_blob_write(ads, ads.eng_state_size[guc_class], 784 real_size - xe_lrc_skip_size(xe)); 785 ads_blob_write(ads, ads.golden_context_lrca[guc_class], 786 addr_ggtt); 787 788 xe_map_memcpy_to(xe, ads_to_map(ads), offset, 789 gt->default_lrc[class], real_size); 790 791 addr_ggtt += alloc_size; 792 offset += alloc_size; 793 } 794 795 xe_gt_assert(gt, total_size == ads->golden_lrc_size); 796 } 797 798 void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads) 799 { 800 guc_populate_golden_lrc(ads); 801 } 802