1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc_ads.h" 7 8 #include <linux/fault-inject.h> 9 10 #include <drm/drm_managed.h> 11 12 #include <generated/xe_wa_oob.h> 13 14 #include "abi/guc_actions_abi.h" 15 #include "regs/xe_engine_regs.h" 16 #include "regs/xe_gt_regs.h" 17 #include "regs/xe_guc_regs.h" 18 #include "xe_bo.h" 19 #include "xe_configfs.h" 20 #include "xe_gt.h" 21 #include "xe_gt_ccs_mode.h" 22 #include "xe_gt_mcr.h" 23 #include "xe_gt_printk.h" 24 #include "xe_guc.h" 25 #include "xe_guc_buf.h" 26 #include "xe_guc_capture.h" 27 #include "xe_guc_ct.h" 28 #include "xe_hw_engine.h" 29 #include "xe_lrc.h" 30 #include "xe_map.h" 31 #include "xe_mmio.h" 32 #include "xe_wa.h" 33 34 /* Slack of a few additional entries per engine */ 35 #define ADS_REGSET_EXTRA_MAX 8 36 37 static struct xe_guc * 38 ads_to_guc(struct xe_guc_ads *ads) 39 { 40 return container_of(ads, struct xe_guc, ads); 41 } 42 43 static struct xe_gt * 44 ads_to_gt(struct xe_guc_ads *ads) 45 { 46 return container_of(ads, struct xe_gt, uc.guc.ads); 47 } 48 49 static struct xe_device * 50 ads_to_xe(struct xe_guc_ads *ads) 51 { 52 return gt_to_xe(ads_to_gt(ads)); 53 } 54 55 static struct iosys_map * 56 ads_to_map(struct xe_guc_ads *ads) 57 { 58 return &ads->bo->vmap; 59 } 60 61 /* UM Queue parameters: */ 62 #define GUC_UM_QUEUE_SIZE (SZ_64K) 63 #define GUC_PAGE_RES_TIMEOUT_US (-1) 64 65 /* 66 * The Additional Data Struct (ADS) has pointers for different buffers used by 67 * the GuC. One gem object (ads->bo) contains the ADS struct itself (guc_ads) 68 * and most of the extra buffers linked via the ADS struct's entries. The UM 69 * fault queues (PAGE_FAULT, PAGE_FAULT_RESPONSE, ACCESS_COUNTER rings) are 70 * kept in a separate BO (ads->um_queue_bo) so that the full memset of ads->bo 71 * performed on every GT reset does not discard fault descriptors already 72 * written into the rings by the GPU. 73 * 74 * Layout of the ADS blob (ads->bo): 75 * 76 * +---------------------------------------+ <== base 77 * | guc_ads | 78 * +---------------------------------------+ 79 * | guc_policies | 80 * +---------------------------------------+ 81 * | guc_gt_system_info | 82 * +---------------------------------------+ 83 * | guc_engine_usage | 84 * +---------------------------------------+ 85 * | guc_um_init_params | 86 * +---------------------------------------+ <== static 87 * | guc_mmio_reg[countA] (engine 0.0) | 88 * | guc_mmio_reg[countB] (engine 0.1) | 89 * | guc_mmio_reg[countC] (engine 1.0) | 90 * | ... | 91 * +---------------------------------------+ <== dynamic 92 * | padding | 93 * +---------------------------------------+ <== 4K aligned 94 * | golden contexts | 95 * +---------------------------------------+ 96 * | padding | 97 * +---------------------------------------+ <== 4K aligned 98 * | w/a KLVs | 99 * +---------------------------------------+ 100 * | padding | 101 * +---------------------------------------+ <== 4K aligned 102 * | capture lists | 103 * +---------------------------------------+ 104 * | padding | 105 * +---------------------------------------+ <== 4K aligned 106 * | private data | 107 * +---------------------------------------+ 108 * | padding | 109 * +---------------------------------------+ <== 4K aligned 110 */ 111 struct __guc_ads_blob { 112 struct guc_ads ads; 113 struct guc_policies policies; 114 struct guc_gt_system_info system_info; 115 struct guc_engine_usage engine_usage; 116 struct guc_um_init_params um_init_params; 117 /* From here on, location is dynamic! Refer to above diagram. */ 118 struct guc_mmio_reg regset[]; 119 } __packed; 120 121 #define ads_blob_read(ads_, field_) \ 122 xe_map_rd_field(ads_to_xe(ads_), ads_to_map(ads_), 0, \ 123 struct __guc_ads_blob, field_) 124 125 #define ads_blob_write(ads_, field_, val_) \ 126 xe_map_wr_field(ads_to_xe(ads_), ads_to_map(ads_), 0, \ 127 struct __guc_ads_blob, field_, val_) 128 129 #define info_map_write(xe_, map_, field_, val_) \ 130 xe_map_wr_field(xe_, map_, 0, struct guc_gt_system_info, field_, val_) 131 132 #define info_map_read(xe_, map_, field_) \ 133 xe_map_rd_field(xe_, map_, 0, struct guc_gt_system_info, field_) 134 135 static size_t guc_ads_regset_size(struct xe_guc_ads *ads) 136 { 137 struct xe_device *xe = ads_to_xe(ads); 138 139 xe_assert(xe, ads->regset_size); 140 141 return ads->regset_size; 142 } 143 144 static size_t guc_ads_golden_lrc_size(struct xe_guc_ads *ads) 145 { 146 return PAGE_ALIGN(ads->golden_lrc_size); 147 } 148 149 static u32 guc_ads_waklv_size(struct xe_guc_ads *ads) 150 { 151 return PAGE_ALIGN(ads->ads_waklv_size); 152 } 153 154 static size_t guc_ads_capture_size(struct xe_guc_ads *ads) 155 { 156 return PAGE_ALIGN(ads->capture_size); 157 } 158 159 static size_t guc_ads_private_data_size(struct xe_guc_ads *ads) 160 { 161 return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size); 162 } 163 164 static size_t guc_ads_regset_offset(struct xe_guc_ads *ads) 165 { 166 return offsetof(struct __guc_ads_blob, regset); 167 } 168 169 static size_t guc_ads_golden_lrc_offset(struct xe_guc_ads *ads) 170 { 171 size_t offset; 172 173 offset = guc_ads_regset_offset(ads) + 174 guc_ads_regset_size(ads); 175 176 return PAGE_ALIGN(offset); 177 } 178 179 static size_t guc_ads_waklv_offset(struct xe_guc_ads *ads) 180 { 181 u32 offset; 182 183 offset = guc_ads_golden_lrc_offset(ads) + 184 guc_ads_golden_lrc_size(ads); 185 186 return PAGE_ALIGN(offset); 187 } 188 189 static size_t guc_ads_capture_offset(struct xe_guc_ads *ads) 190 { 191 size_t offset; 192 193 offset = guc_ads_waklv_offset(ads) + 194 guc_ads_waklv_size(ads); 195 196 return PAGE_ALIGN(offset); 197 } 198 199 static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads) 200 { 201 size_t offset; 202 203 offset = guc_ads_capture_offset(ads) + 204 guc_ads_capture_size(ads); 205 206 return PAGE_ALIGN(offset); 207 } 208 209 static size_t guc_ads_size(struct xe_guc_ads *ads) 210 { 211 return guc_ads_private_data_offset(ads) + 212 guc_ads_private_data_size(ads); 213 } 214 215 static size_t calculate_regset_size(struct xe_gt *gt) 216 { 217 struct xe_reg_sr_entry *sr_entry; 218 unsigned long sr_idx; 219 struct xe_hw_engine *hwe; 220 enum xe_hw_engine_id id; 221 unsigned int count = 0; 222 223 for_each_hw_engine(hwe, gt, id) 224 xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry) 225 count++; 226 227 count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES; 228 229 if (XE_GT_WA(gt, 1607983814)) 230 count += LNCFCMOCS_REG_COUNT; 231 232 return count * sizeof(struct guc_mmio_reg); 233 } 234 235 static inline enum xe_engine_class guc_class_to_engine_class(u16 guc_class) 236 { 237 switch (guc_class) { 238 case GUC_RENDER_CLASS: 239 return XE_ENGINE_CLASS_RENDER; 240 case GUC_VIDEO_CLASS: 241 return XE_ENGINE_CLASS_VIDEO_DECODE; 242 case GUC_VIDEOENHANCE_CLASS: 243 return XE_ENGINE_CLASS_VIDEO_ENHANCE; 244 case GUC_BLITTER_CLASS: 245 case GUC_PAGING_CLASS: 246 return XE_ENGINE_CLASS_COPY; 247 case GUC_COMPUTE_CLASS: 248 return XE_ENGINE_CLASS_COMPUTE; 249 case GUC_GSC_OTHER_CLASS: 250 return XE_ENGINE_CLASS_OTHER; 251 default: 252 XE_WARN_ON(guc_class); 253 return -1; 254 } 255 } 256 257 static u32 engine_enable_mask(struct xe_gt *gt, u16 guc_class) 258 { 259 struct xe_hw_engine *hwe; 260 enum xe_hw_engine_id id; 261 u32 mask = 0; 262 263 for_each_hw_engine(hwe, gt, id) 264 if (xe_hwe_to_guc_class(hwe) == guc_class) 265 mask |= BIT(hwe->instance); 266 267 /* We expect at most one paging engine per GuC instance, for now */ 268 if (guc_class == GUC_PAGING_CLASS) 269 xe_gt_assert(gt, !mask || is_power_of_2(mask)); 270 271 return mask; 272 } 273 274 static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads) 275 { 276 struct xe_gt *gt = ads_to_gt(ads); 277 size_t total_size = 0, alloc_size, real_size; 278 u16 guc_class; 279 280 for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class) { 281 enum xe_engine_class class = 282 guc_class_to_engine_class(guc_class); 283 284 if (!engine_enable_mask(gt, guc_class)) 285 continue; 286 287 real_size = xe_gt_lrc_size(gt, class); 288 alloc_size = PAGE_ALIGN(real_size); 289 total_size += alloc_size; 290 } 291 292 return total_size; 293 } 294 295 static void guc_waklv_enable(struct xe_guc_ads *ads, 296 u32 data[], u32 data_len_dw, 297 u32 *offset, u32 *remain, 298 enum xe_guc_klv_ids klv_id) 299 { 300 size_t size = sizeof(u32) * (1 + data_len_dw); 301 302 if (*remain < size) { 303 drm_warn(&ads_to_xe(ads)->drm, 304 "w/a klv buffer too small to add klv id 0x%04X\n", klv_id); 305 return; 306 } 307 308 /* 16:16 key/length */ 309 xe_map_wr(ads_to_xe(ads), ads_to_map(ads), *offset, u32, 310 FIELD_PREP(GUC_KLV_0_KEY, klv_id) | FIELD_PREP(GUC_KLV_0_LEN, data_len_dw)); 311 /* data_len_dw dwords of data */ 312 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), 313 *offset + sizeof(u32), data, data_len_dw * sizeof(u32)); 314 315 *offset += size; 316 *remain -= size; 317 } 318 319 static void guc_waklv_init(struct xe_guc_ads *ads) 320 { 321 struct xe_gt *gt = ads_to_gt(ads); 322 u64 addr_ggtt; 323 u32 offset, remain, size; 324 325 offset = guc_ads_waklv_offset(ads); 326 remain = guc_ads_waklv_size(ads); 327 328 if (XE_GT_WA(gt, 16021333562)) 329 guc_waklv_enable(ads, NULL, 0, &offset, &remain, 330 GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED); 331 if (XE_GT_WA(gt, 18024947630)) 332 guc_waklv_enable(ads, NULL, 0, &offset, &remain, 333 GUC_WORKAROUND_KLV_ID_GAM_PFQ_SHADOW_TAIL_POLLING); 334 if (XE_GT_WA(gt, 16022287689)) 335 guc_waklv_enable(ads, NULL, 0, &offset, &remain, 336 GUC_WORKAROUND_KLV_ID_DISABLE_MTP_DURING_ASYNC_COMPUTE); 337 338 if (XE_GT_WA(gt, 14022866841)) 339 guc_waklv_enable(ads, NULL, 0, &offset, &remain, 340 GUC_WA_KLV_WAKE_POWER_DOMAINS_FOR_OUTBOUND_MMIO); 341 342 /* 343 * On RC6 exit, GuC will write register 0xB04 with the default value provided. As of now, 344 * the default value for this register is determined to be 0xC40. This could change in the 345 * future, so GuC depends on KMD to send it the correct value. 346 */ 347 if (XE_GT_WA(gt, 13011645652)) { 348 u32 data = 0xC40; 349 350 guc_waklv_enable(ads, &data, 1, &offset, &remain, 351 GUC_WA_KLV_NP_RD_WRITE_TO_CLEAR_RCSM_AT_CGP_LATE_RESTORE); 352 } 353 354 if (XE_GT_WA(gt, 14022293748) || XE_GT_WA(gt, 22019794406)) 355 guc_waklv_enable(ads, NULL, 0, &offset, &remain, 356 GUC_WORKAROUND_KLV_ID_BACK_TO_BACK_RCS_ENGINE_RESET); 357 358 if (GUC_FIRMWARE_VER_AT_LEAST(>->uc.guc, 70, 44) && XE_GT_WA(gt, 16026508708)) 359 guc_waklv_enable(ads, NULL, 0, &offset, &remain, 360 GUC_WA_KLV_RESET_BB_STACK_PTR_ON_VF_SWITCH); 361 if (GUC_FIRMWARE_VER_AT_LEAST(>->uc.guc, 70, 47) && XE_GT_WA(gt, 16026007364)) { 362 u32 data[] = { 363 0x0, 364 0xF, 365 }; 366 guc_waklv_enable(ads, data, ARRAY_SIZE(data), &offset, &remain, 367 GUC_WA_KLV_RESTORE_UNSAVED_MEDIA_CONTROL_REG); 368 } 369 370 if (XE_GT_WA(gt, 14020001231)) 371 guc_waklv_enable(ads, NULL, 0, &offset, &remain, 372 GUC_WORKAROUND_KLV_DISABLE_PSMI_INTERRUPTS_AT_C6_ENTRY_RESTORE_AT_EXIT); 373 if (XE_GT_WA(gt, 14025515070) && GUC_FIRMWARE_VER_AT_LEAST(>->uc.guc, 70, 53)) 374 guc_waklv_enable(ads, NULL, 0, &offset, &remain, 375 GUC_WA_KLV_CLR_CS_INDIRECT_RING_STATE_IF_IDLE_AT_CTX_REG); 376 377 if (XE_GT_WA(gt, 22022079272) && GUC_FIRMWARE_VER_AT_LEAST(>->uc.guc, 70, 62)) 378 guc_waklv_enable(ads, NULL, 0, &offset, &remain, GUC_WA_KLV_REMAP_RANGED_TLB_INV); 379 380 /* The GuC does not enable the sem_tok_64 feature on NVL-S */ 381 if (XE_GT_WA(gt, 16029897822) && gt_to_xe(gt)->info.platform != XE_NOVALAKE_S && 382 GUC_FIRMWARE_VER_AT_LEAST(>->uc.guc, 70, 69)) 383 guc_waklv_enable(ads, NULL, 0, &offset, &remain, 384 GUC_WA_KLV_IGNORE_MMIO_READ_SEM_TOKEN_64); 385 386 /* 387 * On GuC firmware 70.66 and above, use the Feature KLV (shared with the 388 * WA KLV buffer); older firmware uses GUC_CTL_DISABLE_MULTI_QUEUE in 389 * the init params instead. 390 */ 391 if (!xe_configfs_get_enable_multi_queue(to_pci_dev(gt_to_xe(gt)->drm.dev)) && 392 GUC_FIRMWARE_VER_AT_LEAST(>->uc.guc, 70, 66)) { 393 u32 data = 1; 394 395 guc_waklv_enable(ads, &data, 1, &offset, &remain, 396 GUC_FEATURE_KLV_DISABLE_MULTI_QUEUE); 397 } 398 399 size = guc_ads_waklv_size(ads) - remain; 400 if (!size) 401 return; 402 403 offset = guc_ads_waklv_offset(ads); 404 addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset; 405 406 ads_blob_write(ads, ads.wa_klv_addr_lo, lower_32_bits(addr_ggtt)); 407 ads_blob_write(ads, ads.wa_klv_addr_hi, upper_32_bits(addr_ggtt)); 408 ads_blob_write(ads, ads.wa_klv_size, size); 409 } 410 411 static int calculate_waklv_size(struct xe_guc_ads *ads) 412 { 413 /* 414 * A single page is both the minimum size possible and 415 * is sufficiently large enough for all current platforms. 416 */ 417 return SZ_4K; 418 } 419 420 #define MAX_GOLDEN_LRC_SIZE (SZ_4K * 64) 421 422 int xe_guc_ads_init(struct xe_guc_ads *ads) 423 { 424 struct xe_device *xe = ads_to_xe(ads); 425 struct xe_gt *gt = ads_to_gt(ads); 426 struct xe_tile *tile = gt_to_tile(gt); 427 struct xe_bo *bo; 428 429 ads->golden_lrc_size = calculate_golden_lrc_size(ads); 430 ads->capture_size = xe_guc_capture_ads_input_worst_size(ads_to_guc(ads)); 431 ads->regset_size = calculate_regset_size(gt); 432 ads->ads_waklv_size = calculate_waklv_size(ads); 433 434 bo = xe_managed_bo_create_pin_map(xe, tile, guc_ads_size(ads) + MAX_GOLDEN_LRC_SIZE, 435 XE_BO_FLAG_SYSTEM | 436 XE_BO_FLAG_GGTT | 437 XE_BO_FLAG_GGTT_INVALIDATE | 438 XE_BO_FLAG_PINNED_NORESTORE); 439 if (IS_ERR(bo)) 440 return PTR_ERR(bo); 441 442 ads->bo = bo; 443 444 if (xe->info.has_usm) { 445 /* 446 * Allocate a separate BO for the HW fault ring (UM queues). 447 * 448 * Round the size up to the next power of two so that on iGPU 449 * (system memory, no IOMMU) the TTM pool issues a single 450 * alloc_pages(order=N) call, maximising the chance of getting 451 * a physically contiguous block. GuC requires contiguous DPA. 452 */ 453 size_t um_size = IS_DGFX(xe) ? 454 GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX : 455 roundup_pow_of_two(GUC_UM_QUEUE_SIZE * 456 GUC_UM_HW_QUEUE_MAX); 457 458 u32 um_flags = XE_BO_FLAG_VRAM_IF_DGFX(tile) | 459 XE_BO_FLAG_GGTT | 460 XE_BO_FLAG_GGTT_INVALIDATE | 461 XE_BO_FLAG_PINNED_NORESTORE | 462 XE_BO_FLAG_NEEDS_UC; 463 464 bo = xe_managed_bo_create_pin_map(xe, tile, um_size, um_flags); 465 if (IS_ERR(bo)) 466 return PTR_ERR(bo); 467 468 /* 469 * On pre-Xe3p platforms, GAM (not GuC) accesses the UM queue 470 * ring via base_dpa, which must be a contiguous DMA address 471 * range. Verify that the allocated pages are contiguous in 472 * DMA address space. 473 */ 474 if (!xe_bo_is_vram(bo) && 475 !xe_guc_using_main_gamctrl_queues(ads_to_guc(ads)) && 476 unlikely(!xe_bo_sg_is_contiguous(bo, 477 GUC_UM_QUEUE_SIZE * 478 GUC_UM_HW_QUEUE_MAX))) { 479 drm_err(&xe->drm, 480 "UM fault queue memory is not contiguous in DMA address space; GAM requires contiguous DPA\n"); 481 return -ENOMEM; 482 } 483 484 ads->um_queue_bo = bo; 485 } 486 487 return 0; 488 } 489 ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */ 490 491 /** 492 * xe_guc_ads_init_post_hwconfig - initialize ADS post hwconfig load 493 * @ads: Additional data structures object 494 * 495 * Recalculate golden_lrc_size, capture_size and regset_size as the number 496 * hardware engines may have changed after the hwconfig was loaded. Also verify 497 * the new sizes fit in the already allocated ADS buffer object. 498 * 499 * Return: 0 on success, negative error code on error. 500 */ 501 int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads) 502 { 503 struct xe_gt *gt = ads_to_gt(ads); 504 u32 prev_regset_size = ads->regset_size; 505 506 xe_gt_assert(gt, ads->bo); 507 508 ads->golden_lrc_size = calculate_golden_lrc_size(ads); 509 /* Calculate Capture size with worst size */ 510 ads->capture_size = xe_guc_capture_ads_input_worst_size(ads_to_guc(ads)); 511 ads->regset_size = calculate_regset_size(gt); 512 513 xe_gt_assert(gt, ads->golden_lrc_size + 514 (ads->regset_size - prev_regset_size) <= 515 MAX_GOLDEN_LRC_SIZE); 516 517 return 0; 518 } 519 520 static void guc_policies_init(struct xe_guc_ads *ads) 521 { 522 struct xe_device *xe = ads_to_xe(ads); 523 u32 global_flags = 0; 524 525 ads_blob_write(ads, policies.dpc_promote_time, 526 GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US); 527 ads_blob_write(ads, policies.max_num_work_items, 528 GLOBAL_POLICY_MAX_NUM_WI); 529 530 if (xe->wedged.mode == XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET) 531 global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET; 532 533 ads_blob_write(ads, policies.global_flags, global_flags); 534 ads_blob_write(ads, policies.is_valid, 1); 535 } 536 537 static void fill_engine_enable_masks(struct xe_gt *gt, 538 struct iosys_map *info_map) 539 { 540 struct xe_device *xe = gt_to_xe(gt); 541 u16 guc_class; 542 543 for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class) 544 info_map_write(xe, info_map, engine_enabled_masks[guc_class], 545 engine_enable_mask(gt, guc_class)); 546 } 547 548 u16 xe_hwe_to_guc_class(struct xe_hw_engine *hwe) 549 { 550 if (xe_guc_has_paging_engine(&hwe->gt->uc.guc) && 551 xe_gt_is_usm_hwe(hwe->gt, hwe)) 552 return GUC_PAGING_CLASS; 553 554 switch (hwe->class) { 555 case XE_ENGINE_CLASS_RENDER: 556 return GUC_RENDER_CLASS; 557 case XE_ENGINE_CLASS_VIDEO_DECODE: 558 return GUC_VIDEO_CLASS; 559 case XE_ENGINE_CLASS_VIDEO_ENHANCE: 560 return GUC_VIDEOENHANCE_CLASS; 561 case XE_ENGINE_CLASS_COPY: 562 return GUC_BLITTER_CLASS; 563 case XE_ENGINE_CLASS_COMPUTE: 564 return GUC_COMPUTE_CLASS; 565 case XE_ENGINE_CLASS_OTHER: 566 return GUC_GSC_OTHER_CLASS; 567 default: 568 XE_WARN_ON(hwe->class); 569 return -1; 570 } 571 } 572 573 /* 574 * Write the offsets corresponding to the golden LRCs. The actual data is 575 * populated later by guc_golden_lrc_populate() 576 */ 577 static void guc_golden_lrc_init(struct xe_guc_ads *ads) 578 { 579 struct xe_device *xe = ads_to_xe(ads); 580 struct xe_gt *gt = ads_to_gt(ads); 581 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 582 offsetof(struct __guc_ads_blob, system_info)); 583 size_t alloc_size, real_size; 584 u32 addr_ggtt, offset; 585 u16 guc_class; 586 587 offset = guc_ads_golden_lrc_offset(ads); 588 addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset; 589 590 for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class) { 591 enum xe_engine_class class = 592 guc_class_to_engine_class(guc_class); 593 594 if (!info_map_read(xe, &info_map, 595 engine_enabled_masks[guc_class])) 596 continue; 597 598 real_size = xe_gt_lrc_size(gt, class); 599 alloc_size = PAGE_ALIGN(real_size); 600 601 /* 602 * This interface is slightly confusing. We need to pass the 603 * base address of the full golden context and the size of just 604 * the engine state, which is the section of the context image 605 * that starts after the execlists LRC registers. This is 606 * required to allow the GuC to restore just the engine state 607 * when a watchdog reset occurs. 608 */ 609 ads_blob_write(ads, ads.eng_state_size[guc_class], 610 xe_lrc_engine_state_size(gt, class)); 611 ads_blob_write(ads, ads.golden_context_lrca[guc_class], 612 addr_ggtt); 613 614 addr_ggtt += alloc_size; 615 } 616 } 617 618 static void guc_mapping_table_init_invalid(struct xe_gt *gt, 619 struct iosys_map *info_map) 620 { 621 struct xe_device *xe = gt_to_xe(gt); 622 unsigned int i, j; 623 624 /* Table must be set to invalid values for entries not used */ 625 for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i) 626 for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; ++j) 627 info_map_write(xe, info_map, mapping_table[i][j], 628 GUC_MAX_INSTANCES_PER_CLASS); 629 } 630 631 static void guc_mapping_table_init(struct xe_gt *gt, 632 struct iosys_map *info_map) 633 { 634 struct xe_device *xe = gt_to_xe(gt); 635 struct xe_hw_engine *hwe; 636 enum xe_hw_engine_id id; 637 638 guc_mapping_table_init_invalid(gt, info_map); 639 640 for_each_hw_engine(hwe, gt, id) { 641 u16 guc_logical_instance; 642 u8 guc_class; 643 644 guc_class = xe_hwe_to_guc_class(hwe); 645 guc_logical_instance = xe_hwe_guc_logical_instance(hwe); 646 647 info_map_write(xe, info_map, 648 mapping_table[guc_class][guc_logical_instance], 649 hwe->instance); 650 } 651 } 652 653 static u32 guc_get_capture_engine_mask(struct xe_gt *gt, struct iosys_map *info_map, 654 enum guc_capture_list_class_type capture_class) 655 { 656 struct xe_device *xe = gt_to_xe(gt); 657 u32 mask; 658 659 switch (capture_class) { 660 case GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE: 661 mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS]); 662 mask |= info_map_read(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS]); 663 break; 664 case GUC_CAPTURE_LIST_CLASS_VIDEO: 665 mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS]); 666 break; 667 case GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE: 668 mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS]); 669 break; 670 case GUC_CAPTURE_LIST_CLASS_BLITTER: 671 mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS]); 672 break; 673 case GUC_CAPTURE_LIST_CLASS_GSC_OTHER: 674 mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS]); 675 break; 676 case GUC_CAPTURE_LIST_CLASS_PAGING: 677 mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_PAGING_CLASS]); 678 break; 679 default: 680 mask = 0; 681 } 682 683 return mask; 684 } 685 686 static inline bool get_capture_list(struct xe_guc_ads *ads, struct xe_guc *guc, struct xe_gt *gt, 687 int owner, int type, int class, u32 *total_size, size_t *size, 688 void **pptr) 689 { 690 *size = 0; 691 692 if (!xe_guc_capture_getlistsize(guc, owner, type, class, size)) { 693 if (*total_size + *size > ads->capture_size) 694 xe_gt_dbg(gt, "Capture size overflow :%zu vs %d\n", 695 *total_size + *size, ads->capture_size); 696 else if (!xe_guc_capture_getlist(guc, owner, type, class, pptr)) 697 return false; 698 } 699 700 return true; 701 } 702 703 static int guc_capture_prep_lists(struct xe_guc_ads *ads) 704 { 705 struct xe_guc *guc = ads_to_guc(ads); 706 struct xe_gt *gt = ads_to_gt(ads); 707 u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0; 708 struct iosys_map info_map; 709 size_t size = 0; 710 void *ptr; 711 int i, j; 712 713 /* 714 * GuC Capture's steered reg-list needs to be allocated and initialized 715 * after the GuC-hwconfig is available which guaranteed from here. 716 */ 717 xe_guc_capture_steered_list_init(ads_to_guc(ads)); 718 719 capture_offset = guc_ads_capture_offset(ads); 720 ads_ggtt = xe_bo_ggtt_addr(ads->bo); 721 info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 722 offsetof(struct __guc_ads_blob, system_info)); 723 724 /* first, set aside the first page for a capture_list with zero descriptors */ 725 total_size = PAGE_SIZE; 726 if (!xe_guc_capture_getnullheader(guc, &ptr, &size)) 727 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, ptr, size); 728 729 null_ggtt = ads_ggtt + capture_offset; 730 capture_offset += PAGE_SIZE; 731 732 /* 733 * Populate capture list : at this point adps is already allocated and 734 * mapped to worst case size 735 */ 736 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { 737 bool write_empty_list; 738 739 for (j = 0; j < GUC_CAPTURE_LIST_CLASS_MAX; j++) { 740 u32 engine_mask = guc_get_capture_engine_mask(gt, &info_map, j); 741 /* null list if we dont have said engine or list */ 742 if (!engine_mask) { 743 ads_blob_write(ads, ads.capture_class[i][j], null_ggtt); 744 ads_blob_write(ads, ads.capture_instance[i][j], null_ggtt); 745 continue; 746 } 747 748 /* engine exists: start with engine-class registers */ 749 write_empty_list = get_capture_list(ads, guc, gt, i, 750 GUC_STATE_CAPTURE_TYPE_ENGINE_CLASS, 751 j, &total_size, &size, &ptr); 752 if (!write_empty_list) { 753 ads_blob_write(ads, ads.capture_class[i][j], 754 ads_ggtt + capture_offset); 755 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, 756 ptr, size); 757 total_size += size; 758 capture_offset += size; 759 } else { 760 ads_blob_write(ads, ads.capture_class[i][j], null_ggtt); 761 } 762 763 /* engine exists: next, engine-instance registers */ 764 write_empty_list = get_capture_list(ads, guc, gt, i, 765 GUC_STATE_CAPTURE_TYPE_ENGINE_INSTANCE, 766 j, &total_size, &size, &ptr); 767 if (!write_empty_list) { 768 ads_blob_write(ads, ads.capture_instance[i][j], 769 ads_ggtt + capture_offset); 770 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, 771 ptr, size); 772 total_size += size; 773 capture_offset += size; 774 } else { 775 ads_blob_write(ads, ads.capture_instance[i][j], null_ggtt); 776 } 777 } 778 779 /* global registers is last in our PF/VF loops */ 780 write_empty_list = get_capture_list(ads, guc, gt, i, 781 GUC_STATE_CAPTURE_TYPE_GLOBAL, 782 0, &total_size, &size, &ptr); 783 if (!write_empty_list) { 784 ads_blob_write(ads, ads.capture_global[i], ads_ggtt + capture_offset); 785 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, ptr, 786 size); 787 total_size += size; 788 capture_offset += size; 789 } else { 790 ads_blob_write(ads, ads.capture_global[i], null_ggtt); 791 } 792 } 793 794 if (ads->capture_size != PAGE_ALIGN(total_size)) 795 xe_gt_dbg(gt, "Updated ADS capture size %d (was %d)\n", 796 PAGE_ALIGN(total_size), ads->capture_size); 797 return PAGE_ALIGN(total_size); 798 } 799 800 static void guc_mmio_regset_write_one(struct xe_guc_ads *ads, 801 struct iosys_map *regset_map, 802 struct xe_reg reg, 803 unsigned int n_entry) 804 { 805 struct guc_mmio_reg entry = { 806 .offset = reg.addr, 807 .flags = reg.masked ? GUC_REGSET_MASKED : 0, 808 }; 809 810 if (reg.mcr) { 811 struct xe_reg_mcr mcr_reg = XE_REG_MCR(reg.addr); 812 u8 group, instance; 813 814 bool steer = xe_gt_mcr_get_nonterminated_steering(ads_to_gt(ads), mcr_reg, 815 &group, &instance); 816 817 if (steer) { 818 entry.flags |= FIELD_PREP(GUC_REGSET_STEERING_GROUP, group); 819 entry.flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, instance); 820 entry.flags |= GUC_REGSET_STEERING_NEEDED; 821 } 822 } 823 824 xe_map_memcpy_to(ads_to_xe(ads), regset_map, n_entry * sizeof(entry), 825 &entry, sizeof(entry)); 826 } 827 828 static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads, 829 struct iosys_map *regset_map, 830 struct xe_hw_engine *hwe) 831 { 832 struct xe_hw_engine *hwe_rcs_reset_domain = 833 xe_gt_any_hw_engine_by_reset_domain(hwe->gt, XE_ENGINE_CLASS_RENDER); 834 struct xe_reg_sr_entry *entry; 835 unsigned long idx; 836 unsigned int count = 0; 837 const struct { 838 struct xe_reg reg; 839 bool skip; 840 } *e, extra_regs[] = { 841 { .reg = RING_HWS_PGA(hwe->mmio_base), }, 842 { .reg = RING_IMR(hwe->mmio_base), }, 843 { .reg = CCS_MODE, 844 .skip = hwe != hwe_rcs_reset_domain || !xe_gt_ccs_mode_enabled(hwe->gt) }, 845 }; 846 u32 i; 847 848 BUILD_BUG_ON(ARRAY_SIZE(extra_regs) > ADS_REGSET_EXTRA_MAX); 849 850 xa_for_each(&hwe->reg_sr.xa, idx, entry) 851 guc_mmio_regset_write_one(ads, regset_map, entry->reg, count++); 852 853 for (e = extra_regs; e < extra_regs + ARRAY_SIZE(extra_regs); e++) { 854 if (e->skip) 855 continue; 856 857 guc_mmio_regset_write_one(ads, regset_map, e->reg, count++); 858 } 859 860 if (XE_GT_WA(hwe->gt, 1607983814) && hwe->class == XE_ENGINE_CLASS_RENDER) { 861 for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) { 862 guc_mmio_regset_write_one(ads, regset_map, 863 XELP_LNCFCMOCS(i), count++); 864 } 865 } 866 867 if (XE_GT_WA(hwe->gt, 16023105232)) 868 guc_mmio_regset_write_one(ads, regset_map, 869 RING_IDLEDLY(hwe->mmio_base), 870 count++); 871 872 return count; 873 } 874 875 static void guc_mmio_reg_state_init(struct xe_guc_ads *ads) 876 { 877 size_t regset_offset = guc_ads_regset_offset(ads); 878 struct xe_gt *gt = ads_to_gt(ads); 879 struct xe_hw_engine *hwe; 880 enum xe_hw_engine_id id; 881 u32 addr = xe_bo_ggtt_addr(ads->bo) + regset_offset; 882 struct iosys_map regset_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 883 regset_offset); 884 unsigned int regset_used = 0; 885 886 for_each_hw_engine(hwe, gt, id) { 887 unsigned int count; 888 u8 gc; 889 890 /* 891 * 1. Write all MMIO entries for this exec queue to the table. No 892 * need to worry about fused-off engines and when there are 893 * entries in the regset: the reg_state_list has been zero'ed 894 * by xe_guc_ads_populate() 895 */ 896 count = guc_mmio_regset_write(ads, ®set_map, hwe); 897 if (!count) 898 continue; 899 900 /* 901 * 2. Record in the header (ads.reg_state_list) the address 902 * location and number of entries 903 */ 904 gc = xe_hwe_to_guc_class(hwe); 905 ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].address, addr); 906 ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].count, count); 907 908 addr += count * sizeof(struct guc_mmio_reg); 909 iosys_map_incr(®set_map, count * sizeof(struct guc_mmio_reg)); 910 911 regset_used += count * sizeof(struct guc_mmio_reg); 912 } 913 914 xe_gt_assert(gt, regset_used <= ads->regset_size); 915 } 916 917 static void guc_um_init_params(struct xe_guc_ads *ads) 918 { 919 struct xe_bo *um_bo = ads->um_queue_bo; 920 struct xe_guc *guc = ads_to_guc(ads); 921 struct xe_device *xe = ads_to_xe(ads); 922 u64 base_dpa; 923 u32 base_ggtt; 924 bool with_dpa; 925 int i; 926 927 with_dpa = !xe_guc_using_main_gamctrl_queues(guc); 928 929 if (um_bo) { 930 /* All USM platforms: UM queues in dedicated um_queue_bo */ 931 base_ggtt = xe_bo_ggtt_addr(um_bo); 932 base_dpa = xe_bo_main_addr(um_bo, PAGE_SIZE); 933 } else { 934 /* Platform does not support USM: no UM queues, nothing to do */ 935 return; 936 } 937 938 for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) { 939 /* 940 * Some platforms support USM but not access counters. 941 * Skip ACCESS_COUNTER queue initialization for such 942 * platforms, leaving queue_params[2] zero-initialized 943 * to signal unavailability to the GuC. 944 */ 945 if (i == GUC_UM_HW_QUEUE_ACCESS_COUNTER && 946 !xe->info.has_access_counter) 947 continue; 948 949 ads_blob_write(ads, um_init_params.queue_params[i].base_dpa, 950 with_dpa ? (base_dpa + (i * GUC_UM_QUEUE_SIZE)) : 0); 951 ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address, 952 base_ggtt + (i * GUC_UM_QUEUE_SIZE)); 953 ads_blob_write(ads, um_init_params.queue_params[i].size_in_bytes, 954 GUC_UM_QUEUE_SIZE); 955 } 956 957 ads_blob_write(ads, um_init_params.page_response_timeout_in_us, 958 GUC_PAGE_RES_TIMEOUT_US); 959 } 960 961 static void guc_doorbell_init(struct xe_guc_ads *ads) 962 { 963 struct xe_device *xe = ads_to_xe(ads); 964 struct xe_gt *gt = ads_to_gt(ads); 965 966 if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) { 967 u32 distdbreg = 968 xe_mmio_read32(>->mmio, DIST_DBS_POPULATED); 969 970 ads_blob_write(ads, 971 system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI], 972 REG_FIELD_GET(DOORBELLS_PER_SQIDI_MASK, distdbreg) + 1); 973 } 974 } 975 976 /** 977 * xe_guc_ads_populate_minimal - populate minimal ADS 978 * @ads: Additional data structures object 979 * 980 * This function populates a minimal ADS that does not support submissions but 981 * enough so the GuC can load and the hwconfig table can be read. 982 */ 983 void xe_guc_ads_populate_minimal(struct xe_guc_ads *ads) 984 { 985 struct xe_gt *gt = ads_to_gt(ads); 986 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 987 offsetof(struct __guc_ads_blob, system_info)); 988 u32 base = xe_bo_ggtt_addr(ads->bo); 989 990 xe_gt_assert(gt, ads->bo); 991 992 xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, xe_bo_size(ads->bo)); 993 guc_policies_init(ads); 994 guc_golden_lrc_init(ads); 995 guc_mapping_table_init_invalid(gt, &info_map); 996 guc_doorbell_init(ads); 997 998 ads_blob_write(ads, ads.scheduler_policies, base + 999 offsetof(struct __guc_ads_blob, policies)); 1000 ads_blob_write(ads, ads.gt_system_info, base + 1001 offsetof(struct __guc_ads_blob, system_info)); 1002 ads_blob_write(ads, ads.private_data, base + 1003 guc_ads_private_data_offset(ads)); 1004 } 1005 1006 void xe_guc_ads_populate(struct xe_guc_ads *ads) 1007 { 1008 struct xe_device *xe = ads_to_xe(ads); 1009 struct xe_gt *gt = ads_to_gt(ads); 1010 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 1011 offsetof(struct __guc_ads_blob, system_info)); 1012 u32 base = xe_bo_ggtt_addr(ads->bo); 1013 1014 xe_gt_assert(gt, ads->bo); 1015 1016 xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, xe_bo_size(ads->bo)); 1017 guc_policies_init(ads); 1018 fill_engine_enable_masks(gt, &info_map); 1019 guc_mmio_reg_state_init(ads); 1020 guc_golden_lrc_init(ads); 1021 guc_mapping_table_init(gt, &info_map); 1022 guc_capture_prep_lists(ads); 1023 guc_doorbell_init(ads); 1024 guc_waklv_init(ads); 1025 1026 if (xe->info.has_usm) { 1027 guc_um_init_params(ads); 1028 ads_blob_write(ads, ads.um_init_data, base + 1029 offsetof(struct __guc_ads_blob, um_init_params)); 1030 } 1031 1032 ads_blob_write(ads, ads.scheduler_policies, base + 1033 offsetof(struct __guc_ads_blob, policies)); 1034 ads_blob_write(ads, ads.gt_system_info, base + 1035 offsetof(struct __guc_ads_blob, system_info)); 1036 ads_blob_write(ads, ads.private_data, base + 1037 guc_ads_private_data_offset(ads)); 1038 } 1039 1040 /* 1041 * After the golden LRC's are recorded for each engine class by the first 1042 * submission, copy them to the ADS, as initialized earlier by 1043 * guc_golden_lrc_init(). 1044 */ 1045 static void guc_golden_lrc_populate(struct xe_guc_ads *ads) 1046 { 1047 struct xe_device *xe = ads_to_xe(ads); 1048 struct xe_gt *gt = ads_to_gt(ads); 1049 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 1050 offsetof(struct __guc_ads_blob, system_info)); 1051 size_t total_size = 0, alloc_size, real_size; 1052 u32 offset; 1053 u16 guc_class; 1054 1055 offset = guc_ads_golden_lrc_offset(ads); 1056 1057 for (guc_class = 0; guc_class <= GUC_LAST_ENGINE_CLASS; ++guc_class) { 1058 enum xe_engine_class class = 1059 guc_class_to_engine_class(guc_class); 1060 1061 if (!info_map_read(xe, &info_map, 1062 engine_enabled_masks[guc_class])) 1063 continue; 1064 1065 xe_gt_assert(gt, gt->default_lrc[class]); 1066 1067 real_size = xe_gt_lrc_size(gt, class); 1068 alloc_size = PAGE_ALIGN(real_size); 1069 total_size += alloc_size; 1070 1071 xe_map_memcpy_to(xe, ads_to_map(ads), offset, 1072 gt->default_lrc[class], real_size); 1073 1074 offset += alloc_size; 1075 } 1076 1077 xe_gt_assert(gt, total_size == ads->golden_lrc_size); 1078 } 1079 1080 void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads) 1081 { 1082 guc_golden_lrc_populate(ads); 1083 } 1084 1085 static int guc_ads_action_update_policies(struct xe_guc_ads *ads, u32 policy_offset) 1086 { 1087 struct xe_guc_ct *ct = &ads_to_guc(ads)->ct; 1088 u32 action[] = { 1089 XE_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE, 1090 policy_offset 1091 }; 1092 1093 return xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); 1094 } 1095 1096 /** 1097 * xe_guc_ads_scheduler_policy_toggle_reset - Toggle reset policy 1098 * @ads: Additional data structures object 1099 * @enable_engine_reset: true to enable engine resets, false otherwise 1100 * 1101 * This function update the GuC's engine reset policy. 1102 * 1103 * Return: 0 on success, and negative error code otherwise. 1104 */ 1105 int xe_guc_ads_scheduler_policy_toggle_reset(struct xe_guc_ads *ads, 1106 bool enable_engine_reset) 1107 { 1108 struct guc_policies *policies; 1109 struct xe_guc *guc = ads_to_guc(ads); 1110 CLASS(xe_guc_buf, buf)(&guc->buf, sizeof(*policies)); 1111 1112 if (!xe_guc_buf_is_valid(buf)) 1113 return -ENOBUFS; 1114 1115 policies = xe_guc_buf_cpu_ptr(buf); 1116 memset(policies, 0, sizeof(*policies)); 1117 1118 policies->dpc_promote_time = ads_blob_read(ads, policies.dpc_promote_time); 1119 policies->max_num_work_items = ads_blob_read(ads, policies.max_num_work_items); 1120 policies->is_valid = 1; 1121 1122 if (enable_engine_reset) 1123 policies->global_flags &= ~GLOBAL_POLICY_DISABLE_ENGINE_RESET; 1124 else 1125 policies->global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET; 1126 1127 return guc_ads_action_update_policies(ads, xe_guc_buf_flush(buf)); 1128 } 1129