1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc_ads.h" 7 8 #include <linux/fault-inject.h> 9 10 #include <drm/drm_managed.h> 11 12 #include <generated/xe_wa_oob.h> 13 14 #include "abi/guc_actions_abi.h" 15 #include "regs/xe_engine_regs.h" 16 #include "regs/xe_gt_regs.h" 17 #include "regs/xe_guc_regs.h" 18 #include "xe_bo.h" 19 #include "xe_gt.h" 20 #include "xe_gt_ccs_mode.h" 21 #include "xe_gt_printk.h" 22 #include "xe_guc.h" 23 #include "xe_guc_capture.h" 24 #include "xe_guc_ct.h" 25 #include "xe_hw_engine.h" 26 #include "xe_lrc.h" 27 #include "xe_map.h" 28 #include "xe_mmio.h" 29 #include "xe_platform_types.h" 30 #include "xe_uc_fw.h" 31 #include "xe_wa.h" 32 33 /* Slack of a few additional entries per engine */ 34 #define ADS_REGSET_EXTRA_MAX 8 35 36 static struct xe_guc * 37 ads_to_guc(struct xe_guc_ads *ads) 38 { 39 return container_of(ads, struct xe_guc, ads); 40 } 41 42 static struct xe_gt * 43 ads_to_gt(struct xe_guc_ads *ads) 44 { 45 return container_of(ads, struct xe_gt, uc.guc.ads); 46 } 47 48 static struct xe_device * 49 ads_to_xe(struct xe_guc_ads *ads) 50 { 51 return gt_to_xe(ads_to_gt(ads)); 52 } 53 54 static struct iosys_map * 55 ads_to_map(struct xe_guc_ads *ads) 56 { 57 return &ads->bo->vmap; 58 } 59 60 /* UM Queue parameters: */ 61 #define GUC_UM_QUEUE_SIZE (SZ_64K) 62 #define GUC_PAGE_RES_TIMEOUT_US (-1) 63 64 /* 65 * The Additional Data Struct (ADS) has pointers for different buffers used by 66 * the GuC. One single gem object contains the ADS struct itself (guc_ads) and 67 * all the extra buffers indirectly linked via the ADS struct's entries. 68 * 69 * Layout of the ADS blob allocated for the GuC: 70 * 71 * +---------------------------------------+ <== base 72 * | guc_ads | 73 * +---------------------------------------+ 74 * | guc_policies | 75 * +---------------------------------------+ 76 * | guc_gt_system_info | 77 * +---------------------------------------+ 78 * | guc_engine_usage | 79 * +---------------------------------------+ 80 * | guc_um_init_params | 81 * +---------------------------------------+ <== static 82 * | guc_mmio_reg[countA] (engine 0.0) | 83 * | guc_mmio_reg[countB] (engine 0.1) | 84 * | guc_mmio_reg[countC] (engine 1.0) | 85 * | ... | 86 * +---------------------------------------+ <== dynamic 87 * | padding | 88 * +---------------------------------------+ <== 4K aligned 89 * | golden contexts | 90 * +---------------------------------------+ 91 * | padding | 92 * +---------------------------------------+ <== 4K aligned 93 * | w/a KLVs | 94 * +---------------------------------------+ 95 * | padding | 96 * +---------------------------------------+ <== 4K aligned 97 * | capture lists | 98 * +---------------------------------------+ 99 * | padding | 100 * +---------------------------------------+ <== 4K aligned 101 * | UM queues | 102 * +---------------------------------------+ 103 * | padding | 104 * +---------------------------------------+ <== 4K aligned 105 * | private data | 106 * +---------------------------------------+ 107 * | padding | 108 * +---------------------------------------+ <== 4K aligned 109 */ 110 struct __guc_ads_blob { 111 struct guc_ads ads; 112 struct guc_policies policies; 113 struct guc_gt_system_info system_info; 114 struct guc_engine_usage engine_usage; 115 struct guc_um_init_params um_init_params; 116 /* From here on, location is dynamic! Refer to above diagram. */ 117 struct guc_mmio_reg regset[]; 118 } __packed; 119 120 #define ads_blob_read(ads_, field_) \ 121 xe_map_rd_field(ads_to_xe(ads_), ads_to_map(ads_), 0, \ 122 struct __guc_ads_blob, field_) 123 124 #define ads_blob_write(ads_, field_, val_) \ 125 xe_map_wr_field(ads_to_xe(ads_), ads_to_map(ads_), 0, \ 126 struct __guc_ads_blob, field_, val_) 127 128 #define info_map_write(xe_, map_, field_, val_) \ 129 xe_map_wr_field(xe_, map_, 0, struct guc_gt_system_info, field_, val_) 130 131 #define info_map_read(xe_, map_, field_) \ 132 xe_map_rd_field(xe_, map_, 0, struct guc_gt_system_info, field_) 133 134 static size_t guc_ads_regset_size(struct xe_guc_ads *ads) 135 { 136 struct xe_device *xe = ads_to_xe(ads); 137 138 xe_assert(xe, ads->regset_size); 139 140 return ads->regset_size; 141 } 142 143 static size_t guc_ads_golden_lrc_size(struct xe_guc_ads *ads) 144 { 145 return PAGE_ALIGN(ads->golden_lrc_size); 146 } 147 148 static u32 guc_ads_waklv_size(struct xe_guc_ads *ads) 149 { 150 return PAGE_ALIGN(ads->ads_waklv_size); 151 } 152 153 static size_t guc_ads_capture_size(struct xe_guc_ads *ads) 154 { 155 return PAGE_ALIGN(ads->capture_size); 156 } 157 158 static size_t guc_ads_um_queues_size(struct xe_guc_ads *ads) 159 { 160 struct xe_device *xe = ads_to_xe(ads); 161 162 if (!xe->info.has_usm) 163 return 0; 164 165 return GUC_UM_QUEUE_SIZE * GUC_UM_HW_QUEUE_MAX; 166 } 167 168 static size_t guc_ads_private_data_size(struct xe_guc_ads *ads) 169 { 170 return PAGE_ALIGN(ads_to_guc(ads)->fw.private_data_size); 171 } 172 173 static size_t guc_ads_regset_offset(struct xe_guc_ads *ads) 174 { 175 return offsetof(struct __guc_ads_blob, regset); 176 } 177 178 static size_t guc_ads_golden_lrc_offset(struct xe_guc_ads *ads) 179 { 180 size_t offset; 181 182 offset = guc_ads_regset_offset(ads) + 183 guc_ads_regset_size(ads); 184 185 return PAGE_ALIGN(offset); 186 } 187 188 static size_t guc_ads_waklv_offset(struct xe_guc_ads *ads) 189 { 190 u32 offset; 191 192 offset = guc_ads_golden_lrc_offset(ads) + 193 guc_ads_golden_lrc_size(ads); 194 195 return PAGE_ALIGN(offset); 196 } 197 198 static size_t guc_ads_capture_offset(struct xe_guc_ads *ads) 199 { 200 size_t offset; 201 202 offset = guc_ads_waklv_offset(ads) + 203 guc_ads_waklv_size(ads); 204 205 return PAGE_ALIGN(offset); 206 } 207 208 static size_t guc_ads_um_queues_offset(struct xe_guc_ads *ads) 209 { 210 u32 offset; 211 212 offset = guc_ads_capture_offset(ads) + 213 guc_ads_capture_size(ads); 214 215 return PAGE_ALIGN(offset); 216 } 217 218 static size_t guc_ads_private_data_offset(struct xe_guc_ads *ads) 219 { 220 size_t offset; 221 222 offset = guc_ads_um_queues_offset(ads) + 223 guc_ads_um_queues_size(ads); 224 225 return PAGE_ALIGN(offset); 226 } 227 228 static size_t guc_ads_size(struct xe_guc_ads *ads) 229 { 230 return guc_ads_private_data_offset(ads) + 231 guc_ads_private_data_size(ads); 232 } 233 234 static bool needs_wa_1607983814(struct xe_device *xe) 235 { 236 return GRAPHICS_VERx100(xe) < 1250; 237 } 238 239 static size_t calculate_regset_size(struct xe_gt *gt) 240 { 241 struct xe_reg_sr_entry *sr_entry; 242 unsigned long sr_idx; 243 struct xe_hw_engine *hwe; 244 enum xe_hw_engine_id id; 245 unsigned int count = 0; 246 247 for_each_hw_engine(hwe, gt, id) 248 xa_for_each(&hwe->reg_sr.xa, sr_idx, sr_entry) 249 count++; 250 251 count += ADS_REGSET_EXTRA_MAX * XE_NUM_HW_ENGINES; 252 253 if (needs_wa_1607983814(gt_to_xe(gt))) 254 count += LNCFCMOCS_REG_COUNT; 255 256 return count * sizeof(struct guc_mmio_reg); 257 } 258 259 static u32 engine_enable_mask(struct xe_gt *gt, enum xe_engine_class class) 260 { 261 struct xe_hw_engine *hwe; 262 enum xe_hw_engine_id id; 263 u32 mask = 0; 264 265 for_each_hw_engine(hwe, gt, id) 266 if (hwe->class == class) 267 mask |= BIT(hwe->instance); 268 269 return mask; 270 } 271 272 static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads) 273 { 274 struct xe_gt *gt = ads_to_gt(ads); 275 size_t total_size = 0, alloc_size, real_size; 276 int class; 277 278 for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) { 279 if (!engine_enable_mask(gt, class)) 280 continue; 281 282 real_size = xe_gt_lrc_size(gt, class); 283 alloc_size = PAGE_ALIGN(real_size); 284 total_size += alloc_size; 285 } 286 287 return total_size; 288 } 289 290 static void guc_waklv_enable_one_word(struct xe_guc_ads *ads, 291 enum xe_guc_klv_ids klv_id, 292 u32 value, 293 u32 *offset, u32 *remain) 294 { 295 u32 size; 296 u32 klv_entry[] = { 297 /* 16:16 key/length */ 298 FIELD_PREP(GUC_KLV_0_KEY, klv_id) | 299 FIELD_PREP(GUC_KLV_0_LEN, 1), 300 value, 301 /* 1 dword data */ 302 }; 303 304 size = sizeof(klv_entry); 305 306 if (*remain < size) { 307 drm_warn(&ads_to_xe(ads)->drm, 308 "w/a klv buffer too small to add klv id %d\n", klv_id); 309 } else { 310 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), *offset, 311 klv_entry, size); 312 *offset += size; 313 *remain -= size; 314 } 315 } 316 317 static void guc_waklv_enable_simple(struct xe_guc_ads *ads, 318 enum xe_guc_klv_ids klv_id, u32 *offset, u32 *remain) 319 { 320 u32 klv_entry[] = { 321 /* 16:16 key/length */ 322 FIELD_PREP(GUC_KLV_0_KEY, klv_id) | 323 FIELD_PREP(GUC_KLV_0_LEN, 0), 324 /* 0 dwords data */ 325 }; 326 u32 size; 327 328 size = sizeof(klv_entry); 329 330 if (xe_gt_WARN(ads_to_gt(ads), *remain < size, 331 "w/a klv buffer too small to add klv id %d\n", klv_id)) 332 return; 333 334 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), *offset, 335 klv_entry, size); 336 *offset += size; 337 *remain -= size; 338 } 339 340 static void guc_waklv_init(struct xe_guc_ads *ads) 341 { 342 struct xe_gt *gt = ads_to_gt(ads); 343 u64 addr_ggtt; 344 u32 offset, remain, size; 345 346 offset = guc_ads_waklv_offset(ads); 347 remain = guc_ads_waklv_size(ads); 348 349 if (XE_WA(gt, 14019882105)) 350 guc_waklv_enable_simple(ads, 351 GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED, 352 &offset, &remain); 353 if (XE_WA(gt, 18024947630)) 354 guc_waklv_enable_simple(ads, 355 GUC_WORKAROUND_KLV_ID_GAM_PFQ_SHADOW_TAIL_POLLING, 356 &offset, &remain); 357 if (XE_WA(gt, 16022287689)) 358 guc_waklv_enable_simple(ads, 359 GUC_WORKAROUND_KLV_ID_DISABLE_MTP_DURING_ASYNC_COMPUTE, 360 &offset, &remain); 361 362 /* 363 * On RC6 exit, GuC will write register 0xB04 with the default value provided. As of now, 364 * the default value for this register is determined to be 0xC40. This could change in the 365 * future, so GuC depends on KMD to send it the correct value. 366 */ 367 if (XE_WA(gt, 13011645652)) 368 guc_waklv_enable_one_word(ads, 369 GUC_WA_KLV_NP_RD_WRITE_TO_CLEAR_RCSM_AT_CGP_LATE_RESTORE, 370 0xC40, 371 &offset, &remain); 372 373 if (XE_WA(gt, 14022293748) || XE_WA(gt, 22019794406)) 374 guc_waklv_enable_simple(ads, 375 GUC_WORKAROUND_KLV_ID_BACK_TO_BACK_RCS_ENGINE_RESET, 376 &offset, &remain); 377 378 size = guc_ads_waklv_size(ads) - remain; 379 if (!size) 380 return; 381 382 offset = guc_ads_waklv_offset(ads); 383 addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset; 384 385 ads_blob_write(ads, ads.wa_klv_addr_lo, lower_32_bits(addr_ggtt)); 386 ads_blob_write(ads, ads.wa_klv_addr_hi, upper_32_bits(addr_ggtt)); 387 ads_blob_write(ads, ads.wa_klv_size, size); 388 } 389 390 static int calculate_waklv_size(struct xe_guc_ads *ads) 391 { 392 /* 393 * A single page is both the minimum size possible and 394 * is sufficiently large enough for all current platforms. 395 */ 396 return SZ_4K; 397 } 398 399 #define MAX_GOLDEN_LRC_SIZE (SZ_4K * 64) 400 401 int xe_guc_ads_init(struct xe_guc_ads *ads) 402 { 403 struct xe_device *xe = ads_to_xe(ads); 404 struct xe_gt *gt = ads_to_gt(ads); 405 struct xe_tile *tile = gt_to_tile(gt); 406 struct xe_bo *bo; 407 408 ads->golden_lrc_size = calculate_golden_lrc_size(ads); 409 ads->capture_size = xe_guc_capture_ads_input_worst_size(ads_to_guc(ads)); 410 ads->regset_size = calculate_regset_size(gt); 411 ads->ads_waklv_size = calculate_waklv_size(ads); 412 413 bo = xe_managed_bo_create_pin_map(xe, tile, guc_ads_size(ads) + MAX_GOLDEN_LRC_SIZE, 414 XE_BO_FLAG_SYSTEM | 415 XE_BO_FLAG_GGTT | 416 XE_BO_FLAG_GGTT_INVALIDATE); 417 if (IS_ERR(bo)) 418 return PTR_ERR(bo); 419 420 ads->bo = bo; 421 422 return 0; 423 } 424 ALLOW_ERROR_INJECTION(xe_guc_ads_init, ERRNO); /* See xe_pci_probe() */ 425 426 /** 427 * xe_guc_ads_init_post_hwconfig - initialize ADS post hwconfig load 428 * @ads: Additional data structures object 429 * 430 * Recalculate golden_lrc_size, capture_size and regset_size as the number 431 * hardware engines may have changed after the hwconfig was loaded. Also verify 432 * the new sizes fit in the already allocated ADS buffer object. 433 * 434 * Return: 0 on success, negative error code on error. 435 */ 436 int xe_guc_ads_init_post_hwconfig(struct xe_guc_ads *ads) 437 { 438 struct xe_gt *gt = ads_to_gt(ads); 439 u32 prev_regset_size = ads->regset_size; 440 441 xe_gt_assert(gt, ads->bo); 442 443 ads->golden_lrc_size = calculate_golden_lrc_size(ads); 444 /* Calculate Capture size with worst size */ 445 ads->capture_size = xe_guc_capture_ads_input_worst_size(ads_to_guc(ads)); 446 ads->regset_size = calculate_regset_size(gt); 447 448 xe_gt_assert(gt, ads->golden_lrc_size + 449 (ads->regset_size - prev_regset_size) <= 450 MAX_GOLDEN_LRC_SIZE); 451 452 return 0; 453 } 454 455 static void guc_policies_init(struct xe_guc_ads *ads) 456 { 457 struct xe_device *xe = ads_to_xe(ads); 458 u32 global_flags = 0; 459 460 ads_blob_write(ads, policies.dpc_promote_time, 461 GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US); 462 ads_blob_write(ads, policies.max_num_work_items, 463 GLOBAL_POLICY_MAX_NUM_WI); 464 465 if (xe->wedged.mode == 2) 466 global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET; 467 468 ads_blob_write(ads, policies.global_flags, global_flags); 469 ads_blob_write(ads, policies.is_valid, 1); 470 } 471 472 static void fill_engine_enable_masks(struct xe_gt *gt, 473 struct iosys_map *info_map) 474 { 475 struct xe_device *xe = gt_to_xe(gt); 476 477 info_map_write(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS], 478 engine_enable_mask(gt, XE_ENGINE_CLASS_RENDER)); 479 info_map_write(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 480 engine_enable_mask(gt, XE_ENGINE_CLASS_COPY)); 481 info_map_write(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS], 482 engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_DECODE)); 483 info_map_write(xe, info_map, 484 engine_enabled_masks[GUC_VIDEOENHANCE_CLASS], 485 engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE)); 486 info_map_write(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS], 487 engine_enable_mask(gt, XE_ENGINE_CLASS_COMPUTE)); 488 info_map_write(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS], 489 engine_enable_mask(gt, XE_ENGINE_CLASS_OTHER)); 490 } 491 492 static void guc_prep_golden_lrc_null(struct xe_guc_ads *ads) 493 { 494 struct xe_device *xe = ads_to_xe(ads); 495 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 496 offsetof(struct __guc_ads_blob, system_info)); 497 u8 guc_class; 498 499 for (guc_class = 0; guc_class <= GUC_MAX_ENGINE_CLASSES; ++guc_class) { 500 if (!info_map_read(xe, &info_map, 501 engine_enabled_masks[guc_class])) 502 continue; 503 504 ads_blob_write(ads, ads.eng_state_size[guc_class], 505 guc_ads_golden_lrc_size(ads) - 506 xe_lrc_skip_size(xe)); 507 ads_blob_write(ads, ads.golden_context_lrca[guc_class], 508 xe_bo_ggtt_addr(ads->bo) + 509 guc_ads_golden_lrc_offset(ads)); 510 } 511 } 512 513 static void guc_mapping_table_init_invalid(struct xe_gt *gt, 514 struct iosys_map *info_map) 515 { 516 struct xe_device *xe = gt_to_xe(gt); 517 unsigned int i, j; 518 519 /* Table must be set to invalid values for entries not used */ 520 for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i) 521 for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; ++j) 522 info_map_write(xe, info_map, mapping_table[i][j], 523 GUC_MAX_INSTANCES_PER_CLASS); 524 } 525 526 static void guc_mapping_table_init(struct xe_gt *gt, 527 struct iosys_map *info_map) 528 { 529 struct xe_device *xe = gt_to_xe(gt); 530 struct xe_hw_engine *hwe; 531 enum xe_hw_engine_id id; 532 533 guc_mapping_table_init_invalid(gt, info_map); 534 535 for_each_hw_engine(hwe, gt, id) { 536 u8 guc_class; 537 538 guc_class = xe_engine_class_to_guc_class(hwe->class); 539 info_map_write(xe, info_map, 540 mapping_table[guc_class][hwe->logical_instance], 541 hwe->instance); 542 } 543 } 544 545 static u32 guc_get_capture_engine_mask(struct xe_gt *gt, struct iosys_map *info_map, 546 enum guc_capture_list_class_type capture_class) 547 { 548 struct xe_device *xe = gt_to_xe(gt); 549 u32 mask; 550 551 switch (capture_class) { 552 case GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE: 553 mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_RENDER_CLASS]); 554 mask |= info_map_read(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS]); 555 break; 556 case GUC_CAPTURE_LIST_CLASS_VIDEO: 557 mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_VIDEO_CLASS]); 558 break; 559 case GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE: 560 mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS]); 561 break; 562 case GUC_CAPTURE_LIST_CLASS_BLITTER: 563 mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_BLITTER_CLASS]); 564 break; 565 case GUC_CAPTURE_LIST_CLASS_GSC_OTHER: 566 mask = info_map_read(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS]); 567 break; 568 default: 569 mask = 0; 570 } 571 572 return mask; 573 } 574 575 static inline bool get_capture_list(struct xe_guc_ads *ads, struct xe_guc *guc, struct xe_gt *gt, 576 int owner, int type, int class, u32 *total_size, size_t *size, 577 void **pptr) 578 { 579 *size = 0; 580 581 if (!xe_guc_capture_getlistsize(guc, owner, type, class, size)) { 582 if (*total_size + *size > ads->capture_size) 583 xe_gt_dbg(gt, "Capture size overflow :%zu vs %d\n", 584 *total_size + *size, ads->capture_size); 585 else if (!xe_guc_capture_getlist(guc, owner, type, class, pptr)) 586 return false; 587 } 588 589 return true; 590 } 591 592 static int guc_capture_prep_lists(struct xe_guc_ads *ads) 593 { 594 struct xe_guc *guc = ads_to_guc(ads); 595 struct xe_gt *gt = ads_to_gt(ads); 596 u32 ads_ggtt, capture_offset, null_ggtt, total_size = 0; 597 struct iosys_map info_map; 598 size_t size = 0; 599 void *ptr; 600 int i, j; 601 602 /* 603 * GuC Capture's steered reg-list needs to be allocated and initialized 604 * after the GuC-hwconfig is available which guaranteed from here. 605 */ 606 xe_guc_capture_steered_list_init(ads_to_guc(ads)); 607 608 capture_offset = guc_ads_capture_offset(ads); 609 ads_ggtt = xe_bo_ggtt_addr(ads->bo); 610 info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 611 offsetof(struct __guc_ads_blob, system_info)); 612 613 /* first, set aside the first page for a capture_list with zero descriptors */ 614 total_size = PAGE_SIZE; 615 if (!xe_guc_capture_getnullheader(guc, &ptr, &size)) 616 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, ptr, size); 617 618 null_ggtt = ads_ggtt + capture_offset; 619 capture_offset += PAGE_SIZE; 620 621 /* 622 * Populate capture list : at this point adps is already allocated and 623 * mapped to worst case size 624 */ 625 for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) { 626 bool write_empty_list; 627 628 for (j = 0; j < GUC_CAPTURE_LIST_CLASS_MAX; j++) { 629 u32 engine_mask = guc_get_capture_engine_mask(gt, &info_map, j); 630 /* null list if we dont have said engine or list */ 631 if (!engine_mask) { 632 ads_blob_write(ads, ads.capture_class[i][j], null_ggtt); 633 ads_blob_write(ads, ads.capture_instance[i][j], null_ggtt); 634 continue; 635 } 636 637 /* engine exists: start with engine-class registers */ 638 write_empty_list = get_capture_list(ads, guc, gt, i, 639 GUC_STATE_CAPTURE_TYPE_ENGINE_CLASS, 640 j, &total_size, &size, &ptr); 641 if (!write_empty_list) { 642 ads_blob_write(ads, ads.capture_class[i][j], 643 ads_ggtt + capture_offset); 644 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, 645 ptr, size); 646 total_size += size; 647 capture_offset += size; 648 } else { 649 ads_blob_write(ads, ads.capture_class[i][j], null_ggtt); 650 } 651 652 /* engine exists: next, engine-instance registers */ 653 write_empty_list = get_capture_list(ads, guc, gt, i, 654 GUC_STATE_CAPTURE_TYPE_ENGINE_INSTANCE, 655 j, &total_size, &size, &ptr); 656 if (!write_empty_list) { 657 ads_blob_write(ads, ads.capture_instance[i][j], 658 ads_ggtt + capture_offset); 659 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, 660 ptr, size); 661 total_size += size; 662 capture_offset += size; 663 } else { 664 ads_blob_write(ads, ads.capture_instance[i][j], null_ggtt); 665 } 666 } 667 668 /* global registers is last in our PF/VF loops */ 669 write_empty_list = get_capture_list(ads, guc, gt, i, 670 GUC_STATE_CAPTURE_TYPE_GLOBAL, 671 0, &total_size, &size, &ptr); 672 if (!write_empty_list) { 673 ads_blob_write(ads, ads.capture_global[i], ads_ggtt + capture_offset); 674 xe_map_memcpy_to(ads_to_xe(ads), ads_to_map(ads), capture_offset, ptr, 675 size); 676 total_size += size; 677 capture_offset += size; 678 } else { 679 ads_blob_write(ads, ads.capture_global[i], null_ggtt); 680 } 681 } 682 683 if (ads->capture_size != PAGE_ALIGN(total_size)) 684 xe_gt_dbg(gt, "ADS capture alloc size changed from %d to %d\n", 685 ads->capture_size, PAGE_ALIGN(total_size)); 686 return PAGE_ALIGN(total_size); 687 } 688 689 static void guc_mmio_regset_write_one(struct xe_guc_ads *ads, 690 struct iosys_map *regset_map, 691 struct xe_reg reg, 692 unsigned int n_entry) 693 { 694 struct guc_mmio_reg entry = { 695 .offset = reg.addr, 696 .flags = reg.masked ? GUC_REGSET_MASKED : 0, 697 }; 698 699 xe_map_memcpy_to(ads_to_xe(ads), regset_map, n_entry * sizeof(entry), 700 &entry, sizeof(entry)); 701 } 702 703 static unsigned int guc_mmio_regset_write(struct xe_guc_ads *ads, 704 struct iosys_map *regset_map, 705 struct xe_hw_engine *hwe) 706 { 707 struct xe_device *xe = ads_to_xe(ads); 708 struct xe_hw_engine *hwe_rcs_reset_domain = 709 xe_gt_any_hw_engine_by_reset_domain(hwe->gt, XE_ENGINE_CLASS_RENDER); 710 struct xe_reg_sr_entry *entry; 711 unsigned long idx; 712 unsigned int count = 0; 713 const struct { 714 struct xe_reg reg; 715 bool skip; 716 } *e, extra_regs[] = { 717 { .reg = RING_MODE(hwe->mmio_base), }, 718 { .reg = RING_HWS_PGA(hwe->mmio_base), }, 719 { .reg = RING_IMR(hwe->mmio_base), }, 720 { .reg = RCU_MODE, .skip = hwe != hwe_rcs_reset_domain }, 721 { .reg = CCS_MODE, 722 .skip = hwe != hwe_rcs_reset_domain || !xe_gt_ccs_mode_enabled(hwe->gt) }, 723 }; 724 u32 i; 725 726 BUILD_BUG_ON(ARRAY_SIZE(extra_regs) > ADS_REGSET_EXTRA_MAX); 727 728 xa_for_each(&hwe->reg_sr.xa, idx, entry) 729 guc_mmio_regset_write_one(ads, regset_map, entry->reg, count++); 730 731 for (e = extra_regs; e < extra_regs + ARRAY_SIZE(extra_regs); e++) { 732 if (e->skip) 733 continue; 734 735 guc_mmio_regset_write_one(ads, regset_map, e->reg, count++); 736 } 737 738 /* Wa_1607983814 */ 739 if (needs_wa_1607983814(xe) && hwe->class == XE_ENGINE_CLASS_RENDER) { 740 for (i = 0; i < LNCFCMOCS_REG_COUNT; i++) { 741 guc_mmio_regset_write_one(ads, regset_map, 742 XELP_LNCFCMOCS(i), count++); 743 } 744 } 745 746 return count; 747 } 748 749 static void guc_mmio_reg_state_init(struct xe_guc_ads *ads) 750 { 751 size_t regset_offset = guc_ads_regset_offset(ads); 752 struct xe_gt *gt = ads_to_gt(ads); 753 struct xe_hw_engine *hwe; 754 enum xe_hw_engine_id id; 755 u32 addr = xe_bo_ggtt_addr(ads->bo) + regset_offset; 756 struct iosys_map regset_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 757 regset_offset); 758 unsigned int regset_used = 0; 759 760 for_each_hw_engine(hwe, gt, id) { 761 unsigned int count; 762 u8 gc; 763 764 /* 765 * 1. Write all MMIO entries for this exec queue to the table. No 766 * need to worry about fused-off engines and when there are 767 * entries in the regset: the reg_state_list has been zero'ed 768 * by xe_guc_ads_populate() 769 */ 770 count = guc_mmio_regset_write(ads, ®set_map, hwe); 771 if (!count) 772 continue; 773 774 /* 775 * 2. Record in the header (ads.reg_state_list) the address 776 * location and number of entries 777 */ 778 gc = xe_engine_class_to_guc_class(hwe->class); 779 ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].address, addr); 780 ads_blob_write(ads, ads.reg_state_list[gc][hwe->instance].count, count); 781 782 addr += count * sizeof(struct guc_mmio_reg); 783 iosys_map_incr(®set_map, count * sizeof(struct guc_mmio_reg)); 784 785 regset_used += count * sizeof(struct guc_mmio_reg); 786 } 787 788 xe_gt_assert(gt, regset_used <= ads->regset_size); 789 } 790 791 static void guc_um_init_params(struct xe_guc_ads *ads) 792 { 793 u32 um_queue_offset = guc_ads_um_queues_offset(ads); 794 u64 base_dpa; 795 u32 base_ggtt; 796 int i; 797 798 base_ggtt = xe_bo_ggtt_addr(ads->bo) + um_queue_offset; 799 base_dpa = xe_bo_main_addr(ads->bo, PAGE_SIZE) + um_queue_offset; 800 801 for (i = 0; i < GUC_UM_HW_QUEUE_MAX; ++i) { 802 ads_blob_write(ads, um_init_params.queue_params[i].base_dpa, 803 base_dpa + (i * GUC_UM_QUEUE_SIZE)); 804 ads_blob_write(ads, um_init_params.queue_params[i].base_ggtt_address, 805 base_ggtt + (i * GUC_UM_QUEUE_SIZE)); 806 ads_blob_write(ads, um_init_params.queue_params[i].size_in_bytes, 807 GUC_UM_QUEUE_SIZE); 808 } 809 810 ads_blob_write(ads, um_init_params.page_response_timeout_in_us, 811 GUC_PAGE_RES_TIMEOUT_US); 812 } 813 814 static void guc_doorbell_init(struct xe_guc_ads *ads) 815 { 816 struct xe_device *xe = ads_to_xe(ads); 817 struct xe_gt *gt = ads_to_gt(ads); 818 819 if (GRAPHICS_VER(xe) >= 12 && !IS_DGFX(xe)) { 820 u32 distdbreg = 821 xe_mmio_read32(>->mmio, DIST_DBS_POPULATED); 822 823 ads_blob_write(ads, 824 system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI], 825 REG_FIELD_GET(DOORBELLS_PER_SQIDI_MASK, distdbreg) + 1); 826 } 827 } 828 829 /** 830 * xe_guc_ads_populate_minimal - populate minimal ADS 831 * @ads: Additional data structures object 832 * 833 * This function populates a minimal ADS that does not support submissions but 834 * enough so the GuC can load and the hwconfig table can be read. 835 */ 836 void xe_guc_ads_populate_minimal(struct xe_guc_ads *ads) 837 { 838 struct xe_gt *gt = ads_to_gt(ads); 839 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 840 offsetof(struct __guc_ads_blob, system_info)); 841 u32 base = xe_bo_ggtt_addr(ads->bo); 842 843 xe_gt_assert(gt, ads->bo); 844 845 xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads->bo->size); 846 guc_policies_init(ads); 847 guc_prep_golden_lrc_null(ads); 848 guc_mapping_table_init_invalid(gt, &info_map); 849 guc_doorbell_init(ads); 850 851 ads_blob_write(ads, ads.scheduler_policies, base + 852 offsetof(struct __guc_ads_blob, policies)); 853 ads_blob_write(ads, ads.gt_system_info, base + 854 offsetof(struct __guc_ads_blob, system_info)); 855 ads_blob_write(ads, ads.private_data, base + 856 guc_ads_private_data_offset(ads)); 857 } 858 859 void xe_guc_ads_populate(struct xe_guc_ads *ads) 860 { 861 struct xe_device *xe = ads_to_xe(ads); 862 struct xe_gt *gt = ads_to_gt(ads); 863 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 864 offsetof(struct __guc_ads_blob, system_info)); 865 u32 base = xe_bo_ggtt_addr(ads->bo); 866 867 xe_gt_assert(gt, ads->bo); 868 869 xe_map_memset(ads_to_xe(ads), ads_to_map(ads), 0, 0, ads->bo->size); 870 guc_policies_init(ads); 871 fill_engine_enable_masks(gt, &info_map); 872 guc_mmio_reg_state_init(ads); 873 guc_prep_golden_lrc_null(ads); 874 guc_mapping_table_init(gt, &info_map); 875 guc_capture_prep_lists(ads); 876 guc_doorbell_init(ads); 877 guc_waklv_init(ads); 878 879 if (xe->info.has_usm) { 880 guc_um_init_params(ads); 881 ads_blob_write(ads, ads.um_init_data, base + 882 offsetof(struct __guc_ads_blob, um_init_params)); 883 } 884 885 ads_blob_write(ads, ads.scheduler_policies, base + 886 offsetof(struct __guc_ads_blob, policies)); 887 ads_blob_write(ads, ads.gt_system_info, base + 888 offsetof(struct __guc_ads_blob, system_info)); 889 ads_blob_write(ads, ads.private_data, base + 890 guc_ads_private_data_offset(ads)); 891 } 892 893 static void guc_populate_golden_lrc(struct xe_guc_ads *ads) 894 { 895 struct xe_device *xe = ads_to_xe(ads); 896 struct xe_gt *gt = ads_to_gt(ads); 897 struct iosys_map info_map = IOSYS_MAP_INIT_OFFSET(ads_to_map(ads), 898 offsetof(struct __guc_ads_blob, system_info)); 899 size_t total_size = 0, alloc_size, real_size; 900 u32 addr_ggtt, offset; 901 int class; 902 903 offset = guc_ads_golden_lrc_offset(ads); 904 addr_ggtt = xe_bo_ggtt_addr(ads->bo) + offset; 905 906 for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) { 907 u8 guc_class; 908 909 guc_class = xe_engine_class_to_guc_class(class); 910 911 if (!info_map_read(xe, &info_map, 912 engine_enabled_masks[guc_class])) 913 continue; 914 915 xe_gt_assert(gt, gt->default_lrc[class]); 916 917 real_size = xe_gt_lrc_size(gt, class); 918 alloc_size = PAGE_ALIGN(real_size); 919 total_size += alloc_size; 920 921 /* 922 * This interface is slightly confusing. We need to pass the 923 * base address of the full golden context and the size of just 924 * the engine state, which is the section of the context image 925 * that starts after the execlists LRC registers. This is 926 * required to allow the GuC to restore just the engine state 927 * when a watchdog reset occurs. 928 * We calculate the engine state size by removing the size of 929 * what comes before it in the context image (which is identical 930 * on all engines). 931 */ 932 ads_blob_write(ads, ads.eng_state_size[guc_class], 933 real_size - xe_lrc_skip_size(xe)); 934 ads_blob_write(ads, ads.golden_context_lrca[guc_class], 935 addr_ggtt); 936 937 xe_map_memcpy_to(xe, ads_to_map(ads), offset, 938 gt->default_lrc[class], real_size); 939 940 addr_ggtt += alloc_size; 941 offset += alloc_size; 942 } 943 944 xe_gt_assert(gt, total_size == ads->golden_lrc_size); 945 } 946 947 void xe_guc_ads_populate_post_load(struct xe_guc_ads *ads) 948 { 949 guc_populate_golden_lrc(ads); 950 } 951 952 static int guc_ads_action_update_policies(struct xe_guc_ads *ads, u32 policy_offset) 953 { 954 struct xe_guc_ct *ct = &ads_to_guc(ads)->ct; 955 u32 action[] = { 956 XE_GUC_ACTION_GLOBAL_SCHED_POLICY_CHANGE, 957 policy_offset 958 }; 959 960 return xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); 961 } 962 963 /** 964 * xe_guc_ads_scheduler_policy_toggle_reset - Toggle reset policy 965 * @ads: Additional data structures object 966 * 967 * This function update the GuC's engine reset policy based on wedged.mode. 968 * 969 * Return: 0 on success, and negative error code otherwise. 970 */ 971 int xe_guc_ads_scheduler_policy_toggle_reset(struct xe_guc_ads *ads) 972 { 973 struct xe_device *xe = ads_to_xe(ads); 974 struct xe_gt *gt = ads_to_gt(ads); 975 struct xe_tile *tile = gt_to_tile(gt); 976 struct guc_policies *policies; 977 struct xe_bo *bo; 978 int ret = 0; 979 980 policies = kmalloc(sizeof(*policies), GFP_KERNEL); 981 if (!policies) 982 return -ENOMEM; 983 984 policies->dpc_promote_time = ads_blob_read(ads, policies.dpc_promote_time); 985 policies->max_num_work_items = ads_blob_read(ads, policies.max_num_work_items); 986 policies->is_valid = 1; 987 if (xe->wedged.mode == 2) 988 policies->global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET; 989 else 990 policies->global_flags &= ~GLOBAL_POLICY_DISABLE_ENGINE_RESET; 991 992 bo = xe_managed_bo_create_from_data(xe, tile, policies, sizeof(struct guc_policies), 993 XE_BO_FLAG_VRAM_IF_DGFX(tile) | 994 XE_BO_FLAG_GGTT); 995 if (IS_ERR(bo)) { 996 ret = PTR_ERR(bo); 997 goto out; 998 } 999 1000 ret = guc_ads_action_update_policies(ads, xe_bo_ggtt_addr(bo)); 1001 out: 1002 kfree(policies); 1003 return ret; 1004 } 1005