xref: /linux/drivers/gpu/drm/xe/xe_guc.h (revision c532de5a67a70f8533d495f8f2aaa9a0491c3ad0)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef _XE_GUC_H_
7 #define _XE_GUC_H_
8 
9 #include "xe_gt.h"
10 #include "xe_guc_types.h"
11 #include "xe_hw_engine_types.h"
12 #include "xe_macros.h"
13 
14 /*
15  * GuC version number components are defined to be only 8-bit size,
16  * so converting to a 32bit 8.8.8 integer allows simple (and safe)
17  * numerical comparisons.
18  */
19 #define MAKE_GUC_VER(maj, min, pat)	(((maj) << 16) | ((min) << 8) | (pat))
20 #define MAKE_GUC_VER_STRUCT(ver)	MAKE_GUC_VER((ver).major, (ver).minor, (ver).patch)
21 #define GUC_SUBMIT_VER(guc) \
22 	MAKE_GUC_VER_STRUCT((guc)->fw.versions.found[XE_UC_FW_VER_COMPATIBILITY])
23 #define GUC_FIRMWARE_VER(guc) \
24 	MAKE_GUC_VER_STRUCT((guc)->fw.versions.found[XE_UC_FW_VER_RELEASE])
25 
26 struct drm_printer;
27 
28 void xe_guc_comm_init_early(struct xe_guc *guc);
29 int xe_guc_init(struct xe_guc *guc);
30 int xe_guc_init_post_hwconfig(struct xe_guc *guc);
31 int xe_guc_post_load_init(struct xe_guc *guc);
32 int xe_guc_reset(struct xe_guc *guc);
33 int xe_guc_upload(struct xe_guc *guc);
34 int xe_guc_min_load_for_hwconfig(struct xe_guc *guc);
35 int xe_guc_enable_communication(struct xe_guc *guc);
36 int xe_guc_suspend(struct xe_guc *guc);
37 void xe_guc_notify(struct xe_guc *guc);
38 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr);
39 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len);
40 int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, u32 len,
41 			  u32 *response_buf);
42 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val);
43 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val);
44 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir);
45 void xe_guc_sanitize(struct xe_guc *guc);
46 void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p);
47 int xe_guc_reset_prepare(struct xe_guc *guc);
48 void xe_guc_reset_wait(struct xe_guc *guc);
49 void xe_guc_stop_prepare(struct xe_guc *guc);
50 void xe_guc_stop(struct xe_guc *guc);
51 int xe_guc_start(struct xe_guc *guc);
52 void xe_guc_declare_wedged(struct xe_guc *guc);
53 
54 static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class)
55 {
56 	switch (class) {
57 	case XE_ENGINE_CLASS_RENDER:
58 		return GUC_RENDER_CLASS;
59 	case XE_ENGINE_CLASS_VIDEO_DECODE:
60 		return GUC_VIDEO_CLASS;
61 	case XE_ENGINE_CLASS_VIDEO_ENHANCE:
62 		return GUC_VIDEOENHANCE_CLASS;
63 	case XE_ENGINE_CLASS_COPY:
64 		return GUC_BLITTER_CLASS;
65 	case XE_ENGINE_CLASS_COMPUTE:
66 		return GUC_COMPUTE_CLASS;
67 	case XE_ENGINE_CLASS_OTHER:
68 		return GUC_GSC_OTHER_CLASS;
69 	default:
70 		XE_WARN_ON(class);
71 		return -1;
72 	}
73 }
74 
75 static inline struct xe_gt *guc_to_gt(struct xe_guc *guc)
76 {
77 	return container_of(guc, struct xe_gt, uc.guc);
78 }
79 
80 static inline struct xe_device *guc_to_xe(struct xe_guc *guc)
81 {
82 	return gt_to_xe(guc_to_gt(guc));
83 }
84 
85 #endif
86