1dd08ebf6SMatthew Brost /* SPDX-License-Identifier: MIT */ 2dd08ebf6SMatthew Brost /* 3dd08ebf6SMatthew Brost * Copyright © 2022 Intel Corporation 4dd08ebf6SMatthew Brost */ 5dd08ebf6SMatthew Brost 63457388fSLucas De Marchi #ifndef _XE_GT_TOPOLOGY_H_ 73457388fSLucas De Marchi #define _XE_GT_TOPOLOGY_H_ 8dd08ebf6SMatthew Brost 9dd08ebf6SMatthew Brost #include "xe_gt_types.h" 10dd08ebf6SMatthew Brost 11*bde5d767SZhanjun Dong /* 12*bde5d767SZhanjun Dong * Loop over each DSS with the bit is 1 in geometry or compute mask 13*bde5d767SZhanjun Dong * @dss: iterated DSS bit from the DSS mask 14*bde5d767SZhanjun Dong * @gt: GT structure 15*bde5d767SZhanjun Dong */ 16*bde5d767SZhanjun Dong #define for_each_dss(dss, gt) \ 17*bde5d767SZhanjun Dong for_each_or_bit((dss), \ 18*bde5d767SZhanjun Dong (gt)->fuse_topo.g_dss_mask, \ 19*bde5d767SZhanjun Dong (gt)->fuse_topo.c_dss_mask, \ 20*bde5d767SZhanjun Dong XE_MAX_DSS_FUSE_BITS) 21*bde5d767SZhanjun Dong 22dd08ebf6SMatthew Brost struct drm_printer; 23dd08ebf6SMatthew Brost 24dd08ebf6SMatthew Brost void xe_gt_topology_init(struct xe_gt *gt); 25dd08ebf6SMatthew Brost 26dd08ebf6SMatthew Brost void xe_gt_topology_dump(struct xe_gt *gt, struct drm_printer *p); 27dd08ebf6SMatthew Brost 28dd08ebf6SMatthew Brost unsigned int 291415283bSLucas De Marchi xe_dss_mask_group_ffs(const xe_dss_mask_t mask, int groupsize, int groupnum); 30dd08ebf6SMatthew Brost 31d0e2dd76SMichał Winiarski bool xe_dss_mask_empty(const xe_dss_mask_t mask); 32d0e2dd76SMichał Winiarski 3313fb0c98SMatt Roper bool 3413fb0c98SMatt Roper xe_gt_topology_has_dss_in_quadrant(struct xe_gt *gt, int quad); 3513fb0c98SMatt Roper 363457388fSLucas De Marchi #endif /* _XE_GT_TOPOLOGY_H_ */ 37