1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <drm/drm_managed.h> 7 8 #include "regs/xe_gt_regs.h" 9 #include "xe_assert.h" 10 #include "xe_gt.h" 11 #include "xe_gt_ccs_mode.h" 12 #include "xe_gt_printk.h" 13 #include "xe_gt_sysfs.h" 14 #include "xe_mmio.h" 15 16 static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines) 17 { 18 u32 mode = CCS_MODE_CSLICE_0_3_MASK; /* disable all by default */ 19 int num_slices = hweight32(CCS_MASK(gt)); 20 struct xe_device *xe = gt_to_xe(gt); 21 int width, cslice = 0; 22 u32 config = 0; 23 24 xe_assert(xe, xe_gt_ccs_mode_enabled(gt)); 25 26 xe_assert(xe, num_engines && num_engines <= num_slices); 27 xe_assert(xe, !(num_slices % num_engines)); 28 29 /* 30 * Loop over all available slices and assign each a user engine. 31 * For example, if there are four compute slices available, the 32 * assignment of compute slices to compute engines would be, 33 * 34 * With 1 engine (ccs0): 35 * slice 0, 1, 2, 3: ccs0 36 * 37 * With 2 engines (ccs0, ccs1): 38 * slice 0, 2: ccs0 39 * slice 1, 3: ccs1 40 * 41 * With 4 engines (ccs0, ccs1, ccs2, ccs3): 42 * slice 0: ccs0 43 * slice 1: ccs1 44 * slice 2: ccs2 45 * slice 3: ccs3 46 */ 47 for (width = num_slices / num_engines; width; width--) { 48 struct xe_hw_engine *hwe; 49 enum xe_hw_engine_id id; 50 51 for_each_hw_engine(hwe, gt, id) { 52 if (hwe->class != XE_ENGINE_CLASS_COMPUTE) 53 continue; 54 55 if (hwe->logical_instance >= num_engines) 56 break; 57 58 config |= BIT(hwe->instance) << XE_HW_ENGINE_CCS0; 59 60 /* If a slice is fused off, leave disabled */ 61 while ((CCS_MASK(gt) & BIT(cslice)) == 0) 62 cslice++; 63 64 mode &= ~CCS_MODE_CSLICE(cslice, CCS_MODE_CSLICE_MASK); 65 mode |= CCS_MODE_CSLICE(cslice, hwe->instance); 66 cslice++; 67 } 68 } 69 70 xe_mmio_write32(gt, CCS_MODE, mode); 71 72 xe_gt_dbg(gt, "CCS_MODE=%x config:%08x, num_engines:%d, num_slices:%d\n", 73 mode, config, num_engines, num_slices); 74 } 75 76 void xe_gt_apply_ccs_mode(struct xe_gt *gt) 77 { 78 if (!gt->ccs_mode) 79 return; 80 81 __xe_gt_apply_ccs_mode(gt, gt->ccs_mode); 82 } 83 84 static ssize_t 85 num_cslices_show(struct device *kdev, 86 struct device_attribute *attr, char *buf) 87 { 88 struct xe_gt *gt = kobj_to_gt(&kdev->kobj); 89 90 return sysfs_emit(buf, "%u\n", hweight32(CCS_MASK(gt))); 91 } 92 93 static DEVICE_ATTR_RO(num_cslices); 94 95 static ssize_t 96 ccs_mode_show(struct device *kdev, 97 struct device_attribute *attr, char *buf) 98 { 99 struct xe_gt *gt = kobj_to_gt(&kdev->kobj); 100 101 return sysfs_emit(buf, "%u\n", gt->ccs_mode); 102 } 103 104 static ssize_t 105 ccs_mode_store(struct device *kdev, struct device_attribute *attr, 106 const char *buff, size_t count) 107 { 108 struct xe_gt *gt = kobj_to_gt(&kdev->kobj); 109 struct xe_device *xe = gt_to_xe(gt); 110 u32 num_engines, num_slices; 111 int ret; 112 113 ret = kstrtou32(buff, 0, &num_engines); 114 if (ret) 115 return ret; 116 117 /* 118 * Ensure number of engines specified is valid and there is an 119 * exact multiple of engines for slices. 120 */ 121 num_slices = hweight32(CCS_MASK(gt)); 122 if (!num_engines || num_engines > num_slices || num_slices % num_engines) { 123 xe_gt_dbg(gt, "Invalid compute config, %d engines %d slices\n", 124 num_engines, num_slices); 125 return -EINVAL; 126 } 127 128 /* CCS mode can only be updated when there are no drm clients */ 129 spin_lock(&xe->clients.lock); 130 if (xe->clients.count) { 131 spin_unlock(&xe->clients.lock); 132 return -EBUSY; 133 } 134 135 if (gt->ccs_mode != num_engines) { 136 xe_gt_info(gt, "Setting compute mode to %d\n", num_engines); 137 gt->ccs_mode = num_engines; 138 xe_gt_record_user_engines(gt); 139 xe_gt_reset_async(gt); 140 } 141 142 spin_unlock(&xe->clients.lock); 143 144 return count; 145 } 146 147 static DEVICE_ATTR_RW(ccs_mode); 148 149 static const struct attribute *gt_ccs_mode_attrs[] = { 150 &dev_attr_ccs_mode.attr, 151 &dev_attr_num_cslices.attr, 152 NULL, 153 }; 154 155 static void xe_gt_ccs_mode_sysfs_fini(void *arg) 156 { 157 struct xe_gt *gt = arg; 158 159 sysfs_remove_files(gt->sysfs, gt_ccs_mode_attrs); 160 } 161 162 /** 163 * xe_gt_ccs_mode_sysfs_init - Initialize CCS mode sysfs interfaces 164 * @gt: GT structure 165 * 166 * Through a per-gt 'ccs_mode' sysfs interface, the user can enable a fixed 167 * number of compute hardware engines to which the available compute slices 168 * are to be allocated. This user configuration change triggers a gt reset 169 * and it is expected that there are no open drm clients while doing so. 170 * The number of available compute slices is exposed to user through a per-gt 171 * 'num_cslices' sysfs interface. 172 * 173 * Returns: Returns error value for failure and 0 for success. 174 */ 175 int xe_gt_ccs_mode_sysfs_init(struct xe_gt *gt) 176 { 177 struct xe_device *xe = gt_to_xe(gt); 178 int err; 179 180 if (!xe_gt_ccs_mode_enabled(gt)) 181 return 0; 182 183 err = sysfs_create_files(gt->sysfs, gt_ccs_mode_attrs); 184 if (err) 185 return err; 186 187 return devm_add_action_or_reset(xe->drm.dev, xe_gt_ccs_mode_sysfs_fini, gt); 188 } 189