1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_gt.h" 7 8 #include <linux/minmax.h> 9 10 #include <drm/drm_managed.h> 11 #include <uapi/drm/xe_drm.h> 12 13 #include <generated/xe_wa_oob.h> 14 15 #include "instructions/xe_alu_commands.h" 16 #include "instructions/xe_gfxpipe_commands.h" 17 #include "instructions/xe_mi_commands.h" 18 #include "regs/xe_engine_regs.h" 19 #include "regs/xe_gt_regs.h" 20 #include "xe_assert.h" 21 #include "xe_bb.h" 22 #include "xe_bo.h" 23 #include "xe_device.h" 24 #include "xe_eu_stall.h" 25 #include "xe_exec_queue.h" 26 #include "xe_execlist.h" 27 #include "xe_force_wake.h" 28 #include "xe_ggtt.h" 29 #include "xe_gsc.h" 30 #include "xe_gt_ccs_mode.h" 31 #include "xe_gt_clock.h" 32 #include "xe_gt_freq.h" 33 #include "xe_gt_idle.h" 34 #include "xe_gt_mcr.h" 35 #include "xe_gt_pagefault.h" 36 #include "xe_gt_printk.h" 37 #include "xe_gt_sriov_pf.h" 38 #include "xe_gt_sriov_vf.h" 39 #include "xe_gt_sysfs.h" 40 #include "xe_gt_tlb_invalidation.h" 41 #include "xe_gt_topology.h" 42 #include "xe_guc_exec_queue_types.h" 43 #include "xe_guc_pc.h" 44 #include "xe_hw_fence.h" 45 #include "xe_hw_engine_class_sysfs.h" 46 #include "xe_irq.h" 47 #include "xe_lmtt.h" 48 #include "xe_lrc.h" 49 #include "xe_map.h" 50 #include "xe_migrate.h" 51 #include "xe_mmio.h" 52 #include "xe_pat.h" 53 #include "xe_pm.h" 54 #include "xe_mocs.h" 55 #include "xe_reg_sr.h" 56 #include "xe_ring_ops.h" 57 #include "xe_sa.h" 58 #include "xe_sched_job.h" 59 #include "xe_sriov.h" 60 #include "xe_tuning.h" 61 #include "xe_uc.h" 62 #include "xe_uc_fw.h" 63 #include "xe_vm.h" 64 #include "xe_wa.h" 65 #include "xe_wopcm.h" 66 67 static void gt_fini(struct drm_device *drm, void *arg) 68 { 69 struct xe_gt *gt = arg; 70 71 destroy_workqueue(gt->ordered_wq); 72 } 73 74 struct xe_gt *xe_gt_alloc(struct xe_tile *tile) 75 { 76 struct xe_gt *gt; 77 int err; 78 79 gt = drmm_kzalloc(&tile_to_xe(tile)->drm, sizeof(*gt), GFP_KERNEL); 80 if (!gt) 81 return ERR_PTR(-ENOMEM); 82 83 gt->tile = tile; 84 gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", 85 WQ_MEM_RECLAIM); 86 87 err = drmm_add_action_or_reset(>_to_xe(gt)->drm, gt_fini, gt); 88 if (err) 89 return ERR_PTR(err); 90 91 return gt; 92 } 93 94 void xe_gt_sanitize(struct xe_gt *gt) 95 { 96 /* 97 * FIXME: if xe_uc_sanitize is called here, on TGL driver will not 98 * reload 99 */ 100 gt->uc.guc.submission_state.enabled = false; 101 } 102 103 static void xe_gt_enable_host_l2_vram(struct xe_gt *gt) 104 { 105 unsigned int fw_ref; 106 u32 reg; 107 108 if (!XE_WA(gt, 16023588340)) 109 return; 110 111 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 112 if (!fw_ref) 113 return; 114 115 if (!xe_gt_is_media_type(gt)) { 116 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 117 reg |= CG_DIS_CNTLBUS; 118 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 119 } 120 121 xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0xF); 122 xe_force_wake_put(gt_to_fw(gt), fw_ref); 123 } 124 125 static void xe_gt_disable_host_l2_vram(struct xe_gt *gt) 126 { 127 unsigned int fw_ref; 128 u32 reg; 129 130 if (!XE_WA(gt, 16023588340)) 131 return; 132 133 if (xe_gt_is_media_type(gt)) 134 return; 135 136 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 137 if (!fw_ref) 138 return; 139 140 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 141 reg &= ~CG_DIS_CNTLBUS; 142 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 143 144 xe_force_wake_put(gt_to_fw(gt), fw_ref); 145 } 146 147 static void gt_reset_worker(struct work_struct *w); 148 149 static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q) 150 { 151 struct xe_sched_job *job; 152 struct xe_bb *bb; 153 struct dma_fence *fence; 154 long timeout; 155 156 bb = xe_bb_new(gt, 4, false); 157 if (IS_ERR(bb)) 158 return PTR_ERR(bb); 159 160 job = xe_bb_create_job(q, bb); 161 if (IS_ERR(job)) { 162 xe_bb_free(bb, NULL); 163 return PTR_ERR(job); 164 } 165 166 xe_sched_job_arm(job); 167 fence = dma_fence_get(&job->drm.s_fence->finished); 168 xe_sched_job_push(job); 169 170 timeout = dma_fence_wait_timeout(fence, false, HZ); 171 dma_fence_put(fence); 172 xe_bb_free(bb, NULL); 173 if (timeout < 0) 174 return timeout; 175 else if (!timeout) 176 return -ETIME; 177 178 return 0; 179 } 180 181 static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) 182 { 183 struct xe_reg_sr *sr = &q->hwe->reg_lrc; 184 struct xe_reg_sr_entry *entry; 185 unsigned long idx; 186 struct xe_sched_job *job; 187 struct xe_bb *bb; 188 struct dma_fence *fence; 189 long timeout; 190 int count_rmw = 0; 191 int count = 0; 192 193 if (q->hwe->class == XE_ENGINE_CLASS_RENDER) 194 /* Big enough to emit all of the context's 3DSTATE */ 195 bb = xe_bb_new(gt, xe_gt_lrc_size(gt, q->hwe->class), false); 196 else 197 /* Just pick a large BB size */ 198 bb = xe_bb_new(gt, SZ_4K, false); 199 200 if (IS_ERR(bb)) 201 return PTR_ERR(bb); 202 203 /* count RMW registers as those will be handled separately */ 204 xa_for_each(&sr->xa, idx, entry) { 205 if (entry->reg.masked || entry->clr_bits == ~0) 206 ++count; 207 else 208 ++count_rmw; 209 } 210 211 if (count || count_rmw) 212 xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name); 213 214 if (count) { 215 /* emit single LRI with all non RMW regs */ 216 217 bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); 218 219 xa_for_each(&sr->xa, idx, entry) { 220 struct xe_reg reg = entry->reg; 221 u32 val; 222 223 if (reg.masked) 224 val = entry->clr_bits << 16; 225 else if (entry->clr_bits == ~0) 226 val = 0; 227 else 228 continue; 229 230 val |= entry->set_bits; 231 232 bb->cs[bb->len++] = reg.addr; 233 bb->cs[bb->len++] = val; 234 xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val); 235 } 236 } 237 238 if (count_rmw) { 239 /* emit MI_MATH for each RMW reg */ 240 241 xa_for_each(&sr->xa, idx, entry) { 242 if (entry->reg.masked || entry->clr_bits == ~0) 243 continue; 244 245 bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO; 246 bb->cs[bb->len++] = entry->reg.addr; 247 bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr; 248 249 bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) | 250 MI_LRI_LRM_CS_MMIO; 251 bb->cs[bb->len++] = CS_GPR_REG(0, 1).addr; 252 bb->cs[bb->len++] = entry->clr_bits; 253 bb->cs[bb->len++] = CS_GPR_REG(0, 2).addr; 254 bb->cs[bb->len++] = entry->set_bits; 255 256 bb->cs[bb->len++] = MI_MATH(8); 257 bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCA, REG0); 258 bb->cs[bb->len++] = CS_ALU_INSTR_LOADINV(SRCB, REG1); 259 bb->cs[bb->len++] = CS_ALU_INSTR_AND; 260 bb->cs[bb->len++] = CS_ALU_INSTR_STORE(REG0, ACCU); 261 bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCA, REG0); 262 bb->cs[bb->len++] = CS_ALU_INSTR_LOAD(SRCB, REG2); 263 bb->cs[bb->len++] = CS_ALU_INSTR_OR; 264 bb->cs[bb->len++] = CS_ALU_INSTR_STORE(REG0, ACCU); 265 266 bb->cs[bb->len++] = MI_LOAD_REGISTER_REG | MI_LRR_SRC_CS_MMIO; 267 bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr; 268 bb->cs[bb->len++] = entry->reg.addr; 269 270 xe_gt_dbg(gt, "REG[%#x] = ~%#x|%#x\n", 271 entry->reg.addr, entry->clr_bits, entry->set_bits); 272 } 273 274 /* reset used GPR */ 275 bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(3) | MI_LRI_LRM_CS_MMIO; 276 bb->cs[bb->len++] = CS_GPR_REG(0, 0).addr; 277 bb->cs[bb->len++] = 0; 278 bb->cs[bb->len++] = CS_GPR_REG(0, 1).addr; 279 bb->cs[bb->len++] = 0; 280 bb->cs[bb->len++] = CS_GPR_REG(0, 2).addr; 281 bb->cs[bb->len++] = 0; 282 } 283 284 xe_lrc_emit_hwe_state_instructions(q, bb); 285 286 job = xe_bb_create_job(q, bb); 287 if (IS_ERR(job)) { 288 xe_bb_free(bb, NULL); 289 return PTR_ERR(job); 290 } 291 292 xe_sched_job_arm(job); 293 fence = dma_fence_get(&job->drm.s_fence->finished); 294 xe_sched_job_push(job); 295 296 timeout = dma_fence_wait_timeout(fence, false, HZ); 297 dma_fence_put(fence); 298 xe_bb_free(bb, NULL); 299 if (timeout < 0) 300 return timeout; 301 else if (!timeout) 302 return -ETIME; 303 304 return 0; 305 } 306 307 int xe_gt_record_default_lrcs(struct xe_gt *gt) 308 { 309 struct xe_device *xe = gt_to_xe(gt); 310 struct xe_hw_engine *hwe; 311 enum xe_hw_engine_id id; 312 int err = 0; 313 314 for_each_hw_engine(hwe, gt, id) { 315 struct xe_exec_queue *q, *nop_q; 316 void *default_lrc; 317 318 if (gt->default_lrc[hwe->class]) 319 continue; 320 321 xe_reg_sr_init(&hwe->reg_lrc, hwe->name, xe); 322 xe_wa_process_lrc(hwe); 323 xe_hw_engine_setup_default_lrc_state(hwe); 324 xe_tuning_process_lrc(hwe); 325 326 default_lrc = drmm_kzalloc(&xe->drm, 327 xe_gt_lrc_size(gt, hwe->class), 328 GFP_KERNEL); 329 if (!default_lrc) 330 return -ENOMEM; 331 332 q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 1, 333 hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 334 if (IS_ERR(q)) { 335 err = PTR_ERR(q); 336 xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n", 337 hwe->name, q); 338 return err; 339 } 340 341 /* Prime golden LRC with known good state */ 342 err = emit_wa_job(gt, q); 343 if (err) { 344 xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n", 345 hwe->name, ERR_PTR(err), q->guc->id); 346 goto put_exec_queue; 347 } 348 349 nop_q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 350 1, hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 351 if (IS_ERR(nop_q)) { 352 err = PTR_ERR(nop_q); 353 xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n", 354 hwe->name, nop_q); 355 goto put_exec_queue; 356 } 357 358 /* Switch to different LRC */ 359 err = emit_nop_job(gt, nop_q); 360 if (err) { 361 xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n", 362 hwe->name, ERR_PTR(err), nop_q->guc->id); 363 goto put_nop_q; 364 } 365 366 /* Reload golden LRC to record the effect of any indirect W/A */ 367 err = emit_nop_job(gt, q); 368 if (err) { 369 xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n", 370 hwe->name, ERR_PTR(err), q->guc->id); 371 goto put_nop_q; 372 } 373 374 xe_map_memcpy_from(xe, default_lrc, 375 &q->lrc[0]->bo->vmap, 376 xe_lrc_pphwsp_offset(q->lrc[0]), 377 xe_gt_lrc_size(gt, hwe->class)); 378 379 gt->default_lrc[hwe->class] = default_lrc; 380 put_nop_q: 381 xe_exec_queue_put(nop_q); 382 put_exec_queue: 383 xe_exec_queue_put(q); 384 if (err) 385 break; 386 } 387 388 return err; 389 } 390 391 int xe_gt_init_early(struct xe_gt *gt) 392 { 393 unsigned int fw_ref; 394 int err; 395 396 if (IS_SRIOV_PF(gt_to_xe(gt))) { 397 err = xe_gt_sriov_pf_init_early(gt); 398 if (err) 399 return err; 400 } 401 402 xe_reg_sr_init(>->reg_sr, "GT", gt_to_xe(gt)); 403 404 err = xe_wa_init(gt); 405 if (err) 406 return err; 407 408 err = xe_tuning_init(gt); 409 if (err) 410 return err; 411 412 xe_wa_process_oob(gt); 413 414 xe_force_wake_init_gt(gt, gt_to_fw(gt)); 415 spin_lock_init(>->global_invl_lock); 416 417 err = xe_gt_tlb_invalidation_init_early(gt); 418 if (err) 419 return err; 420 421 xe_mocs_init_early(gt); 422 423 /* 424 * Only after this point can GT-specific MMIO operations 425 * (including things like communication with the GuC) 426 * be performed. 427 */ 428 xe_gt_mmio_init(gt); 429 430 err = xe_uc_init_noalloc(>->uc); 431 if (err) 432 return err; 433 434 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 435 if (!fw_ref) 436 return -ETIMEDOUT; 437 438 xe_gt_mcr_init_early(gt); 439 xe_pat_init(gt); 440 xe_force_wake_put(gt_to_fw(gt), fw_ref); 441 442 return 0; 443 } 444 445 static void dump_pat_on_error(struct xe_gt *gt) 446 { 447 struct drm_printer p; 448 char prefix[32]; 449 450 snprintf(prefix, sizeof(prefix), "[GT%u Error]", gt->info.id); 451 p = drm_dbg_printer(>_to_xe(gt)->drm, DRM_UT_DRIVER, prefix); 452 453 xe_pat_dump(gt, &p); 454 } 455 456 static int gt_init_with_gt_forcewake(struct xe_gt *gt) 457 { 458 unsigned int fw_ref; 459 int err; 460 461 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 462 if (!fw_ref) 463 return -ETIMEDOUT; 464 465 err = xe_uc_init(>->uc); 466 if (err) 467 goto err_force_wake; 468 469 xe_gt_topology_init(gt); 470 xe_gt_mcr_init(gt); 471 xe_gt_enable_host_l2_vram(gt); 472 473 if (!xe_gt_is_media_type(gt)) { 474 err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt); 475 if (err) 476 goto err_force_wake; 477 if (IS_SRIOV_PF(gt_to_xe(gt))) 478 xe_lmtt_init(>_to_tile(gt)->sriov.pf.lmtt); 479 } 480 481 /* Enable per hw engine IRQs */ 482 xe_irq_enable_hwe(gt); 483 484 /* Rerun MCR init as we now have hw engine list */ 485 xe_gt_mcr_init(gt); 486 487 err = xe_hw_engines_init_early(gt); 488 if (err) { 489 dump_pat_on_error(gt); 490 goto err_force_wake; 491 } 492 493 err = xe_hw_engine_class_sysfs_init(gt); 494 if (err) 495 goto err_force_wake; 496 497 /* Initialize CCS mode sysfs after early initialization of HW engines */ 498 err = xe_gt_ccs_mode_sysfs_init(gt); 499 if (err) 500 goto err_force_wake; 501 502 /* 503 * Stash hardware-reported version. Since this register does not exist 504 * on pre-MTL platforms, reading it there will (correctly) return 0. 505 */ 506 gt->info.gmdid = xe_mmio_read32(>->mmio, GMD_ID); 507 508 xe_force_wake_put(gt_to_fw(gt), fw_ref); 509 return 0; 510 511 err_force_wake: 512 xe_force_wake_put(gt_to_fw(gt), fw_ref); 513 514 return err; 515 } 516 517 static int gt_init_with_all_forcewake(struct xe_gt *gt) 518 { 519 unsigned int fw_ref; 520 int err; 521 522 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 523 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 524 err = -ETIMEDOUT; 525 goto err_force_wake; 526 } 527 528 xe_gt_mcr_set_implicit_defaults(gt); 529 xe_wa_process_gt(gt); 530 xe_tuning_process_gt(gt); 531 xe_reg_sr_apply_mmio(>->reg_sr, gt); 532 533 err = xe_gt_clock_init(gt); 534 if (err) 535 goto err_force_wake; 536 537 xe_mocs_init(gt); 538 err = xe_execlist_init(gt); 539 if (err) 540 goto err_force_wake; 541 542 err = xe_hw_engines_init(gt); 543 if (err) 544 goto err_force_wake; 545 546 err = xe_uc_init_post_hwconfig(>->uc); 547 if (err) 548 goto err_force_wake; 549 550 if (!xe_gt_is_media_type(gt)) { 551 /* 552 * USM has its only SA pool to non-block behind user operations 553 */ 554 if (gt_to_xe(gt)->info.has_usm) { 555 struct xe_device *xe = gt_to_xe(gt); 556 557 gt->usm.bb_pool = xe_sa_bo_manager_init(gt_to_tile(gt), 558 IS_DGFX(xe) ? SZ_1M : SZ_512K, 16); 559 if (IS_ERR(gt->usm.bb_pool)) { 560 err = PTR_ERR(gt->usm.bb_pool); 561 goto err_force_wake; 562 } 563 } 564 } 565 566 if (!xe_gt_is_media_type(gt)) { 567 struct xe_tile *tile = gt_to_tile(gt); 568 569 tile->migrate = xe_migrate_init(tile); 570 if (IS_ERR(tile->migrate)) { 571 err = PTR_ERR(tile->migrate); 572 goto err_force_wake; 573 } 574 } 575 576 err = xe_uc_load_hw(>->uc); 577 if (err) 578 goto err_force_wake; 579 580 /* Configure default CCS mode of 1 engine with all resources */ 581 if (xe_gt_ccs_mode_enabled(gt)) { 582 gt->ccs_mode = 1; 583 xe_gt_apply_ccs_mode(gt); 584 } 585 586 if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt)) 587 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 588 589 if (IS_SRIOV_PF(gt_to_xe(gt))) { 590 xe_gt_sriov_pf_init(gt); 591 xe_gt_sriov_pf_init_hw(gt); 592 } 593 594 xe_force_wake_put(gt_to_fw(gt), fw_ref); 595 596 return 0; 597 598 err_force_wake: 599 xe_force_wake_put(gt_to_fw(gt), fw_ref); 600 601 return err; 602 } 603 604 static void xe_gt_fini(void *arg) 605 { 606 struct xe_gt *gt = arg; 607 int i; 608 609 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 610 xe_hw_fence_irq_finish(>->fence_irq[i]); 611 612 xe_gt_disable_host_l2_vram(gt); 613 } 614 615 int xe_gt_init(struct xe_gt *gt) 616 { 617 int err; 618 int i; 619 620 INIT_WORK(>->reset.worker, gt_reset_worker); 621 622 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) { 623 gt->ring_ops[i] = xe_ring_ops_get(gt, i); 624 xe_hw_fence_irq_init(>->fence_irq[i]); 625 } 626 627 err = devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, xe_gt_fini, gt); 628 if (err) 629 return err; 630 631 err = xe_gt_pagefault_init(gt); 632 if (err) 633 return err; 634 635 err = xe_gt_sysfs_init(gt); 636 if (err) 637 return err; 638 639 err = gt_init_with_gt_forcewake(gt); 640 if (err) 641 return err; 642 643 err = xe_gt_idle_init(>->gtidle); 644 if (err) 645 return err; 646 647 err = xe_gt_freq_init(gt); 648 if (err) 649 return err; 650 651 xe_force_wake_init_engines(gt, gt_to_fw(gt)); 652 653 err = gt_init_with_all_forcewake(gt); 654 if (err) 655 return err; 656 657 xe_gt_record_user_engines(gt); 658 659 err = xe_eu_stall_init(gt); 660 if (err) 661 return err; 662 663 return 0; 664 } 665 666 /** 667 * xe_gt_mmio_init() - Initialize GT's MMIO access 668 * @gt: the GT object 669 * 670 * Initialize GT's MMIO accessor, which will be used to access registers inside 671 * this GT. 672 */ 673 void xe_gt_mmio_init(struct xe_gt *gt) 674 { 675 struct xe_tile *tile = gt_to_tile(gt); 676 struct xe_device *xe = tile_to_xe(tile); 677 678 xe_mmio_init(>->mmio, tile, tile->mmio.regs, tile->mmio.regs_size); 679 680 if (gt->info.type == XE_GT_TYPE_MEDIA) { 681 gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET; 682 gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH; 683 } else { 684 gt->mmio.adj_offset = 0; 685 gt->mmio.adj_limit = 0; 686 } 687 688 if (IS_SRIOV_VF(xe)) 689 gt->mmio.sriov_vf_gt = gt; 690 } 691 692 void xe_gt_record_user_engines(struct xe_gt *gt) 693 { 694 struct xe_hw_engine *hwe; 695 enum xe_hw_engine_id id; 696 697 gt->user_engines.mask = 0; 698 memset(gt->user_engines.instances_per_class, 0, 699 sizeof(gt->user_engines.instances_per_class)); 700 701 for_each_hw_engine(hwe, gt, id) { 702 if (xe_hw_engine_is_reserved(hwe)) 703 continue; 704 705 gt->user_engines.mask |= BIT_ULL(id); 706 gt->user_engines.instances_per_class[hwe->class]++; 707 } 708 709 xe_gt_assert(gt, (gt->user_engines.mask | gt->info.engine_mask) 710 == gt->info.engine_mask); 711 } 712 713 static int do_gt_reset(struct xe_gt *gt) 714 { 715 int err; 716 717 if (IS_SRIOV_VF(gt_to_xe(gt))) 718 return xe_gt_sriov_vf_reset(gt); 719 720 xe_gsc_wa_14015076503(gt, true); 721 722 xe_mmio_write32(>->mmio, GDRST, GRDOM_FULL); 723 err = xe_mmio_wait32(>->mmio, GDRST, GRDOM_FULL, 0, 5000, NULL, false); 724 if (err) 725 xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n", 726 ERR_PTR(err)); 727 728 xe_gsc_wa_14015076503(gt, false); 729 730 return err; 731 } 732 733 static int vf_gt_restart(struct xe_gt *gt) 734 { 735 int err; 736 737 err = xe_uc_sanitize_reset(>->uc); 738 if (err) 739 return err; 740 741 err = xe_uc_load_hw(>->uc); 742 if (err) 743 return err; 744 745 err = xe_uc_start(>->uc); 746 if (err) 747 return err; 748 749 return 0; 750 } 751 752 static int do_gt_restart(struct xe_gt *gt) 753 { 754 struct xe_hw_engine *hwe; 755 enum xe_hw_engine_id id; 756 int err; 757 758 if (IS_SRIOV_VF(gt_to_xe(gt))) 759 return vf_gt_restart(gt); 760 761 xe_pat_init(gt); 762 763 xe_gt_enable_host_l2_vram(gt); 764 765 xe_gt_mcr_set_implicit_defaults(gt); 766 xe_reg_sr_apply_mmio(>->reg_sr, gt); 767 768 err = xe_wopcm_init(>->uc.wopcm); 769 if (err) 770 return err; 771 772 for_each_hw_engine(hwe, gt, id) 773 xe_hw_engine_enable_ring(hwe); 774 775 err = xe_uc_sanitize_reset(>->uc); 776 if (err) 777 return err; 778 779 err = xe_uc_load_hw(>->uc); 780 if (err) 781 return err; 782 783 if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt)) 784 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 785 786 if (IS_SRIOV_PF(gt_to_xe(gt))) 787 xe_gt_sriov_pf_init_hw(gt); 788 789 xe_mocs_init(gt); 790 err = xe_uc_start(>->uc); 791 if (err) 792 return err; 793 794 for_each_hw_engine(hwe, gt, id) 795 xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); 796 797 /* Get CCS mode in sync between sw/hw */ 798 xe_gt_apply_ccs_mode(gt); 799 800 /* Restore GT freq to expected values */ 801 xe_gt_sanitize_freq(gt); 802 803 if (IS_SRIOV_PF(gt_to_xe(gt))) 804 xe_gt_sriov_pf_restart(gt); 805 806 return 0; 807 } 808 809 static int gt_reset(struct xe_gt *gt) 810 { 811 unsigned int fw_ref; 812 int err; 813 814 if (xe_device_wedged(gt_to_xe(gt))) 815 return -ECANCELED; 816 817 /* We only support GT resets with GuC submission */ 818 if (!xe_device_uc_enabled(gt_to_xe(gt))) 819 return -ENODEV; 820 821 xe_gt_info(gt, "reset started\n"); 822 823 xe_pm_runtime_get(gt_to_xe(gt)); 824 825 if (xe_fault_inject_gt_reset()) { 826 err = -ECANCELED; 827 goto err_fail; 828 } 829 830 xe_gt_sanitize(gt); 831 832 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 833 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 834 err = -ETIMEDOUT; 835 goto err_out; 836 } 837 838 xe_uc_gucrc_disable(>->uc); 839 xe_uc_stop_prepare(>->uc); 840 xe_gt_pagefault_reset(gt); 841 842 xe_uc_stop(>->uc); 843 844 xe_gt_tlb_invalidation_reset(gt); 845 846 err = do_gt_reset(gt); 847 if (err) 848 goto err_out; 849 850 err = do_gt_restart(gt); 851 if (err) 852 goto err_out; 853 854 xe_force_wake_put(gt_to_fw(gt), fw_ref); 855 xe_pm_runtime_put(gt_to_xe(gt)); 856 857 xe_gt_info(gt, "reset done\n"); 858 859 return 0; 860 861 err_out: 862 xe_force_wake_put(gt_to_fw(gt), fw_ref); 863 XE_WARN_ON(xe_uc_start(>->uc)); 864 err_fail: 865 xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err)); 866 867 xe_device_declare_wedged(gt_to_xe(gt)); 868 xe_pm_runtime_put(gt_to_xe(gt)); 869 870 return err; 871 } 872 873 static void gt_reset_worker(struct work_struct *w) 874 { 875 struct xe_gt *gt = container_of(w, typeof(*gt), reset.worker); 876 877 gt_reset(gt); 878 } 879 880 void xe_gt_reset_async(struct xe_gt *gt) 881 { 882 xe_gt_info(gt, "trying reset from %ps\n", __builtin_return_address(0)); 883 884 /* Don't do a reset while one is already in flight */ 885 if (!xe_fault_inject_gt_reset() && xe_uc_reset_prepare(>->uc)) 886 return; 887 888 xe_gt_info(gt, "reset queued\n"); 889 queue_work(gt->ordered_wq, >->reset.worker); 890 } 891 892 void xe_gt_suspend_prepare(struct xe_gt *gt) 893 { 894 unsigned int fw_ref; 895 896 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 897 898 xe_uc_suspend_prepare(>->uc); 899 900 xe_force_wake_put(gt_to_fw(gt), fw_ref); 901 } 902 903 int xe_gt_suspend(struct xe_gt *gt) 904 { 905 unsigned int fw_ref; 906 int err; 907 908 xe_gt_dbg(gt, "suspending\n"); 909 xe_gt_sanitize(gt); 910 911 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 912 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) 913 goto err_msg; 914 915 err = xe_uc_suspend(>->uc); 916 if (err) 917 goto err_force_wake; 918 919 xe_gt_idle_disable_pg(gt); 920 921 xe_gt_disable_host_l2_vram(gt); 922 923 xe_force_wake_put(gt_to_fw(gt), fw_ref); 924 xe_gt_dbg(gt, "suspended\n"); 925 926 return 0; 927 928 err_msg: 929 err = -ETIMEDOUT; 930 err_force_wake: 931 xe_force_wake_put(gt_to_fw(gt), fw_ref); 932 xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(err)); 933 934 return err; 935 } 936 937 void xe_gt_shutdown(struct xe_gt *gt) 938 { 939 unsigned int fw_ref; 940 941 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 942 do_gt_reset(gt); 943 xe_force_wake_put(gt_to_fw(gt), fw_ref); 944 } 945 946 /** 947 * xe_gt_sanitize_freq() - Restore saved frequencies if necessary. 948 * @gt: the GT object 949 * 950 * Called after driver init/GSC load completes to restore GT frequencies if we 951 * limited them for any WAs. 952 */ 953 int xe_gt_sanitize_freq(struct xe_gt *gt) 954 { 955 int ret = 0; 956 957 if ((!xe_uc_fw_is_available(>->uc.gsc.fw) || 958 xe_uc_fw_is_loaded(>->uc.gsc.fw) || 959 xe_uc_fw_is_in_error_state(>->uc.gsc.fw)) && 960 XE_WA(gt, 22019338487)) 961 ret = xe_guc_pc_restore_stashed_freq(>->uc.guc.pc); 962 963 return ret; 964 } 965 966 int xe_gt_resume(struct xe_gt *gt) 967 { 968 unsigned int fw_ref; 969 int err; 970 971 xe_gt_dbg(gt, "resuming\n"); 972 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 973 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) 974 goto err_msg; 975 976 err = do_gt_restart(gt); 977 if (err) 978 goto err_force_wake; 979 980 xe_gt_idle_enable_pg(gt); 981 982 xe_force_wake_put(gt_to_fw(gt), fw_ref); 983 xe_gt_dbg(gt, "resumed\n"); 984 985 return 0; 986 987 err_msg: 988 err = -ETIMEDOUT; 989 err_force_wake: 990 xe_force_wake_put(gt_to_fw(gt), fw_ref); 991 xe_gt_err(gt, "resume failed (%pe)\n", ERR_PTR(err)); 992 993 return err; 994 } 995 996 struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt, 997 enum xe_engine_class class, 998 u16 instance, bool logical) 999 { 1000 struct xe_hw_engine *hwe; 1001 enum xe_hw_engine_id id; 1002 1003 for_each_hw_engine(hwe, gt, id) 1004 if (hwe->class == class && 1005 ((!logical && hwe->instance == instance) || 1006 (logical && hwe->logical_instance == instance))) 1007 return hwe; 1008 1009 return NULL; 1010 } 1011 1012 struct xe_hw_engine *xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt, 1013 enum xe_engine_class class) 1014 { 1015 struct xe_hw_engine *hwe; 1016 enum xe_hw_engine_id id; 1017 1018 for_each_hw_engine(hwe, gt, id) { 1019 switch (class) { 1020 case XE_ENGINE_CLASS_RENDER: 1021 case XE_ENGINE_CLASS_COMPUTE: 1022 if (hwe->class == XE_ENGINE_CLASS_RENDER || 1023 hwe->class == XE_ENGINE_CLASS_COMPUTE) 1024 return hwe; 1025 break; 1026 default: 1027 if (hwe->class == class) 1028 return hwe; 1029 } 1030 } 1031 1032 return NULL; 1033 } 1034 1035 struct xe_hw_engine *xe_gt_any_hw_engine(struct xe_gt *gt) 1036 { 1037 struct xe_hw_engine *hwe; 1038 enum xe_hw_engine_id id; 1039 1040 for_each_hw_engine(hwe, gt, id) 1041 return hwe; 1042 1043 return NULL; 1044 } 1045 1046 /** 1047 * xe_gt_declare_wedged() - Declare GT wedged 1048 * @gt: the GT object 1049 * 1050 * Wedge the GT which stops all submission, saves desired debug state, and 1051 * cleans up anything which could timeout. 1052 */ 1053 void xe_gt_declare_wedged(struct xe_gt *gt) 1054 { 1055 xe_gt_assert(gt, gt_to_xe(gt)->wedged.mode); 1056 1057 xe_uc_declare_wedged(>->uc); 1058 xe_gt_tlb_invalidation_reset(gt); 1059 } 1060