1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_gt.h" 7 8 #include <linux/minmax.h> 9 10 #include <drm/drm_managed.h> 11 #include <uapi/drm/xe_drm.h> 12 13 #include <generated/xe_wa_oob.h> 14 15 #include "instructions/xe_gfxpipe_commands.h" 16 #include "instructions/xe_mi_commands.h" 17 #include "regs/xe_gt_regs.h" 18 #include "xe_assert.h" 19 #include "xe_bb.h" 20 #include "xe_bo.h" 21 #include "xe_device.h" 22 #include "xe_exec_queue.h" 23 #include "xe_execlist.h" 24 #include "xe_force_wake.h" 25 #include "xe_ggtt.h" 26 #include "xe_gsc.h" 27 #include "xe_gt_ccs_mode.h" 28 #include "xe_gt_clock.h" 29 #include "xe_gt_freq.h" 30 #include "xe_gt_idle.h" 31 #include "xe_gt_mcr.h" 32 #include "xe_gt_pagefault.h" 33 #include "xe_gt_printk.h" 34 #include "xe_gt_sriov_pf.h" 35 #include "xe_gt_sriov_vf.h" 36 #include "xe_gt_sysfs.h" 37 #include "xe_gt_tlb_invalidation.h" 38 #include "xe_gt_topology.h" 39 #include "xe_guc_exec_queue_types.h" 40 #include "xe_guc_pc.h" 41 #include "xe_hw_fence.h" 42 #include "xe_hw_engine_class_sysfs.h" 43 #include "xe_irq.h" 44 #include "xe_lmtt.h" 45 #include "xe_lrc.h" 46 #include "xe_map.h" 47 #include "xe_migrate.h" 48 #include "xe_mmio.h" 49 #include "xe_pat.h" 50 #include "xe_pm.h" 51 #include "xe_mocs.h" 52 #include "xe_reg_sr.h" 53 #include "xe_ring_ops.h" 54 #include "xe_sa.h" 55 #include "xe_sched_job.h" 56 #include "xe_sriov.h" 57 #include "xe_tuning.h" 58 #include "xe_uc.h" 59 #include "xe_uc_fw.h" 60 #include "xe_vm.h" 61 #include "xe_wa.h" 62 #include "xe_wopcm.h" 63 64 static void gt_fini(struct drm_device *drm, void *arg) 65 { 66 struct xe_gt *gt = arg; 67 68 destroy_workqueue(gt->ordered_wq); 69 } 70 71 struct xe_gt *xe_gt_alloc(struct xe_tile *tile) 72 { 73 struct xe_gt *gt; 74 int err; 75 76 gt = drmm_kzalloc(&tile_to_xe(tile)->drm, sizeof(*gt), GFP_KERNEL); 77 if (!gt) 78 return ERR_PTR(-ENOMEM); 79 80 gt->tile = tile; 81 gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", 82 WQ_MEM_RECLAIM); 83 84 err = drmm_add_action_or_reset(>_to_xe(gt)->drm, gt_fini, gt); 85 if (err) 86 return ERR_PTR(err); 87 88 return gt; 89 } 90 91 void xe_gt_sanitize(struct xe_gt *gt) 92 { 93 /* 94 * FIXME: if xe_uc_sanitize is called here, on TGL driver will not 95 * reload 96 */ 97 gt->uc.guc.submission_state.enabled = false; 98 } 99 100 static void xe_gt_enable_host_l2_vram(struct xe_gt *gt) 101 { 102 unsigned int fw_ref; 103 u32 reg; 104 105 if (!XE_WA(gt, 16023588340)) 106 return; 107 108 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 109 if (!fw_ref) 110 return; 111 112 if (!xe_gt_is_media_type(gt)) { 113 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 114 reg |= CG_DIS_CNTLBUS; 115 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 116 } 117 118 xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0x3); 119 xe_force_wake_put(gt_to_fw(gt), fw_ref); 120 } 121 122 static void xe_gt_disable_host_l2_vram(struct xe_gt *gt) 123 { 124 unsigned int fw_ref; 125 u32 reg; 126 127 if (!XE_WA(gt, 16023588340)) 128 return; 129 130 if (xe_gt_is_media_type(gt)) 131 return; 132 133 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 134 if (!fw_ref) 135 return; 136 137 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 138 reg &= ~CG_DIS_CNTLBUS; 139 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 140 141 xe_force_wake_put(gt_to_fw(gt), fw_ref); 142 } 143 144 static void gt_reset_worker(struct work_struct *w); 145 146 static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q) 147 { 148 struct xe_sched_job *job; 149 struct xe_bb *bb; 150 struct dma_fence *fence; 151 long timeout; 152 153 bb = xe_bb_new(gt, 4, false); 154 if (IS_ERR(bb)) 155 return PTR_ERR(bb); 156 157 job = xe_bb_create_job(q, bb); 158 if (IS_ERR(job)) { 159 xe_bb_free(bb, NULL); 160 return PTR_ERR(job); 161 } 162 163 xe_sched_job_arm(job); 164 fence = dma_fence_get(&job->drm.s_fence->finished); 165 xe_sched_job_push(job); 166 167 timeout = dma_fence_wait_timeout(fence, false, HZ); 168 dma_fence_put(fence); 169 xe_bb_free(bb, NULL); 170 if (timeout < 0) 171 return timeout; 172 else if (!timeout) 173 return -ETIME; 174 175 return 0; 176 } 177 178 /* 179 * Convert back from encoded value to type-safe, only to be used when reg.mcr 180 * is true 181 */ 182 static struct xe_reg_mcr to_xe_reg_mcr(const struct xe_reg reg) 183 { 184 return (const struct xe_reg_mcr){.__reg.raw = reg.raw }; 185 } 186 187 static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) 188 { 189 struct xe_reg_sr *sr = &q->hwe->reg_lrc; 190 struct xe_reg_sr_entry *entry; 191 unsigned long idx; 192 struct xe_sched_job *job; 193 struct xe_bb *bb; 194 struct dma_fence *fence; 195 long timeout; 196 int count = 0; 197 198 if (q->hwe->class == XE_ENGINE_CLASS_RENDER) 199 /* Big enough to emit all of the context's 3DSTATE */ 200 bb = xe_bb_new(gt, xe_gt_lrc_size(gt, q->hwe->class), false); 201 else 202 /* Just pick a large BB size */ 203 bb = xe_bb_new(gt, SZ_4K, false); 204 205 if (IS_ERR(bb)) 206 return PTR_ERR(bb); 207 208 xa_for_each(&sr->xa, idx, entry) 209 ++count; 210 211 if (count) { 212 xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name); 213 214 bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); 215 216 xa_for_each(&sr->xa, idx, entry) { 217 struct xe_reg reg = entry->reg; 218 struct xe_reg_mcr reg_mcr = to_xe_reg_mcr(reg); 219 u32 val; 220 221 /* 222 * Skip reading the register if it's not really needed 223 */ 224 if (reg.masked) 225 val = entry->clr_bits << 16; 226 else if (entry->clr_bits + 1) 227 val = (reg.mcr ? 228 xe_gt_mcr_unicast_read_any(gt, reg_mcr) : 229 xe_mmio_read32(>->mmio, reg)) & (~entry->clr_bits); 230 else 231 val = 0; 232 233 val |= entry->set_bits; 234 235 bb->cs[bb->len++] = reg.addr; 236 bb->cs[bb->len++] = val; 237 xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val); 238 } 239 } 240 241 xe_lrc_emit_hwe_state_instructions(q, bb); 242 243 job = xe_bb_create_job(q, bb); 244 if (IS_ERR(job)) { 245 xe_bb_free(bb, NULL); 246 return PTR_ERR(job); 247 } 248 249 xe_sched_job_arm(job); 250 fence = dma_fence_get(&job->drm.s_fence->finished); 251 xe_sched_job_push(job); 252 253 timeout = dma_fence_wait_timeout(fence, false, HZ); 254 dma_fence_put(fence); 255 xe_bb_free(bb, NULL); 256 if (timeout < 0) 257 return timeout; 258 else if (!timeout) 259 return -ETIME; 260 261 return 0; 262 } 263 264 int xe_gt_record_default_lrcs(struct xe_gt *gt) 265 { 266 struct xe_device *xe = gt_to_xe(gt); 267 struct xe_hw_engine *hwe; 268 enum xe_hw_engine_id id; 269 int err = 0; 270 271 for_each_hw_engine(hwe, gt, id) { 272 struct xe_exec_queue *q, *nop_q; 273 void *default_lrc; 274 275 if (gt->default_lrc[hwe->class]) 276 continue; 277 278 xe_reg_sr_init(&hwe->reg_lrc, hwe->name, xe); 279 xe_wa_process_lrc(hwe); 280 xe_hw_engine_setup_default_lrc_state(hwe); 281 xe_tuning_process_lrc(hwe); 282 283 default_lrc = drmm_kzalloc(&xe->drm, 284 xe_gt_lrc_size(gt, hwe->class), 285 GFP_KERNEL); 286 if (!default_lrc) 287 return -ENOMEM; 288 289 q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 1, 290 hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 291 if (IS_ERR(q)) { 292 err = PTR_ERR(q); 293 xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n", 294 hwe->name, q); 295 return err; 296 } 297 298 /* Prime golden LRC with known good state */ 299 err = emit_wa_job(gt, q); 300 if (err) { 301 xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n", 302 hwe->name, ERR_PTR(err), q->guc->id); 303 goto put_exec_queue; 304 } 305 306 nop_q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 307 1, hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 308 if (IS_ERR(nop_q)) { 309 err = PTR_ERR(nop_q); 310 xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n", 311 hwe->name, nop_q); 312 goto put_exec_queue; 313 } 314 315 /* Switch to different LRC */ 316 err = emit_nop_job(gt, nop_q); 317 if (err) { 318 xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n", 319 hwe->name, ERR_PTR(err), nop_q->guc->id); 320 goto put_nop_q; 321 } 322 323 /* Reload golden LRC to record the effect of any indirect W/A */ 324 err = emit_nop_job(gt, q); 325 if (err) { 326 xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n", 327 hwe->name, ERR_PTR(err), q->guc->id); 328 goto put_nop_q; 329 } 330 331 xe_map_memcpy_from(xe, default_lrc, 332 &q->lrc[0]->bo->vmap, 333 xe_lrc_pphwsp_offset(q->lrc[0]), 334 xe_gt_lrc_size(gt, hwe->class)); 335 336 gt->default_lrc[hwe->class] = default_lrc; 337 put_nop_q: 338 xe_exec_queue_put(nop_q); 339 put_exec_queue: 340 xe_exec_queue_put(q); 341 if (err) 342 break; 343 } 344 345 return err; 346 } 347 348 int xe_gt_init_early(struct xe_gt *gt) 349 { 350 int err; 351 352 if (IS_SRIOV_PF(gt_to_xe(gt))) { 353 err = xe_gt_sriov_pf_init_early(gt); 354 if (err) 355 return err; 356 } 357 358 xe_reg_sr_init(>->reg_sr, "GT", gt_to_xe(gt)); 359 360 err = xe_wa_init(gt); 361 if (err) 362 return err; 363 364 xe_wa_process_gt(gt); 365 xe_wa_process_oob(gt); 366 xe_tuning_process_gt(gt); 367 368 xe_force_wake_init_gt(gt, gt_to_fw(gt)); 369 spin_lock_init(>->global_invl_lock); 370 371 err = xe_gt_tlb_invalidation_init_early(gt); 372 if (err) 373 return err; 374 375 return 0; 376 } 377 378 static void dump_pat_on_error(struct xe_gt *gt) 379 { 380 struct drm_printer p; 381 char prefix[32]; 382 383 snprintf(prefix, sizeof(prefix), "[GT%u Error]", gt->info.id); 384 p = drm_dbg_printer(>_to_xe(gt)->drm, DRM_UT_DRIVER, prefix); 385 386 xe_pat_dump(gt, &p); 387 } 388 389 static int gt_fw_domain_init(struct xe_gt *gt) 390 { 391 unsigned int fw_ref; 392 int err; 393 394 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 395 if (!fw_ref) 396 return -ETIMEDOUT; 397 398 if (!xe_gt_is_media_type(gt)) { 399 err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt); 400 if (err) 401 goto err_force_wake; 402 if (IS_SRIOV_PF(gt_to_xe(gt))) 403 xe_lmtt_init(>_to_tile(gt)->sriov.pf.lmtt); 404 } 405 406 /* Enable per hw engine IRQs */ 407 xe_irq_enable_hwe(gt); 408 409 /* Rerun MCR init as we now have hw engine list */ 410 xe_gt_mcr_init(gt); 411 412 err = xe_hw_engines_init_early(gt); 413 if (err) 414 goto err_force_wake; 415 416 err = xe_hw_engine_class_sysfs_init(gt); 417 if (err) 418 goto err_force_wake; 419 420 /* Initialize CCS mode sysfs after early initialization of HW engines */ 421 err = xe_gt_ccs_mode_sysfs_init(gt); 422 if (err) 423 goto err_force_wake; 424 425 /* 426 * Stash hardware-reported version. Since this register does not exist 427 * on pre-MTL platforms, reading it there will (correctly) return 0. 428 */ 429 gt->info.gmdid = xe_mmio_read32(>->mmio, GMD_ID); 430 431 xe_force_wake_put(gt_to_fw(gt), fw_ref); 432 return 0; 433 434 err_force_wake: 435 dump_pat_on_error(gt); 436 xe_force_wake_put(gt_to_fw(gt), fw_ref); 437 438 return err; 439 } 440 441 static int all_fw_domain_init(struct xe_gt *gt) 442 { 443 unsigned int fw_ref; 444 int err; 445 446 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 447 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 448 err = -ETIMEDOUT; 449 goto err_force_wake; 450 } 451 452 xe_gt_mcr_set_implicit_defaults(gt); 453 xe_reg_sr_apply_mmio(>->reg_sr, gt); 454 455 err = xe_gt_clock_init(gt); 456 if (err) 457 goto err_force_wake; 458 459 xe_mocs_init(gt); 460 err = xe_execlist_init(gt); 461 if (err) 462 goto err_force_wake; 463 464 err = xe_hw_engines_init(gt); 465 if (err) 466 goto err_force_wake; 467 468 err = xe_uc_init_post_hwconfig(>->uc); 469 if (err) 470 goto err_force_wake; 471 472 if (!xe_gt_is_media_type(gt)) { 473 /* 474 * USM has its only SA pool to non-block behind user operations 475 */ 476 if (gt_to_xe(gt)->info.has_usm) { 477 struct xe_device *xe = gt_to_xe(gt); 478 479 gt->usm.bb_pool = xe_sa_bo_manager_init(gt_to_tile(gt), 480 IS_DGFX(xe) ? SZ_1M : SZ_512K, 16); 481 if (IS_ERR(gt->usm.bb_pool)) { 482 err = PTR_ERR(gt->usm.bb_pool); 483 goto err_force_wake; 484 } 485 } 486 } 487 488 if (!xe_gt_is_media_type(gt)) { 489 struct xe_tile *tile = gt_to_tile(gt); 490 491 tile->migrate = xe_migrate_init(tile); 492 if (IS_ERR(tile->migrate)) { 493 err = PTR_ERR(tile->migrate); 494 goto err_force_wake; 495 } 496 } 497 498 err = xe_uc_init_hw(>->uc); 499 if (err) 500 goto err_force_wake; 501 502 /* Configure default CCS mode of 1 engine with all resources */ 503 if (xe_gt_ccs_mode_enabled(gt)) { 504 gt->ccs_mode = 1; 505 xe_gt_apply_ccs_mode(gt); 506 } 507 508 if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt)) 509 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 510 511 if (IS_SRIOV_PF(gt_to_xe(gt))) { 512 xe_gt_sriov_pf_init(gt); 513 xe_gt_sriov_pf_init_hw(gt); 514 } 515 516 xe_force_wake_put(gt_to_fw(gt), fw_ref); 517 518 return 0; 519 520 err_force_wake: 521 xe_force_wake_put(gt_to_fw(gt), fw_ref); 522 523 return err; 524 } 525 526 /* 527 * Initialize enough GT to be able to load GuC in order to obtain hwconfig and 528 * enable CTB communication. 529 */ 530 int xe_gt_init_hwconfig(struct xe_gt *gt) 531 { 532 unsigned int fw_ref; 533 int err; 534 535 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 536 if (!fw_ref) 537 return -ETIMEDOUT; 538 539 xe_gt_mcr_init_early(gt); 540 xe_pat_init(gt); 541 542 err = xe_uc_init(>->uc); 543 if (err) 544 goto out_fw; 545 546 err = xe_uc_init_hwconfig(>->uc); 547 if (err) 548 goto out_fw; 549 550 xe_gt_topology_init(gt); 551 xe_gt_mcr_init(gt); 552 xe_gt_enable_host_l2_vram(gt); 553 554 out_fw: 555 xe_force_wake_put(gt_to_fw(gt), fw_ref); 556 return err; 557 } 558 559 static void xe_gt_fini(void *arg) 560 { 561 struct xe_gt *gt = arg; 562 int i; 563 564 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 565 xe_hw_fence_irq_finish(>->fence_irq[i]); 566 567 xe_gt_disable_host_l2_vram(gt); 568 } 569 570 int xe_gt_init(struct xe_gt *gt) 571 { 572 int err; 573 int i; 574 575 INIT_WORK(>->reset.worker, gt_reset_worker); 576 577 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) { 578 gt->ring_ops[i] = xe_ring_ops_get(gt, i); 579 xe_hw_fence_irq_init(>->fence_irq[i]); 580 } 581 582 err = devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, xe_gt_fini, gt); 583 if (err) 584 return err; 585 586 err = xe_gt_pagefault_init(gt); 587 if (err) 588 return err; 589 590 xe_mocs_init_early(gt); 591 592 err = xe_gt_sysfs_init(gt); 593 if (err) 594 return err; 595 596 err = gt_fw_domain_init(gt); 597 if (err) 598 return err; 599 600 err = xe_gt_idle_init(>->gtidle); 601 if (err) 602 return err; 603 604 err = xe_gt_freq_init(gt); 605 if (err) 606 return err; 607 608 xe_force_wake_init_engines(gt, gt_to_fw(gt)); 609 610 err = all_fw_domain_init(gt); 611 if (err) 612 return err; 613 614 xe_gt_record_user_engines(gt); 615 616 return 0; 617 } 618 619 /** 620 * xe_gt_mmio_init() - Initialize GT's MMIO access 621 * @gt: the GT object 622 * 623 * Initialize GT's MMIO accessor, which will be used to access registers inside 624 * this GT. 625 */ 626 void xe_gt_mmio_init(struct xe_gt *gt) 627 { 628 struct xe_tile *tile = gt_to_tile(gt); 629 struct xe_device *xe = tile_to_xe(tile); 630 631 xe_mmio_init(>->mmio, tile, tile->mmio.regs, tile->mmio.regs_size); 632 633 if (gt->info.type == XE_GT_TYPE_MEDIA) { 634 gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET; 635 gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH; 636 } else { 637 gt->mmio.adj_offset = 0; 638 gt->mmio.adj_limit = 0; 639 } 640 641 if (IS_SRIOV_VF(xe)) 642 gt->mmio.sriov_vf_gt = gt; 643 } 644 645 void xe_gt_record_user_engines(struct xe_gt *gt) 646 { 647 struct xe_hw_engine *hwe; 648 enum xe_hw_engine_id id; 649 650 gt->user_engines.mask = 0; 651 memset(gt->user_engines.instances_per_class, 0, 652 sizeof(gt->user_engines.instances_per_class)); 653 654 for_each_hw_engine(hwe, gt, id) { 655 if (xe_hw_engine_is_reserved(hwe)) 656 continue; 657 658 gt->user_engines.mask |= BIT_ULL(id); 659 gt->user_engines.instances_per_class[hwe->class]++; 660 } 661 662 xe_gt_assert(gt, (gt->user_engines.mask | gt->info.engine_mask) 663 == gt->info.engine_mask); 664 } 665 666 static int do_gt_reset(struct xe_gt *gt) 667 { 668 int err; 669 670 if (IS_SRIOV_VF(gt_to_xe(gt))) 671 return xe_gt_sriov_vf_reset(gt); 672 673 xe_gsc_wa_14015076503(gt, true); 674 675 xe_mmio_write32(>->mmio, GDRST, GRDOM_FULL); 676 err = xe_mmio_wait32(>->mmio, GDRST, GRDOM_FULL, 0, 5000, NULL, false); 677 if (err) 678 xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n", 679 ERR_PTR(err)); 680 681 xe_gsc_wa_14015076503(gt, false); 682 683 return err; 684 } 685 686 static int vf_gt_restart(struct xe_gt *gt) 687 { 688 int err; 689 690 err = xe_uc_sanitize_reset(>->uc); 691 if (err) 692 return err; 693 694 err = xe_uc_init_hw(>->uc); 695 if (err) 696 return err; 697 698 err = xe_uc_start(>->uc); 699 if (err) 700 return err; 701 702 return 0; 703 } 704 705 static int do_gt_restart(struct xe_gt *gt) 706 { 707 struct xe_hw_engine *hwe; 708 enum xe_hw_engine_id id; 709 int err; 710 711 if (IS_SRIOV_VF(gt_to_xe(gt))) 712 return vf_gt_restart(gt); 713 714 xe_pat_init(gt); 715 716 xe_gt_enable_host_l2_vram(gt); 717 718 xe_gt_mcr_set_implicit_defaults(gt); 719 xe_reg_sr_apply_mmio(>->reg_sr, gt); 720 721 err = xe_wopcm_init(>->uc.wopcm); 722 if (err) 723 return err; 724 725 for_each_hw_engine(hwe, gt, id) 726 xe_hw_engine_enable_ring(hwe); 727 728 err = xe_uc_sanitize_reset(>->uc); 729 if (err) 730 return err; 731 732 err = xe_uc_init_hw(>->uc); 733 if (err) 734 return err; 735 736 if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt)) 737 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 738 739 if (IS_SRIOV_PF(gt_to_xe(gt))) 740 xe_gt_sriov_pf_init_hw(gt); 741 742 xe_mocs_init(gt); 743 err = xe_uc_start(>->uc); 744 if (err) 745 return err; 746 747 for_each_hw_engine(hwe, gt, id) 748 xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); 749 750 /* Get CCS mode in sync between sw/hw */ 751 xe_gt_apply_ccs_mode(gt); 752 753 /* Restore GT freq to expected values */ 754 xe_gt_sanitize_freq(gt); 755 756 if (IS_SRIOV_PF(gt_to_xe(gt))) 757 xe_gt_sriov_pf_restart(gt); 758 759 return 0; 760 } 761 762 static int gt_reset(struct xe_gt *gt) 763 { 764 unsigned int fw_ref; 765 int err; 766 767 if (xe_device_wedged(gt_to_xe(gt))) 768 return -ECANCELED; 769 770 /* We only support GT resets with GuC submission */ 771 if (!xe_device_uc_enabled(gt_to_xe(gt))) 772 return -ENODEV; 773 774 xe_gt_info(gt, "reset started\n"); 775 776 xe_pm_runtime_get(gt_to_xe(gt)); 777 778 if (xe_fault_inject_gt_reset()) { 779 err = -ECANCELED; 780 goto err_fail; 781 } 782 783 xe_gt_sanitize(gt); 784 785 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 786 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 787 err = -ETIMEDOUT; 788 goto err_out; 789 } 790 791 xe_uc_gucrc_disable(>->uc); 792 xe_uc_stop_prepare(>->uc); 793 xe_gt_pagefault_reset(gt); 794 795 xe_uc_stop(>->uc); 796 797 xe_gt_tlb_invalidation_reset(gt); 798 799 err = do_gt_reset(gt); 800 if (err) 801 goto err_out; 802 803 err = do_gt_restart(gt); 804 if (err) 805 goto err_out; 806 807 xe_force_wake_put(gt_to_fw(gt), fw_ref); 808 xe_pm_runtime_put(gt_to_xe(gt)); 809 810 xe_gt_info(gt, "reset done\n"); 811 812 return 0; 813 814 err_out: 815 xe_force_wake_put(gt_to_fw(gt), fw_ref); 816 XE_WARN_ON(xe_uc_start(>->uc)); 817 err_fail: 818 xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err)); 819 820 xe_device_declare_wedged(gt_to_xe(gt)); 821 xe_pm_runtime_put(gt_to_xe(gt)); 822 823 return err; 824 } 825 826 static void gt_reset_worker(struct work_struct *w) 827 { 828 struct xe_gt *gt = container_of(w, typeof(*gt), reset.worker); 829 830 gt_reset(gt); 831 } 832 833 void xe_gt_reset_async(struct xe_gt *gt) 834 { 835 xe_gt_info(gt, "trying reset from %ps\n", __builtin_return_address(0)); 836 837 /* Don't do a reset while one is already in flight */ 838 if (!xe_fault_inject_gt_reset() && xe_uc_reset_prepare(>->uc)) 839 return; 840 841 xe_gt_info(gt, "reset queued\n"); 842 queue_work(gt->ordered_wq, >->reset.worker); 843 } 844 845 void xe_gt_suspend_prepare(struct xe_gt *gt) 846 { 847 unsigned int fw_ref; 848 849 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 850 851 xe_uc_stop_prepare(>->uc); 852 853 xe_force_wake_put(gt_to_fw(gt), fw_ref); 854 } 855 856 int xe_gt_suspend(struct xe_gt *gt) 857 { 858 unsigned int fw_ref; 859 int err; 860 861 xe_gt_dbg(gt, "suspending\n"); 862 xe_gt_sanitize(gt); 863 864 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 865 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) 866 goto err_msg; 867 868 err = xe_uc_suspend(>->uc); 869 if (err) 870 goto err_force_wake; 871 872 xe_gt_idle_disable_pg(gt); 873 874 xe_gt_disable_host_l2_vram(gt); 875 876 xe_force_wake_put(gt_to_fw(gt), fw_ref); 877 xe_gt_dbg(gt, "suspended\n"); 878 879 return 0; 880 881 err_msg: 882 err = -ETIMEDOUT; 883 err_force_wake: 884 xe_force_wake_put(gt_to_fw(gt), fw_ref); 885 xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(err)); 886 887 return err; 888 } 889 890 void xe_gt_shutdown(struct xe_gt *gt) 891 { 892 unsigned int fw_ref; 893 894 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 895 do_gt_reset(gt); 896 xe_force_wake_put(gt_to_fw(gt), fw_ref); 897 } 898 899 /** 900 * xe_gt_sanitize_freq() - Restore saved frequencies if necessary. 901 * @gt: the GT object 902 * 903 * Called after driver init/GSC load completes to restore GT frequencies if we 904 * limited them for any WAs. 905 */ 906 int xe_gt_sanitize_freq(struct xe_gt *gt) 907 { 908 int ret = 0; 909 910 if ((!xe_uc_fw_is_available(>->uc.gsc.fw) || 911 xe_uc_fw_is_loaded(>->uc.gsc.fw) || 912 xe_uc_fw_is_in_error_state(>->uc.gsc.fw)) && 913 XE_WA(gt, 22019338487)) 914 ret = xe_guc_pc_restore_stashed_freq(>->uc.guc.pc); 915 916 return ret; 917 } 918 919 int xe_gt_resume(struct xe_gt *gt) 920 { 921 unsigned int fw_ref; 922 int err; 923 924 xe_gt_dbg(gt, "resuming\n"); 925 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 926 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) 927 goto err_msg; 928 929 err = do_gt_restart(gt); 930 if (err) 931 goto err_force_wake; 932 933 xe_gt_idle_enable_pg(gt); 934 935 xe_force_wake_put(gt_to_fw(gt), fw_ref); 936 xe_gt_dbg(gt, "resumed\n"); 937 938 return 0; 939 940 err_msg: 941 err = -ETIMEDOUT; 942 err_force_wake: 943 xe_force_wake_put(gt_to_fw(gt), fw_ref); 944 xe_gt_err(gt, "resume failed (%pe)\n", ERR_PTR(err)); 945 946 return err; 947 } 948 949 struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt, 950 enum xe_engine_class class, 951 u16 instance, bool logical) 952 { 953 struct xe_hw_engine *hwe; 954 enum xe_hw_engine_id id; 955 956 for_each_hw_engine(hwe, gt, id) 957 if (hwe->class == class && 958 ((!logical && hwe->instance == instance) || 959 (logical && hwe->logical_instance == instance))) 960 return hwe; 961 962 return NULL; 963 } 964 965 struct xe_hw_engine *xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt, 966 enum xe_engine_class class) 967 { 968 struct xe_hw_engine *hwe; 969 enum xe_hw_engine_id id; 970 971 for_each_hw_engine(hwe, gt, id) { 972 switch (class) { 973 case XE_ENGINE_CLASS_RENDER: 974 case XE_ENGINE_CLASS_COMPUTE: 975 if (hwe->class == XE_ENGINE_CLASS_RENDER || 976 hwe->class == XE_ENGINE_CLASS_COMPUTE) 977 return hwe; 978 break; 979 default: 980 if (hwe->class == class) 981 return hwe; 982 } 983 } 984 985 return NULL; 986 } 987 988 struct xe_hw_engine *xe_gt_any_hw_engine(struct xe_gt *gt) 989 { 990 struct xe_hw_engine *hwe; 991 enum xe_hw_engine_id id; 992 993 for_each_hw_engine(hwe, gt, id) 994 return hwe; 995 996 return NULL; 997 } 998 999 /** 1000 * xe_gt_declare_wedged() - Declare GT wedged 1001 * @gt: the GT object 1002 * 1003 * Wedge the GT which stops all submission, saves desired debug state, and 1004 * cleans up anything which could timeout. 1005 */ 1006 void xe_gt_declare_wedged(struct xe_gt *gt) 1007 { 1008 xe_gt_assert(gt, gt_to_xe(gt)->wedged.mode); 1009 1010 xe_uc_declare_wedged(>->uc); 1011 xe_gt_tlb_invalidation_reset(gt); 1012 } 1013