1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_gt.h" 7 8 #include <linux/minmax.h> 9 10 #include <drm/drm_managed.h> 11 #include <uapi/drm/xe_drm.h> 12 13 #include <generated/xe_device_wa_oob.h> 14 #include <generated/xe_wa_oob.h> 15 16 #include "instructions/xe_alu_commands.h" 17 #include "instructions/xe_mi_commands.h" 18 #include "regs/xe_engine_regs.h" 19 #include "regs/xe_gt_regs.h" 20 #include "xe_assert.h" 21 #include "xe_bb.h" 22 #include "xe_device.h" 23 #include "xe_eu_stall.h" 24 #include "xe_exec_queue.h" 25 #include "xe_execlist.h" 26 #include "xe_force_wake.h" 27 #include "xe_ggtt.h" 28 #include "xe_gsc.h" 29 #include "xe_gt_ccs_mode.h" 30 #include "xe_gt_clock.h" 31 #include "xe_gt_freq.h" 32 #include "xe_gt_idle.h" 33 #include "xe_gt_mcr.h" 34 #include "xe_gt_printk.h" 35 #include "xe_gt_sriov_pf.h" 36 #include "xe_gt_sriov_vf.h" 37 #include "xe_gt_stats.h" 38 #include "xe_gt_sysfs.h" 39 #include "xe_gt_topology.h" 40 #include "xe_guc_exec_queue_types.h" 41 #include "xe_guc_pc.h" 42 #include "xe_guc_rc.h" 43 #include "xe_guc_submit.h" 44 #include "xe_hw_fence.h" 45 #include "xe_hw_engine_class_sysfs.h" 46 #include "xe_irq.h" 47 #include "xe_lmtt.h" 48 #include "xe_lrc.h" 49 #include "xe_map.h" 50 #include "xe_migrate.h" 51 #include "xe_mmio.h" 52 #include "xe_pagefault.h" 53 #include "xe_pat.h" 54 #include "xe_pm.h" 55 #include "xe_mocs.h" 56 #include "xe_reg_sr.h" 57 #include "xe_ring_ops.h" 58 #include "xe_sa.h" 59 #include "xe_sched_job.h" 60 #include "xe_sriov.h" 61 #include "xe_tlb_inval.h" 62 #include "xe_tuning.h" 63 #include "xe_uc.h" 64 #include "xe_uc_fw.h" 65 #include "xe_vm.h" 66 #include "xe_wa.h" 67 #include "xe_wopcm.h" 68 69 struct xe_gt *xe_gt_alloc(struct xe_tile *tile) 70 { 71 struct xe_device *xe = tile_to_xe(tile); 72 struct drm_device *drm = &xe->drm; 73 bool shared_wq = xe->info.needs_shared_vf_gt_wq && tile->primary_gt && 74 IS_SRIOV_VF(xe); 75 struct workqueue_struct *ordered_wq; 76 struct xe_gt *gt; 77 78 gt = drmm_kzalloc(drm, sizeof(*gt), GFP_KERNEL); 79 if (!gt) 80 return ERR_PTR(-ENOMEM); 81 82 gt->tile = tile; 83 if (shared_wq && tile->primary_gt->ordered_wq) 84 ordered_wq = tile->primary_gt->ordered_wq; 85 else 86 ordered_wq = drmm_alloc_ordered_workqueue(drm, "gt-ordered-wq", 87 WQ_MEM_RECLAIM); 88 if (IS_ERR(ordered_wq)) 89 return ERR_CAST(ordered_wq); 90 91 gt->ordered_wq = ordered_wq; 92 93 return gt; 94 } 95 96 void xe_gt_sanitize(struct xe_gt *gt) 97 { 98 /* 99 * FIXME: if xe_uc_sanitize is called here, on TGL driver will not 100 * reload 101 */ 102 xe_guc_submit_disable(>->uc.guc); 103 } 104 105 static void xe_gt_enable_host_l2_vram(struct xe_gt *gt) 106 { 107 u32 reg; 108 109 if (!XE_GT_WA(gt, 16023588340)) 110 return; 111 112 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 113 if (!fw_ref.domains) 114 return; 115 116 if (xe_gt_is_main_type(gt)) { 117 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 118 reg |= CG_DIS_CNTLBUS; 119 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 120 } 121 122 xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0xF); 123 } 124 125 static void xe_gt_disable_host_l2_vram(struct xe_gt *gt) 126 { 127 u32 reg; 128 129 if (!XE_GT_WA(gt, 16023588340)) 130 return; 131 132 if (xe_gt_is_media_type(gt)) 133 return; 134 135 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 136 if (!fw_ref.domains) 137 return; 138 139 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 140 reg &= ~CG_DIS_CNTLBUS; 141 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 142 } 143 144 static void xe_gt_enable_comp_1wcoh(struct xe_gt *gt) 145 { 146 struct xe_device *xe = gt_to_xe(gt); 147 u32 reg; 148 149 if (IS_SRIOV_VF(xe)) 150 return; 151 152 if (GRAPHICS_VER(xe) >= 30 && xe->info.has_flat_ccs) { 153 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 154 if (!fw_ref.domains) 155 return; 156 157 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 158 reg |= EN_CMP_1WCOH; 159 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 160 161 if (xe_gt_is_media_type(gt)) { 162 xe_mmio_rmw32(>->mmio, XE2_GAMWALK_CTRL_MEDIA, 0, EN_CMP_1WCOH_GW); 163 } else { 164 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMWALK_CTRL_3D); 165 reg |= EN_CMP_1WCOH_GW; 166 xe_gt_mcr_multicast_write(gt, XE2_GAMWALK_CTRL_3D, reg); 167 } 168 } 169 } 170 171 static void gt_reset_worker(struct work_struct *w); 172 173 static int emit_job_sync(struct xe_exec_queue *q, struct xe_bb *bb, 174 long timeout_jiffies) 175 { 176 struct xe_sched_job *job; 177 struct dma_fence *fence; 178 long timeout; 179 180 job = xe_bb_create_job(q, bb); 181 if (IS_ERR(job)) 182 return PTR_ERR(job); 183 184 xe_sched_job_arm(job); 185 fence = dma_fence_get(&job->drm.s_fence->finished); 186 xe_sched_job_push(job); 187 188 timeout = dma_fence_wait_timeout(fence, false, timeout_jiffies); 189 dma_fence_put(fence); 190 if (timeout < 0) 191 return timeout; 192 else if (!timeout) 193 return -ETIME; 194 195 return 0; 196 } 197 198 static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q) 199 { 200 struct xe_bb *bb; 201 int ret; 202 203 bb = xe_bb_new(gt, 4, false); 204 if (IS_ERR(bb)) 205 return PTR_ERR(bb); 206 207 ret = emit_job_sync(q, bb, HZ); 208 xe_bb_free(bb, NULL); 209 210 return ret; 211 } 212 213 /* Dwords required to emit a RMW of a register */ 214 #define EMIT_RMW_DW 20 215 216 static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) 217 { 218 struct xe_hw_engine *hwe = q->hwe; 219 struct xe_reg_sr *sr = &hwe->reg_lrc; 220 struct xe_reg_sr_entry *entry; 221 int count_rmw = 0, count_rmw_mcr = 0, count = 0, ret; 222 unsigned long idx; 223 struct xe_bb *bb; 224 size_t bb_len = 0; 225 u32 *cs; 226 227 /* count RMW registers as those will be handled separately */ 228 xa_for_each(&sr->xa, idx, entry) { 229 if (entry->reg.masked || entry->clr_bits == ~0) 230 ++count; 231 else if (entry->reg.mcr) 232 ++count_rmw_mcr; 233 else 234 ++count_rmw; 235 } 236 237 if (count) 238 bb_len += count * 2 + 1; 239 240 /* 241 * RMW of MCR registers is the same as a normal RMW, except an 242 * additional LRI (3 dwords) is required per register to steer the read 243 * to a nom-terminated instance. 244 * 245 * We could probably shorten the batch slightly by eliding the 246 * steering for consecutive MCR registers that have the same 247 * group/instance target, but it's not worth the extra complexity to do 248 * so. 249 */ 250 bb_len += count_rmw * EMIT_RMW_DW; 251 bb_len += count_rmw_mcr * (EMIT_RMW_DW + 3); 252 253 /* 254 * After doing all RMW, we need 7 trailing dwords to clean up, 255 * plus an additional 3 dwords to reset steering if any of the 256 * registers were MCR. 257 */ 258 if (count_rmw || count_rmw_mcr) 259 bb_len += 7 + (count_rmw_mcr ? 3 : 0); 260 261 if (hwe->class == XE_ENGINE_CLASS_RENDER) 262 /* 263 * Big enough to emit all of the context's 3DSTATE via 264 * xe_lrc_emit_hwe_state_instructions() 265 */ 266 bb_len += xe_gt_lrc_size(gt, hwe->class) / sizeof(u32); 267 268 xe_gt_dbg(gt, "LRC %s WA job: %zu dwords\n", hwe->name, bb_len); 269 270 bb = xe_bb_new(gt, bb_len, false); 271 if (IS_ERR(bb)) 272 return PTR_ERR(bb); 273 274 cs = bb->cs; 275 276 if (count) { 277 /* 278 * Emit single LRI with all non RMW regs: 1 leading dw + 2dw per 279 * reg + 1 280 */ 281 282 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); 283 284 xa_for_each(&sr->xa, idx, entry) { 285 struct xe_reg reg = entry->reg; 286 u32 val; 287 288 if (reg.masked) 289 val = entry->clr_bits << 16; 290 else if (entry->clr_bits == ~0) 291 val = 0; 292 else 293 continue; 294 295 val |= entry->set_bits; 296 297 *cs++ = reg.addr; 298 *cs++ = val; 299 xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val); 300 } 301 } 302 303 if (count_rmw || count_rmw_mcr) { 304 xa_for_each(&sr->xa, idx, entry) { 305 if (entry->reg.masked || entry->clr_bits == ~0) 306 continue; 307 308 if (entry->reg.mcr) { 309 struct xe_reg_mcr reg = { .__reg.raw = entry->reg.raw }; 310 u8 group, instance; 311 312 xe_gt_mcr_get_nonterminated_steering(gt, reg, &group, &instance); 313 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1); 314 *cs++ = CS_MMIO_GROUP_INSTANCE_SELECT(hwe->mmio_base).addr; 315 *cs++ = SELECTIVE_READ_ADDRESSING | 316 REG_FIELD_PREP(SELECTIVE_READ_GROUP, group) | 317 REG_FIELD_PREP(SELECTIVE_READ_INSTANCE, instance); 318 } 319 320 *cs++ = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO; 321 *cs++ = entry->reg.addr; 322 *cs++ = CS_GPR_REG(0, 0).addr; 323 324 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) | 325 MI_LRI_LRM_CS_MMIO; 326 *cs++ = CS_GPR_REG(0, 1).addr; 327 *cs++ = entry->clr_bits; 328 *cs++ = CS_GPR_REG(0, 2).addr; 329 *cs++ = entry->set_bits; 330 331 *cs++ = MI_MATH(8); 332 *cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0); 333 *cs++ = CS_ALU_INSTR_LOADINV(SRCB, REG1); 334 *cs++ = CS_ALU_INSTR_AND; 335 *cs++ = CS_ALU_INSTR_STORE(REG0, ACCU); 336 *cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0); 337 *cs++ = CS_ALU_INSTR_LOAD(SRCB, REG2); 338 *cs++ = CS_ALU_INSTR_OR; 339 *cs++ = CS_ALU_INSTR_STORE(REG0, ACCU); 340 341 *cs++ = MI_LOAD_REGISTER_REG | MI_LRR_SRC_CS_MMIO; 342 *cs++ = CS_GPR_REG(0, 0).addr; 343 *cs++ = entry->reg.addr; 344 345 xe_gt_dbg(gt, "REG[%#x] = ~%#x|%#x%s\n", 346 entry->reg.addr, entry->clr_bits, entry->set_bits, 347 entry->reg.mcr ? " (MCR)" : ""); 348 } 349 350 /* reset used GPR */ 351 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(3) | 352 MI_LRI_LRM_CS_MMIO; 353 *cs++ = CS_GPR_REG(0, 0).addr; 354 *cs++ = 0; 355 *cs++ = CS_GPR_REG(0, 1).addr; 356 *cs++ = 0; 357 *cs++ = CS_GPR_REG(0, 2).addr; 358 *cs++ = 0; 359 360 /* reset steering */ 361 if (count_rmw_mcr) { 362 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1); 363 *cs++ = CS_MMIO_GROUP_INSTANCE_SELECT(q->hwe->mmio_base).addr; 364 *cs++ = 0; 365 } 366 } 367 368 cs = xe_lrc_emit_hwe_state_instructions(q, cs); 369 370 bb->len = cs - bb->cs; 371 372 ret = emit_job_sync(q, bb, HZ); 373 374 xe_bb_free(bb, NULL); 375 376 return ret; 377 } 378 379 int xe_gt_record_default_lrcs(struct xe_gt *gt) 380 { 381 struct xe_device *xe = gt_to_xe(gt); 382 struct xe_hw_engine *hwe; 383 enum xe_hw_engine_id id; 384 int err = 0; 385 386 for_each_hw_engine(hwe, gt, id) { 387 struct xe_exec_queue *q, *nop_q; 388 void *default_lrc; 389 390 if (gt->default_lrc[hwe->class]) 391 continue; 392 393 xe_reg_sr_init(&hwe->reg_lrc, hwe->name, xe); 394 xe_wa_process_lrc(hwe); 395 xe_hw_engine_setup_default_lrc_state(hwe); 396 xe_tuning_process_lrc(hwe); 397 398 default_lrc = drmm_kzalloc(&xe->drm, 399 xe_gt_lrc_size(gt, hwe->class), 400 GFP_KERNEL); 401 if (!default_lrc) 402 return -ENOMEM; 403 404 q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 1, 405 hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 406 if (IS_ERR(q)) { 407 err = PTR_ERR(q); 408 xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n", 409 hwe->name, q); 410 return err; 411 } 412 413 /* Prime golden LRC with known good state */ 414 err = emit_wa_job(gt, q); 415 if (err) { 416 xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n", 417 hwe->name, ERR_PTR(err), q->guc->id); 418 goto put_exec_queue; 419 } 420 421 nop_q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 422 1, hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 423 if (IS_ERR(nop_q)) { 424 err = PTR_ERR(nop_q); 425 xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n", 426 hwe->name, nop_q); 427 goto put_exec_queue; 428 } 429 430 /* Switch to different LRC */ 431 err = emit_nop_job(gt, nop_q); 432 if (err) { 433 xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n", 434 hwe->name, ERR_PTR(err), nop_q->guc->id); 435 goto put_nop_q; 436 } 437 438 xe_map_memcpy_from(xe, default_lrc, 439 &q->lrc[0]->bo->vmap, 440 xe_lrc_pphwsp_offset(q->lrc[0]), 441 xe_gt_lrc_size(gt, hwe->class)); 442 443 gt->default_lrc[hwe->class] = default_lrc; 444 put_nop_q: 445 xe_exec_queue_put(nop_q); 446 put_exec_queue: 447 xe_exec_queue_put(q); 448 if (err) 449 break; 450 } 451 452 return err; 453 } 454 455 static void wa_14026539277(struct xe_gt *gt) 456 { 457 struct xe_device *xe = gt_to_xe(gt); 458 u32 val; 459 460 /* 461 * FIXME: We currently can't use FUNC(xe_rtp_match_not_sriov_vf) in the 462 * rules for Wa_14026539277 due to xe_wa_process_device_oob() being 463 * called before xe_sriov_probe_early(); and we can't move the call to 464 * the former to happen after the latter because MMIO read functions 465 * already depend on a device OOB workaround. This needs to be fixed by 466 * allowing workaround checks to happen at different stages of driver 467 * initialization. 468 */ 469 if (IS_SRIOV_VF(xe)) 470 return; 471 472 if (!XE_DEVICE_WA(xe, 14026539277)) 473 return; 474 475 if (!xe_gt_is_main_type(gt)) 476 return; 477 478 val = xe_gt_mcr_unicast_read_any(gt, L2COMPUTESIDECTRL); 479 val &= ~CECTRL; 480 val |= CECTRL_CENODATA_ALWAYS; 481 xe_gt_mcr_multicast_write(gt, L2COMPUTESIDECTRL, val); 482 } 483 484 int xe_gt_init_early(struct xe_gt *gt) 485 { 486 int err; 487 488 if (IS_SRIOV_PF(gt_to_xe(gt))) { 489 err = xe_gt_sriov_pf_init_early(gt); 490 if (err) 491 return err; 492 } 493 494 if (IS_SRIOV_VF(gt_to_xe(gt))) { 495 err = xe_gt_sriov_vf_init_early(gt); 496 if (err) 497 return err; 498 } 499 500 xe_reg_sr_init(>->reg_sr, "GT", gt_to_xe(gt)); 501 502 err = xe_wa_gt_init(gt); 503 if (err) 504 return err; 505 506 err = xe_tuning_init(gt); 507 if (err) 508 return err; 509 510 xe_wa_process_gt_oob(gt); 511 512 xe_force_wake_init_gt(gt, gt_to_fw(gt)); 513 spin_lock_init(>->global_invl_lock); 514 515 err = xe_gt_tlb_inval_init_early(gt); 516 if (err) 517 return err; 518 519 xe_mocs_init_early(gt); 520 521 /* 522 * Only after this point can GT-specific MMIO operations 523 * (including things like communication with the GuC) 524 * be performed. 525 */ 526 xe_gt_mmio_init(gt); 527 528 err = xe_uc_init_noalloc(>->uc); 529 if (err) 530 return err; 531 532 err = xe_gt_stats_init(gt); 533 if (err) 534 return err; 535 536 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 537 if (!fw_ref.domains) 538 return -ETIMEDOUT; 539 540 xe_gt_mcr_init_early(gt); 541 xe_pat_init(gt); 542 543 return 0; 544 } 545 546 static void dump_pat_on_error(struct xe_gt *gt) 547 { 548 struct drm_printer p; 549 char prefix[32]; 550 551 snprintf(prefix, sizeof(prefix), "[GT%u Error]", gt->info.id); 552 p = drm_dbg_printer(>_to_xe(gt)->drm, DRM_UT_DRIVER, prefix); 553 554 xe_pat_dump(gt, &p); 555 } 556 557 static int gt_init_with_gt_forcewake(struct xe_gt *gt) 558 { 559 int err; 560 561 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 562 if (!fw_ref.domains) 563 return -ETIMEDOUT; 564 565 err = xe_uc_init(>->uc); 566 if (err) 567 return err; 568 569 xe_gt_topology_init(gt); 570 xe_gt_mcr_init(gt); 571 xe_gt_enable_host_l2_vram(gt); 572 xe_gt_enable_comp_1wcoh(gt); 573 574 if (xe_gt_is_main_type(gt)) { 575 err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt); 576 if (err) 577 return err; 578 if (IS_SRIOV_PF(gt_to_xe(gt))) 579 xe_lmtt_init(>_to_tile(gt)->sriov.pf.lmtt); 580 } 581 582 /* Enable per hw engine IRQs */ 583 xe_irq_enable_hwe(gt); 584 585 /* Rerun MCR init as we now have hw engine list */ 586 xe_gt_mcr_init(gt); 587 588 err = xe_hw_engines_init_early(gt); 589 if (err) { 590 dump_pat_on_error(gt); 591 return err; 592 } 593 594 err = xe_hw_engine_class_sysfs_init(gt); 595 if (err) 596 return err; 597 598 /* Initialize CCS mode sysfs after early initialization of HW engines */ 599 err = xe_gt_ccs_mode_sysfs_init(gt); 600 if (err) 601 return err; 602 603 /* 604 * Stash hardware-reported version. Since this register does not exist 605 * on pre-MTL platforms, reading it there will (correctly) return 0. 606 */ 607 gt->info.gmdid = xe_mmio_read32(>->mmio, GMD_ID); 608 609 /* 610 * Wa_14026539277 can't be implemented as a regular GT workaround (i.e. 611 * as an entry in gt_was[]) for two reasons: it is actually a device 612 * workaround that happens to involve programming a GT register; and it 613 * needs to be applied early to avoid getting the hardware in a bad 614 * state before we have a chance to do the necessary programming. 615 */ 616 wa_14026539277(gt); 617 618 return 0; 619 } 620 621 static int gt_init_with_all_forcewake(struct xe_gt *gt) 622 { 623 int err; 624 625 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 626 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL)) 627 return -ETIMEDOUT; 628 629 xe_gt_mcr_set_implicit_defaults(gt); 630 xe_wa_process_gt(gt); 631 xe_tuning_process_gt(gt); 632 xe_reg_sr_apply_mmio(>->reg_sr, gt); 633 634 err = xe_gt_clock_init(gt); 635 if (err) 636 return err; 637 638 xe_mocs_init(gt); 639 err = xe_execlist_init(gt); 640 if (err) 641 return err; 642 643 err = xe_hw_engines_init(gt); 644 if (err) 645 return err; 646 647 err = xe_uc_init_post_hwconfig(>->uc); 648 if (err) 649 return err; 650 651 if (xe_gt_is_main_type(gt)) { 652 /* 653 * USM has its only SA pool to non-block behind user operations 654 */ 655 if (gt_to_xe(gt)->info.has_usm) { 656 struct xe_device *xe = gt_to_xe(gt); 657 658 gt->usm.bb_pool = xe_sa_bo_manager_init(gt_to_tile(gt), 659 IS_DGFX(xe) ? SZ_1M : SZ_512K, 16); 660 if (IS_ERR(gt->usm.bb_pool)) 661 return PTR_ERR(gt->usm.bb_pool); 662 } 663 } 664 665 if (xe_gt_is_main_type(gt)) { 666 struct xe_tile *tile = gt_to_tile(gt); 667 668 err = xe_migrate_init(tile->migrate); 669 if (err) 670 return err; 671 } 672 673 err = xe_uc_load_hw(>->uc); 674 if (err) 675 return err; 676 677 /* Configure default CCS mode of 1 engine with all resources */ 678 if (xe_gt_ccs_mode_enabled(gt)) { 679 gt->ccs_mode = 1; 680 xe_gt_apply_ccs_mode(gt); 681 } 682 683 if (IS_SRIOV_PF(gt_to_xe(gt)) && xe_gt_is_main_type(gt)) 684 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 685 686 if (IS_SRIOV_PF(gt_to_xe(gt))) 687 xe_gt_sriov_pf_init_hw(gt); 688 689 return 0; 690 } 691 692 static void xe_gt_fini(void *arg) 693 { 694 struct xe_gt *gt = arg; 695 int i; 696 697 if (disable_work_sync(>->reset.worker)) 698 /* 699 * If gt_reset_worker was halted from executing, take care of 700 * releasing the rpm reference here. 701 */ 702 xe_pm_runtime_put(gt_to_xe(gt)); 703 704 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 705 xe_hw_fence_irq_finish(>->fence_irq[i]); 706 707 xe_gt_disable_host_l2_vram(gt); 708 } 709 710 int xe_gt_init(struct xe_gt *gt) 711 { 712 int err; 713 int i; 714 715 INIT_WORK(>->reset.worker, gt_reset_worker); 716 717 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) { 718 gt->ring_ops[i] = xe_ring_ops_get(gt, i); 719 xe_hw_fence_irq_init(>->fence_irq[i]); 720 } 721 722 err = devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, xe_gt_fini, gt); 723 if (err) 724 return err; 725 726 err = xe_gt_sysfs_init(gt); 727 if (err) 728 return err; 729 730 err = gt_init_with_gt_forcewake(gt); 731 if (err) 732 return err; 733 734 err = xe_gt_idle_init(>->gtidle); 735 if (err) 736 return err; 737 738 err = xe_gt_freq_init(gt); 739 if (err) 740 return err; 741 742 xe_force_wake_init_engines(gt, gt_to_fw(gt)); 743 744 err = gt_init_with_all_forcewake(gt); 745 if (err) 746 return err; 747 748 xe_gt_record_user_engines(gt); 749 750 err = xe_eu_stall_init(gt); 751 if (err) 752 return err; 753 754 if (IS_SRIOV_VF(gt_to_xe(gt))) { 755 err = xe_gt_sriov_vf_init(gt); 756 if (err) 757 return err; 758 } 759 760 return 0; 761 } 762 763 /** 764 * xe_gt_mmio_init() - Initialize GT's MMIO access 765 * @gt: the GT object 766 * 767 * Initialize GT's MMIO accessor, which will be used to access registers inside 768 * this GT. 769 */ 770 void xe_gt_mmio_init(struct xe_gt *gt) 771 { 772 struct xe_tile *tile = gt_to_tile(gt); 773 struct xe_device *xe = tile_to_xe(tile); 774 775 xe_mmio_init(>->mmio, tile, tile->mmio.regs, tile->mmio.regs_size); 776 777 if (gt->info.type == XE_GT_TYPE_MEDIA) { 778 gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET; 779 gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH; 780 } else { 781 gt->mmio.adj_offset = 0; 782 gt->mmio.adj_limit = 0; 783 } 784 785 if (IS_SRIOV_VF(xe)) 786 gt->mmio.sriov_vf_gt = gt; 787 } 788 789 void xe_gt_record_user_engines(struct xe_gt *gt) 790 { 791 struct xe_hw_engine *hwe; 792 enum xe_hw_engine_id id; 793 794 gt->user_engines.mask = 0; 795 memset(gt->user_engines.instances_per_class, 0, 796 sizeof(gt->user_engines.instances_per_class)); 797 798 for_each_hw_engine(hwe, gt, id) { 799 if (xe_hw_engine_is_reserved(hwe)) 800 continue; 801 802 gt->user_engines.mask |= BIT_ULL(id); 803 gt->user_engines.instances_per_class[hwe->class]++; 804 } 805 806 xe_gt_assert(gt, (gt->user_engines.mask | gt->info.engine_mask) 807 == gt->info.engine_mask); 808 } 809 810 static int do_gt_reset(struct xe_gt *gt) 811 { 812 int err; 813 814 if (IS_SRIOV_VF(gt_to_xe(gt))) 815 return xe_gt_sriov_vf_reset(gt); 816 817 xe_gsc_wa_14015076503(gt, true); 818 819 xe_mmio_write32(>->mmio, GDRST, GRDOM_FULL); 820 err = xe_mmio_wait32(>->mmio, GDRST, GRDOM_FULL, 0, 5000, NULL, false); 821 if (err) 822 xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n", 823 ERR_PTR(err)); 824 825 xe_gsc_wa_14015076503(gt, false); 826 827 return err; 828 } 829 830 static int vf_gt_restart(struct xe_gt *gt) 831 { 832 int err; 833 834 err = xe_uc_sanitize_reset(>->uc); 835 if (err) 836 return err; 837 838 err = xe_uc_load_hw(>->uc); 839 if (err) 840 return err; 841 842 err = xe_uc_start(>->uc); 843 if (err) 844 return err; 845 846 return 0; 847 } 848 849 static int do_gt_restart(struct xe_gt *gt) 850 { 851 struct xe_hw_engine *hwe; 852 enum xe_hw_engine_id id; 853 int err; 854 855 if (IS_SRIOV_VF(gt_to_xe(gt))) 856 return vf_gt_restart(gt); 857 858 xe_pat_init(gt); 859 860 xe_gt_enable_host_l2_vram(gt); 861 xe_gt_enable_comp_1wcoh(gt); 862 863 xe_gt_mcr_set_implicit_defaults(gt); 864 xe_reg_sr_apply_mmio(>->reg_sr, gt); 865 866 err = xe_wopcm_init(>->uc.wopcm); 867 if (err) 868 return err; 869 870 for_each_hw_engine(hwe, gt, id) 871 xe_hw_engine_enable_ring(hwe); 872 873 err = xe_uc_sanitize_reset(>->uc); 874 if (err) 875 return err; 876 877 err = xe_uc_load_hw(>->uc); 878 if (err) 879 return err; 880 881 if (IS_SRIOV_PF(gt_to_xe(gt)) && xe_gt_is_main_type(gt)) 882 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 883 884 if (IS_SRIOV_PF(gt_to_xe(gt))) 885 xe_gt_sriov_pf_init_hw(gt); 886 887 xe_mocs_init(gt); 888 889 for_each_hw_engine(hwe, gt, id) 890 xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); 891 892 /* Get CCS mode in sync between sw/hw */ 893 xe_gt_apply_ccs_mode(gt); 894 895 err = xe_uc_start(>->uc); 896 if (err) 897 return err; 898 899 /* Restore GT freq to expected values */ 900 xe_gt_sanitize_freq(gt); 901 902 if (IS_SRIOV_PF(gt_to_xe(gt))) 903 xe_gt_sriov_pf_restart(gt); 904 905 return 0; 906 } 907 908 static void gt_reset_worker(struct work_struct *w) 909 { 910 struct xe_gt *gt = container_of(w, typeof(*gt), reset.worker); 911 unsigned int fw_ref; 912 int err; 913 914 if (xe_device_wedged(gt_to_xe(gt))) 915 goto err_pm_put; 916 917 /* We only support GT resets with GuC submission */ 918 if (!xe_device_uc_enabled(gt_to_xe(gt))) 919 goto err_pm_put; 920 921 xe_gt_info(gt, "reset started\n"); 922 923 if (xe_fault_inject_gt_reset()) { 924 err = -ECANCELED; 925 goto err_fail; 926 } 927 928 xe_gt_sanitize(gt); 929 930 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 931 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 932 err = -ETIMEDOUT; 933 goto err_out; 934 } 935 936 if (IS_SRIOV_PF(gt_to_xe(gt))) 937 xe_gt_sriov_pf_stop_prepare(gt); 938 939 xe_guc_rc_disable(>->uc.guc); 940 xe_uc_stop_prepare(>->uc); 941 xe_pagefault_reset(gt_to_xe(gt), gt); 942 943 xe_uc_stop(>->uc); 944 945 xe_tlb_inval_reset(>->tlb_inval); 946 947 err = do_gt_reset(gt); 948 if (err) 949 goto err_out; 950 951 err = do_gt_restart(gt); 952 if (err) 953 goto err_out; 954 955 xe_force_wake_put(gt_to_fw(gt), fw_ref); 956 957 /* Pair with get while enqueueing the work in xe_gt_reset_async() */ 958 xe_pm_runtime_put(gt_to_xe(gt)); 959 960 xe_gt_info(gt, "reset done\n"); 961 962 return; 963 964 err_out: 965 xe_force_wake_put(gt_to_fw(gt), fw_ref); 966 XE_WARN_ON(xe_uc_start(>->uc)); 967 968 err_fail: 969 xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err)); 970 xe_device_declare_wedged(gt_to_xe(gt)); 971 err_pm_put: 972 xe_pm_runtime_put(gt_to_xe(gt)); 973 } 974 975 void xe_gt_reset_async(struct xe_gt *gt) 976 { 977 xe_gt_info(gt, "trying reset from %ps\n", __builtin_return_address(0)); 978 979 /* Don't do a reset while one is already in flight */ 980 if (!xe_fault_inject_gt_reset() && xe_uc_reset_prepare(>->uc)) 981 return; 982 983 xe_gt_info(gt, "reset queued\n"); 984 985 /* Pair with put in gt_reset_worker() if work is enqueued */ 986 xe_pm_runtime_get_noresume(gt_to_xe(gt)); 987 if (!queue_work(gt->ordered_wq, >->reset.worker)) 988 xe_pm_runtime_put(gt_to_xe(gt)); 989 } 990 991 void xe_gt_suspend_prepare(struct xe_gt *gt) 992 { 993 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 994 xe_uc_suspend_prepare(>->uc); 995 } 996 997 int xe_gt_suspend(struct xe_gt *gt) 998 { 999 int err; 1000 1001 xe_gt_dbg(gt, "suspending\n"); 1002 xe_gt_sanitize(gt); 1003 1004 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 1005 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL)) { 1006 xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(-ETIMEDOUT)); 1007 return -ETIMEDOUT; 1008 } 1009 1010 err = xe_uc_suspend(>->uc); 1011 if (err) { 1012 xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(err)); 1013 return err; 1014 } 1015 1016 xe_gt_idle_disable_pg(gt); 1017 1018 xe_gt_disable_host_l2_vram(gt); 1019 1020 xe_gt_dbg(gt, "suspended\n"); 1021 1022 return 0; 1023 } 1024 1025 void xe_gt_shutdown(struct xe_gt *gt) 1026 { 1027 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 1028 do_gt_reset(gt); 1029 } 1030 1031 /** 1032 * xe_gt_sanitize_freq() - Restore saved frequencies if necessary. 1033 * @gt: the GT object 1034 * 1035 * Called after driver init/GSC load completes to restore GT frequencies if we 1036 * limited them for any WAs. 1037 */ 1038 int xe_gt_sanitize_freq(struct xe_gt *gt) 1039 { 1040 int ret = 0; 1041 1042 if ((!xe_uc_fw_is_available(>->uc.gsc.fw) || 1043 xe_uc_fw_is_loaded(>->uc.gsc.fw) || 1044 xe_uc_fw_is_in_error_state(>->uc.gsc.fw)) && 1045 XE_GT_WA(gt, 22019338487)) 1046 ret = xe_guc_pc_restore_stashed_freq(>->uc.guc.pc); 1047 1048 return ret; 1049 } 1050 1051 int xe_gt_resume(struct xe_gt *gt) 1052 { 1053 int err; 1054 1055 xe_gt_dbg(gt, "resuming\n"); 1056 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 1057 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL)) { 1058 xe_gt_err(gt, "resume failed (%pe)\n", ERR_PTR(-ETIMEDOUT)); 1059 return -ETIMEDOUT; 1060 } 1061 1062 err = do_gt_restart(gt); 1063 if (err) 1064 return err; 1065 1066 xe_gt_idle_enable_pg(gt); 1067 1068 xe_gt_dbg(gt, "resumed\n"); 1069 1070 return 0; 1071 } 1072 1073 /** 1074 * xe_gt_runtime_suspend() - GT runtime suspend 1075 * @gt: the GT object 1076 * 1077 * Return: 0 on success, negative error code otherwise. 1078 */ 1079 int xe_gt_runtime_suspend(struct xe_gt *gt) 1080 { 1081 xe_gt_dbg(gt, "runtime suspending\n"); 1082 1083 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 1084 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL)) { 1085 xe_gt_err(gt, "runtime suspend failed (%pe)\n", ERR_PTR(-ETIMEDOUT)); 1086 return -ETIMEDOUT; 1087 } 1088 1089 xe_uc_runtime_suspend(>->uc); 1090 xe_gt_disable_host_l2_vram(gt); 1091 1092 xe_gt_dbg(gt, "runtime suspended\n"); 1093 1094 return 0; 1095 } 1096 1097 /** 1098 * xe_gt_runtime_resume() - GT runtime resume 1099 * @gt: the GT object 1100 * 1101 * Return: 0 on success, negative error code otherwise. 1102 */ 1103 int xe_gt_runtime_resume(struct xe_gt *gt) 1104 { 1105 xe_gt_dbg(gt, "runtime resuming\n"); 1106 1107 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 1108 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL)) { 1109 xe_gt_err(gt, "runtime resume failed (%pe)\n", ERR_PTR(-ETIMEDOUT)); 1110 return -ETIMEDOUT; 1111 } 1112 1113 xe_gt_enable_host_l2_vram(gt); 1114 xe_uc_runtime_resume(>->uc); 1115 1116 xe_gt_dbg(gt, "runtime resumed\n"); 1117 1118 return 0; 1119 } 1120 1121 struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt, 1122 enum xe_engine_class class, 1123 u16 instance, bool logical) 1124 { 1125 struct xe_hw_engine *hwe; 1126 enum xe_hw_engine_id id; 1127 1128 for_each_hw_engine(hwe, gt, id) 1129 if (hwe->class == class && 1130 ((!logical && hwe->instance == instance) || 1131 (logical && hwe->logical_instance == instance))) 1132 return hwe; 1133 1134 return NULL; 1135 } 1136 1137 struct xe_hw_engine *xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt, 1138 enum xe_engine_class class) 1139 { 1140 struct xe_hw_engine *hwe; 1141 enum xe_hw_engine_id id; 1142 1143 for_each_hw_engine(hwe, gt, id) { 1144 switch (class) { 1145 case XE_ENGINE_CLASS_RENDER: 1146 case XE_ENGINE_CLASS_COMPUTE: 1147 if (hwe->class == XE_ENGINE_CLASS_RENDER || 1148 hwe->class == XE_ENGINE_CLASS_COMPUTE) 1149 return hwe; 1150 break; 1151 default: 1152 if (hwe->class == class) 1153 return hwe; 1154 } 1155 } 1156 1157 return NULL; 1158 } 1159 1160 struct xe_hw_engine *xe_gt_any_hw_engine(struct xe_gt *gt) 1161 { 1162 struct xe_hw_engine *hwe; 1163 enum xe_hw_engine_id id; 1164 1165 for_each_hw_engine(hwe, gt, id) 1166 return hwe; 1167 1168 return NULL; 1169 } 1170 1171 /** 1172 * xe_gt_declare_wedged() - Declare GT wedged 1173 * @gt: the GT object 1174 * 1175 * Wedge the GT which stops all submission, saves desired debug state, and 1176 * cleans up anything which could timeout. 1177 */ 1178 void xe_gt_declare_wedged(struct xe_gt *gt) 1179 { 1180 xe_gt_assert(gt, gt_to_xe(gt)->wedged.mode); 1181 1182 xe_uc_declare_wedged(>->uc); 1183 xe_tlb_inval_reset(>->tlb_inval); 1184 } 1185