1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_gt.h" 7 8 #include <linux/minmax.h> 9 10 #include <drm/drm_managed.h> 11 #include <drm/xe_drm.h> 12 #include <generated/xe_wa_oob.h> 13 14 #include "instructions/xe_gfxpipe_commands.h" 15 #include "instructions/xe_mi_commands.h" 16 #include "regs/xe_gt_regs.h" 17 #include "xe_assert.h" 18 #include "xe_bb.h" 19 #include "xe_bo.h" 20 #include "xe_device.h" 21 #include "xe_exec_queue.h" 22 #include "xe_execlist.h" 23 #include "xe_force_wake.h" 24 #include "xe_ggtt.h" 25 #include "xe_gsc.h" 26 #include "xe_gt_ccs_mode.h" 27 #include "xe_gt_clock.h" 28 #include "xe_gt_freq.h" 29 #include "xe_gt_idle.h" 30 #include "xe_gt_mcr.h" 31 #include "xe_gt_pagefault.h" 32 #include "xe_gt_printk.h" 33 #include "xe_gt_sriov_pf.h" 34 #include "xe_gt_sysfs.h" 35 #include "xe_gt_tlb_invalidation.h" 36 #include "xe_gt_topology.h" 37 #include "xe_guc_exec_queue_types.h" 38 #include "xe_guc_pc.h" 39 #include "xe_hw_fence.h" 40 #include "xe_hw_engine_class_sysfs.h" 41 #include "xe_irq.h" 42 #include "xe_lmtt.h" 43 #include "xe_lrc.h" 44 #include "xe_map.h" 45 #include "xe_migrate.h" 46 #include "xe_mmio.h" 47 #include "xe_pat.h" 48 #include "xe_pcode.h" 49 #include "xe_pm.h" 50 #include "xe_mocs.h" 51 #include "xe_reg_sr.h" 52 #include "xe_ring_ops.h" 53 #include "xe_sa.h" 54 #include "xe_sched_job.h" 55 #include "xe_sriov.h" 56 #include "xe_tuning.h" 57 #include "xe_uc.h" 58 #include "xe_uc_fw.h" 59 #include "xe_vm.h" 60 #include "xe_wa.h" 61 #include "xe_wopcm.h" 62 63 static void gt_fini(struct drm_device *drm, void *arg) 64 { 65 struct xe_gt *gt = arg; 66 67 destroy_workqueue(gt->ordered_wq); 68 } 69 70 struct xe_gt *xe_gt_alloc(struct xe_tile *tile) 71 { 72 struct xe_gt *gt; 73 int err; 74 75 gt = drmm_kzalloc(&tile_to_xe(tile)->drm, sizeof(*gt), GFP_KERNEL); 76 if (!gt) 77 return ERR_PTR(-ENOMEM); 78 79 gt->tile = tile; 80 gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", 0); 81 82 err = drmm_add_action_or_reset(>_to_xe(gt)->drm, gt_fini, gt); 83 if (err) 84 return ERR_PTR(err); 85 86 return gt; 87 } 88 89 void xe_gt_sanitize(struct xe_gt *gt) 90 { 91 /* 92 * FIXME: if xe_uc_sanitize is called here, on TGL driver will not 93 * reload 94 */ 95 gt->uc.guc.submission_state.enabled = false; 96 } 97 98 /** 99 * xe_gt_remove() - Clean up the GT structures before driver removal 100 * @gt: the GT object 101 * 102 * This function should only act on objects/structures that must be cleaned 103 * before the driver removal callback is complete and therefore can't be 104 * deferred to a drmm action. 105 */ 106 void xe_gt_remove(struct xe_gt *gt) 107 { 108 int i; 109 110 xe_uc_remove(>->uc); 111 112 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 113 xe_hw_fence_irq_finish(>->fence_irq[i]); 114 } 115 116 static void gt_reset_worker(struct work_struct *w); 117 118 static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q) 119 { 120 struct xe_sched_job *job; 121 struct xe_bb *bb; 122 struct dma_fence *fence; 123 long timeout; 124 125 bb = xe_bb_new(gt, 4, false); 126 if (IS_ERR(bb)) 127 return PTR_ERR(bb); 128 129 job = xe_bb_create_job(q, bb); 130 if (IS_ERR(job)) { 131 xe_bb_free(bb, NULL); 132 return PTR_ERR(job); 133 } 134 135 xe_sched_job_arm(job); 136 fence = dma_fence_get(&job->drm.s_fence->finished); 137 xe_sched_job_push(job); 138 139 timeout = dma_fence_wait_timeout(fence, false, HZ); 140 dma_fence_put(fence); 141 xe_bb_free(bb, NULL); 142 if (timeout < 0) 143 return timeout; 144 else if (!timeout) 145 return -ETIME; 146 147 return 0; 148 } 149 150 /* 151 * Convert back from encoded value to type-safe, only to be used when reg.mcr 152 * is true 153 */ 154 static struct xe_reg_mcr to_xe_reg_mcr(const struct xe_reg reg) 155 { 156 return (const struct xe_reg_mcr){.__reg.raw = reg.raw }; 157 } 158 159 static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) 160 { 161 struct xe_reg_sr *sr = &q->hwe->reg_lrc; 162 struct xe_reg_sr_entry *entry; 163 unsigned long idx; 164 struct xe_sched_job *job; 165 struct xe_bb *bb; 166 struct dma_fence *fence; 167 long timeout; 168 int count = 0; 169 170 if (q->hwe->class == XE_ENGINE_CLASS_RENDER) 171 /* Big enough to emit all of the context's 3DSTATE */ 172 bb = xe_bb_new(gt, xe_gt_lrc_size(gt, q->hwe->class), false); 173 else 174 /* Just pick a large BB size */ 175 bb = xe_bb_new(gt, SZ_4K, false); 176 177 if (IS_ERR(bb)) 178 return PTR_ERR(bb); 179 180 xa_for_each(&sr->xa, idx, entry) 181 ++count; 182 183 if (count) { 184 xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name); 185 186 bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); 187 188 xa_for_each(&sr->xa, idx, entry) { 189 struct xe_reg reg = entry->reg; 190 struct xe_reg_mcr reg_mcr = to_xe_reg_mcr(reg); 191 u32 val; 192 193 /* 194 * Skip reading the register if it's not really needed 195 */ 196 if (reg.masked) 197 val = entry->clr_bits << 16; 198 else if (entry->clr_bits + 1) 199 val = (reg.mcr ? 200 xe_gt_mcr_unicast_read_any(gt, reg_mcr) : 201 xe_mmio_read32(gt, reg)) & (~entry->clr_bits); 202 else 203 val = 0; 204 205 val |= entry->set_bits; 206 207 bb->cs[bb->len++] = reg.addr; 208 bb->cs[bb->len++] = val; 209 xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val); 210 } 211 } 212 213 xe_lrc_emit_hwe_state_instructions(q, bb); 214 215 job = xe_bb_create_job(q, bb); 216 if (IS_ERR(job)) { 217 xe_bb_free(bb, NULL); 218 return PTR_ERR(job); 219 } 220 221 xe_sched_job_arm(job); 222 fence = dma_fence_get(&job->drm.s_fence->finished); 223 xe_sched_job_push(job); 224 225 timeout = dma_fence_wait_timeout(fence, false, HZ); 226 dma_fence_put(fence); 227 xe_bb_free(bb, NULL); 228 if (timeout < 0) 229 return timeout; 230 else if (!timeout) 231 return -ETIME; 232 233 return 0; 234 } 235 236 int xe_gt_record_default_lrcs(struct xe_gt *gt) 237 { 238 struct xe_device *xe = gt_to_xe(gt); 239 struct xe_hw_engine *hwe; 240 enum xe_hw_engine_id id; 241 int err = 0; 242 243 for_each_hw_engine(hwe, gt, id) { 244 struct xe_exec_queue *q, *nop_q; 245 void *default_lrc; 246 247 if (gt->default_lrc[hwe->class]) 248 continue; 249 250 xe_reg_sr_init(&hwe->reg_lrc, hwe->name, xe); 251 xe_wa_process_lrc(hwe); 252 xe_hw_engine_setup_default_lrc_state(hwe); 253 xe_tuning_process_lrc(hwe); 254 255 default_lrc = drmm_kzalloc(&xe->drm, 256 xe_gt_lrc_size(gt, hwe->class), 257 GFP_KERNEL); 258 if (!default_lrc) 259 return -ENOMEM; 260 261 q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 1, 262 hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 263 if (IS_ERR(q)) { 264 err = PTR_ERR(q); 265 xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n", 266 hwe->name, q); 267 return err; 268 } 269 270 /* Prime golden LRC with known good state */ 271 err = emit_wa_job(gt, q); 272 if (err) { 273 xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n", 274 hwe->name, ERR_PTR(err), q->guc->id); 275 goto put_exec_queue; 276 } 277 278 nop_q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 279 1, hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 280 if (IS_ERR(nop_q)) { 281 err = PTR_ERR(nop_q); 282 xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n", 283 hwe->name, nop_q); 284 goto put_exec_queue; 285 } 286 287 /* Switch to different LRC */ 288 err = emit_nop_job(gt, nop_q); 289 if (err) { 290 xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n", 291 hwe->name, ERR_PTR(err), nop_q->guc->id); 292 goto put_nop_q; 293 } 294 295 /* Reload golden LRC to record the effect of any indirect W/A */ 296 err = emit_nop_job(gt, q); 297 if (err) { 298 xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n", 299 hwe->name, ERR_PTR(err), q->guc->id); 300 goto put_nop_q; 301 } 302 303 xe_map_memcpy_from(xe, default_lrc, 304 &q->lrc[0]->bo->vmap, 305 xe_lrc_pphwsp_offset(q->lrc[0]), 306 xe_gt_lrc_size(gt, hwe->class)); 307 308 gt->default_lrc[hwe->class] = default_lrc; 309 put_nop_q: 310 xe_exec_queue_put(nop_q); 311 put_exec_queue: 312 xe_exec_queue_put(q); 313 if (err) 314 break; 315 } 316 317 return err; 318 } 319 320 int xe_gt_init_early(struct xe_gt *gt) 321 { 322 int err; 323 324 if (IS_SRIOV_PF(gt_to_xe(gt))) { 325 err = xe_gt_sriov_pf_init_early(gt); 326 if (err) 327 return err; 328 } 329 330 xe_reg_sr_init(>->reg_sr, "GT", gt_to_xe(gt)); 331 332 err = xe_wa_init(gt); 333 if (err) 334 return err; 335 336 xe_wa_process_gt(gt); 337 xe_wa_process_oob(gt); 338 xe_tuning_process_gt(gt); 339 340 xe_force_wake_init_gt(gt, gt_to_fw(gt)); 341 xe_pcode_init(gt); 342 343 return 0; 344 } 345 346 static void dump_pat_on_error(struct xe_gt *gt) 347 { 348 struct drm_printer p; 349 char prefix[32]; 350 351 snprintf(prefix, sizeof(prefix), "[GT%u Error]", gt->info.id); 352 p = drm_dbg_printer(>_to_xe(gt)->drm, DRM_UT_DRIVER, prefix); 353 354 xe_pat_dump(gt, &p); 355 } 356 357 static int gt_fw_domain_init(struct xe_gt *gt) 358 { 359 int err, i; 360 361 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 362 if (err) 363 goto err_hw_fence_irq; 364 365 if (!xe_gt_is_media_type(gt)) { 366 err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt); 367 if (err) 368 goto err_force_wake; 369 if (IS_SRIOV_PF(gt_to_xe(gt))) 370 xe_lmtt_init(>_to_tile(gt)->sriov.pf.lmtt); 371 } 372 373 /* Enable per hw engine IRQs */ 374 xe_irq_enable_hwe(gt); 375 376 /* Rerun MCR init as we now have hw engine list */ 377 xe_gt_mcr_init(gt); 378 379 err = xe_hw_engines_init_early(gt); 380 if (err) 381 goto err_force_wake; 382 383 err = xe_hw_engine_class_sysfs_init(gt); 384 if (err) 385 goto err_force_wake; 386 387 /* Initialize CCS mode sysfs after early initialization of HW engines */ 388 err = xe_gt_ccs_mode_sysfs_init(gt); 389 if (err) 390 goto err_force_wake; 391 392 /* 393 * Stash hardware-reported version. Since this register does not exist 394 * on pre-MTL platforms, reading it there will (correctly) return 0. 395 */ 396 gt->info.gmdid = xe_mmio_read32(gt, GMD_ID); 397 398 err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 399 XE_WARN_ON(err); 400 401 return 0; 402 403 err_force_wake: 404 dump_pat_on_error(gt); 405 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 406 err_hw_fence_irq: 407 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 408 xe_hw_fence_irq_finish(>->fence_irq[i]); 409 410 return err; 411 } 412 413 static int all_fw_domain_init(struct xe_gt *gt) 414 { 415 int err, i; 416 417 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 418 if (err) 419 goto err_hw_fence_irq; 420 421 xe_gt_mcr_set_implicit_defaults(gt); 422 xe_reg_sr_apply_mmio(>->reg_sr, gt); 423 424 err = xe_gt_clock_init(gt); 425 if (err) 426 goto err_force_wake; 427 428 xe_mocs_init(gt); 429 err = xe_execlist_init(gt); 430 if (err) 431 goto err_force_wake; 432 433 err = xe_hw_engines_init(gt); 434 if (err) 435 goto err_force_wake; 436 437 err = xe_uc_init_post_hwconfig(>->uc); 438 if (err) 439 goto err_force_wake; 440 441 if (!xe_gt_is_media_type(gt)) { 442 /* 443 * USM has its only SA pool to non-block behind user operations 444 */ 445 if (gt_to_xe(gt)->info.has_usm) { 446 struct xe_device *xe = gt_to_xe(gt); 447 448 gt->usm.bb_pool = xe_sa_bo_manager_init(gt_to_tile(gt), 449 IS_DGFX(xe) ? SZ_1M : SZ_512K, 16); 450 if (IS_ERR(gt->usm.bb_pool)) { 451 err = PTR_ERR(gt->usm.bb_pool); 452 goto err_force_wake; 453 } 454 } 455 } 456 457 if (!xe_gt_is_media_type(gt)) { 458 struct xe_tile *tile = gt_to_tile(gt); 459 460 tile->migrate = xe_migrate_init(tile); 461 if (IS_ERR(tile->migrate)) { 462 err = PTR_ERR(tile->migrate); 463 goto err_force_wake; 464 } 465 } 466 467 err = xe_uc_init_hw(>->uc); 468 if (err) 469 goto err_force_wake; 470 471 /* Configure default CCS mode of 1 engine with all resources */ 472 if (xe_gt_ccs_mode_enabled(gt)) { 473 gt->ccs_mode = 1; 474 xe_gt_apply_ccs_mode(gt); 475 } 476 477 if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt)) 478 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 479 480 if (IS_SRIOV_PF(gt_to_xe(gt))) 481 xe_gt_sriov_pf_init_hw(gt); 482 483 err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 484 XE_WARN_ON(err); 485 486 return 0; 487 488 err_force_wake: 489 xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 490 err_hw_fence_irq: 491 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 492 xe_hw_fence_irq_finish(>->fence_irq[i]); 493 494 return err; 495 } 496 497 /* 498 * Initialize enough GT to be able to load GuC in order to obtain hwconfig and 499 * enable CTB communication. 500 */ 501 int xe_gt_init_hwconfig(struct xe_gt *gt) 502 { 503 int err; 504 505 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 506 if (err) 507 goto out; 508 509 xe_gt_mcr_init_early(gt); 510 xe_pat_init(gt); 511 512 err = xe_uc_init(>->uc); 513 if (err) 514 goto out_fw; 515 516 err = xe_uc_init_hwconfig(>->uc); 517 if (err) 518 goto out_fw; 519 520 xe_gt_topology_init(gt); 521 xe_gt_mcr_init(gt); 522 523 out_fw: 524 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 525 out: 526 return err; 527 } 528 529 int xe_gt_init(struct xe_gt *gt) 530 { 531 int err; 532 int i; 533 534 INIT_WORK(>->reset.worker, gt_reset_worker); 535 536 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) { 537 gt->ring_ops[i] = xe_ring_ops_get(gt, i); 538 xe_hw_fence_irq_init(>->fence_irq[i]); 539 } 540 541 err = xe_gt_tlb_invalidation_init(gt); 542 if (err) 543 return err; 544 545 err = xe_gt_pagefault_init(gt); 546 if (err) 547 return err; 548 549 xe_mocs_init_early(gt); 550 551 err = xe_gt_sysfs_init(gt); 552 if (err) 553 return err; 554 555 err = gt_fw_domain_init(gt); 556 if (err) 557 return err; 558 559 err = xe_gt_idle_init(>->gtidle); 560 if (err) 561 return err; 562 563 err = xe_gt_freq_init(gt); 564 if (err) 565 return err; 566 567 xe_force_wake_init_engines(gt, gt_to_fw(gt)); 568 569 err = all_fw_domain_init(gt); 570 if (err) 571 return err; 572 573 xe_gt_record_user_engines(gt); 574 575 return 0; 576 } 577 578 void xe_gt_record_user_engines(struct xe_gt *gt) 579 { 580 struct xe_hw_engine *hwe; 581 enum xe_hw_engine_id id; 582 583 gt->user_engines.mask = 0; 584 memset(gt->user_engines.instances_per_class, 0, 585 sizeof(gt->user_engines.instances_per_class)); 586 587 for_each_hw_engine(hwe, gt, id) { 588 if (xe_hw_engine_is_reserved(hwe)) 589 continue; 590 591 gt->user_engines.mask |= BIT_ULL(id); 592 gt->user_engines.instances_per_class[hwe->class]++; 593 } 594 595 xe_gt_assert(gt, (gt->user_engines.mask | gt->info.engine_mask) 596 == gt->info.engine_mask); 597 } 598 599 static int do_gt_reset(struct xe_gt *gt) 600 { 601 int err; 602 603 xe_gsc_wa_14015076503(gt, true); 604 605 xe_mmio_write32(gt, GDRST, GRDOM_FULL); 606 err = xe_mmio_wait32(gt, GDRST, GRDOM_FULL, 0, 5000, NULL, false); 607 if (err) 608 xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n", 609 ERR_PTR(err)); 610 611 xe_gsc_wa_14015076503(gt, false); 612 613 return err; 614 } 615 616 static int vf_gt_restart(struct xe_gt *gt) 617 { 618 int err; 619 620 err = xe_uc_sanitize_reset(>->uc); 621 if (err) 622 return err; 623 624 err = xe_uc_init_hw(>->uc); 625 if (err) 626 return err; 627 628 err = xe_uc_start(>->uc); 629 if (err) 630 return err; 631 632 return 0; 633 } 634 635 static int do_gt_restart(struct xe_gt *gt) 636 { 637 struct xe_hw_engine *hwe; 638 enum xe_hw_engine_id id; 639 int err; 640 641 if (IS_SRIOV_VF(gt_to_xe(gt))) 642 return vf_gt_restart(gt); 643 644 xe_pat_init(gt); 645 646 xe_gt_mcr_set_implicit_defaults(gt); 647 xe_reg_sr_apply_mmio(>->reg_sr, gt); 648 649 err = xe_wopcm_init(>->uc.wopcm); 650 if (err) 651 return err; 652 653 for_each_hw_engine(hwe, gt, id) 654 xe_hw_engine_enable_ring(hwe); 655 656 err = xe_uc_sanitize_reset(>->uc); 657 if (err) 658 return err; 659 660 err = xe_uc_init_hw(>->uc); 661 if (err) 662 return err; 663 664 if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt)) 665 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 666 667 if (IS_SRIOV_PF(gt_to_xe(gt))) 668 xe_gt_sriov_pf_init_hw(gt); 669 670 xe_mocs_init(gt); 671 err = xe_uc_start(>->uc); 672 if (err) 673 return err; 674 675 for_each_hw_engine(hwe, gt, id) { 676 xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); 677 xe_reg_sr_apply_whitelist(hwe); 678 } 679 680 /* Get CCS mode in sync between sw/hw */ 681 xe_gt_apply_ccs_mode(gt); 682 683 /* Restore GT freq to expected values */ 684 xe_gt_sanitize_freq(gt); 685 686 if (IS_SRIOV_PF(gt_to_xe(gt))) 687 xe_gt_sriov_pf_restart(gt); 688 689 return 0; 690 } 691 692 static int gt_reset(struct xe_gt *gt) 693 { 694 int err; 695 696 if (xe_device_wedged(gt_to_xe(gt))) 697 return -ECANCELED; 698 699 /* We only support GT resets with GuC submission */ 700 if (!xe_device_uc_enabled(gt_to_xe(gt))) 701 return -ENODEV; 702 703 xe_gt_info(gt, "reset started\n"); 704 705 if (xe_fault_inject_gt_reset()) { 706 err = -ECANCELED; 707 goto err_fail; 708 } 709 710 xe_pm_runtime_get(gt_to_xe(gt)); 711 xe_gt_sanitize(gt); 712 713 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 714 if (err) 715 goto err_msg; 716 717 xe_uc_gucrc_disable(>->uc); 718 xe_uc_stop_prepare(>->uc); 719 xe_gt_pagefault_reset(gt); 720 721 xe_uc_stop(>->uc); 722 723 xe_gt_tlb_invalidation_reset(gt); 724 725 err = do_gt_reset(gt); 726 if (err) 727 goto err_out; 728 729 err = do_gt_restart(gt); 730 if (err) 731 goto err_out; 732 733 err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 734 XE_WARN_ON(err); 735 xe_pm_runtime_put(gt_to_xe(gt)); 736 737 xe_gt_info(gt, "reset done\n"); 738 739 return 0; 740 741 err_out: 742 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 743 err_msg: 744 XE_WARN_ON(xe_uc_start(>->uc)); 745 xe_pm_runtime_put(gt_to_xe(gt)); 746 err_fail: 747 xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err)); 748 749 xe_device_declare_wedged(gt_to_xe(gt)); 750 751 return err; 752 } 753 754 static void gt_reset_worker(struct work_struct *w) 755 { 756 struct xe_gt *gt = container_of(w, typeof(*gt), reset.worker); 757 758 gt_reset(gt); 759 } 760 761 void xe_gt_reset_async(struct xe_gt *gt) 762 { 763 xe_gt_info(gt, "trying reset\n"); 764 765 /* Don't do a reset while one is already in flight */ 766 if (!xe_fault_inject_gt_reset() && xe_uc_reset_prepare(>->uc)) 767 return; 768 769 xe_gt_info(gt, "reset queued\n"); 770 queue_work(gt->ordered_wq, >->reset.worker); 771 } 772 773 void xe_gt_suspend_prepare(struct xe_gt *gt) 774 { 775 XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 776 777 xe_uc_stop_prepare(>->uc); 778 779 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 780 } 781 782 int xe_gt_suspend(struct xe_gt *gt) 783 { 784 int err; 785 786 xe_gt_dbg(gt, "suspending\n"); 787 xe_gt_sanitize(gt); 788 789 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 790 if (err) 791 goto err_msg; 792 793 err = xe_uc_suspend(>->uc); 794 if (err) 795 goto err_force_wake; 796 797 xe_gt_idle_disable_pg(gt); 798 799 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 800 xe_gt_dbg(gt, "suspended\n"); 801 802 return 0; 803 804 err_force_wake: 805 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 806 err_msg: 807 xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(err)); 808 809 return err; 810 } 811 812 /** 813 * xe_gt_sanitize_freq() - Restore saved frequencies if necessary. 814 * @gt: the GT object 815 * 816 * Called after driver init/GSC load completes to restore GT frequencies if we 817 * limited them for any WAs. 818 */ 819 int xe_gt_sanitize_freq(struct xe_gt *gt) 820 { 821 int ret = 0; 822 823 if ((!xe_uc_fw_is_available(>->uc.gsc.fw) || 824 xe_uc_fw_is_loaded(>->uc.gsc.fw)) && XE_WA(gt, 22019338487)) 825 ret = xe_guc_pc_restore_stashed_freq(>->uc.guc.pc); 826 827 return ret; 828 } 829 830 int xe_gt_resume(struct xe_gt *gt) 831 { 832 int err; 833 834 xe_gt_dbg(gt, "resuming\n"); 835 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 836 if (err) 837 goto err_msg; 838 839 err = do_gt_restart(gt); 840 if (err) 841 goto err_force_wake; 842 843 xe_gt_idle_enable_pg(gt); 844 845 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 846 xe_gt_dbg(gt, "resumed\n"); 847 848 return 0; 849 850 err_force_wake: 851 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 852 err_msg: 853 xe_gt_err(gt, "resume failed (%pe)\n", ERR_PTR(err)); 854 855 return err; 856 } 857 858 struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt, 859 enum xe_engine_class class, 860 u16 instance, bool logical) 861 { 862 struct xe_hw_engine *hwe; 863 enum xe_hw_engine_id id; 864 865 for_each_hw_engine(hwe, gt, id) 866 if (hwe->class == class && 867 ((!logical && hwe->instance == instance) || 868 (logical && hwe->logical_instance == instance))) 869 return hwe; 870 871 return NULL; 872 } 873 874 struct xe_hw_engine *xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt, 875 enum xe_engine_class class) 876 { 877 struct xe_hw_engine *hwe; 878 enum xe_hw_engine_id id; 879 880 for_each_hw_engine(hwe, gt, id) { 881 switch (class) { 882 case XE_ENGINE_CLASS_RENDER: 883 case XE_ENGINE_CLASS_COMPUTE: 884 if (hwe->class == XE_ENGINE_CLASS_RENDER || 885 hwe->class == XE_ENGINE_CLASS_COMPUTE) 886 return hwe; 887 break; 888 default: 889 if (hwe->class == class) 890 return hwe; 891 } 892 } 893 894 return NULL; 895 } 896 897 struct xe_hw_engine *xe_gt_any_hw_engine(struct xe_gt *gt) 898 { 899 struct xe_hw_engine *hwe; 900 enum xe_hw_engine_id id; 901 902 for_each_hw_engine(hwe, gt, id) 903 return hwe; 904 905 return NULL; 906 } 907 908 /** 909 * xe_gt_declare_wedged() - Declare GT wedged 910 * @gt: the GT object 911 * 912 * Wedge the GT which stops all submission, saves desired debug state, and 913 * cleans up anything which could timeout. 914 */ 915 void xe_gt_declare_wedged(struct xe_gt *gt) 916 { 917 xe_gt_assert(gt, gt_to_xe(gt)->wedged.mode); 918 919 xe_uc_declare_wedged(>->uc); 920 xe_gt_tlb_invalidation_reset(gt); 921 } 922