1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_gt.h" 7 8 #include <linux/minmax.h> 9 10 #include <kunit/visibility.h> 11 12 #include <drm/drm_managed.h> 13 #include <uapi/drm/xe_drm.h> 14 15 #include <generated/xe_device_wa_oob.h> 16 #include <generated/xe_wa_oob.h> 17 18 #include "instructions/xe_alu_commands.h" 19 #include "instructions/xe_mi_commands.h" 20 #include "regs/xe_engine_regs.h" 21 #include "regs/xe_gt_regs.h" 22 #include "xe_assert.h" 23 #include "xe_bb.h" 24 #include "xe_debugfs.h" 25 #include "xe_device.h" 26 #include "xe_eu_stall.h" 27 #include "xe_exec_queue.h" 28 #include "xe_execlist.h" 29 #include "xe_force_wake.h" 30 #include "xe_ggtt.h" 31 #include "xe_gsc.h" 32 #include "xe_gt_ccs_mode.h" 33 #include "xe_gt_clock.h" 34 #include "xe_gt_freq.h" 35 #include "xe_gt_idle.h" 36 #include "xe_gt_mcr.h" 37 #include "xe_gt_printk.h" 38 #include "xe_gt_sriov_pf.h" 39 #include "xe_gt_sriov_vf.h" 40 #include "xe_gt_stats.h" 41 #include "xe_gt_sysfs.h" 42 #include "xe_gt_topology.h" 43 #include "xe_guc_exec_queue_types.h" 44 #include "xe_guc_pc.h" 45 #include "xe_guc_rc.h" 46 #include "xe_guc_submit.h" 47 #include "xe_hw_fence.h" 48 #include "xe_hw_engine_class_sysfs.h" 49 #include "xe_irq.h" 50 #include "xe_lmtt.h" 51 #include "xe_lrc.h" 52 #include "xe_map.h" 53 #include "xe_migrate.h" 54 #include "xe_mmio.h" 55 #include "xe_pagefault.h" 56 #include "xe_pat.h" 57 #include "xe_pm.h" 58 #include "xe_mocs.h" 59 #include "xe_reg_sr.h" 60 #include "xe_ring_ops.h" 61 #include "xe_sa.h" 62 #include "xe_sched_job.h" 63 #include "xe_sriov.h" 64 #include "xe_tlb_inval.h" 65 #include "xe_tuning.h" 66 #include "xe_uc.h" 67 #include "xe_uc_fw.h" 68 #include "xe_vm.h" 69 #include "xe_wa.h" 70 #include "xe_wopcm.h" 71 72 struct xe_gt *xe_gt_alloc(struct xe_tile *tile) 73 { 74 struct xe_device *xe = tile_to_xe(tile); 75 struct drm_device *drm = &xe->drm; 76 bool shared_wq = xe->info.needs_shared_vf_gt_wq && tile->primary_gt && 77 IS_SRIOV_VF(xe); 78 struct workqueue_struct *ordered_wq; 79 struct xe_gt *gt; 80 81 gt = drmm_kzalloc(drm, sizeof(*gt), GFP_KERNEL); 82 if (!gt) 83 return ERR_PTR(-ENOMEM); 84 85 gt->tile = tile; 86 if (shared_wq && tile->primary_gt->ordered_wq) 87 ordered_wq = tile->primary_gt->ordered_wq; 88 else 89 ordered_wq = drmm_alloc_ordered_workqueue(drm, "gt-ordered-wq", 90 WQ_MEM_RECLAIM); 91 if (IS_ERR(ordered_wq)) 92 return ERR_CAST(ordered_wq); 93 94 gt->ordered_wq = ordered_wq; 95 96 return gt; 97 } 98 99 void xe_gt_sanitize(struct xe_gt *gt) 100 { 101 /* 102 * FIXME: if xe_uc_sanitize is called here, on TGL driver will not 103 * reload 104 */ 105 xe_guc_submit_disable(>->uc.guc); 106 } 107 108 static void xe_gt_enable_host_l2_vram(struct xe_gt *gt) 109 { 110 u32 reg; 111 112 if (!XE_GT_WA(gt, 16023588340)) 113 return; 114 115 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 116 if (!fw_ref.domains) 117 return; 118 119 if (xe_gt_is_main_type(gt)) { 120 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 121 reg |= CG_DIS_CNTLBUS; 122 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 123 } 124 125 xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0xF); 126 } 127 128 static void xe_gt_disable_host_l2_vram(struct xe_gt *gt) 129 { 130 u32 reg; 131 132 if (!XE_GT_WA(gt, 16023588340)) 133 return; 134 135 if (xe_gt_is_media_type(gt)) 136 return; 137 138 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 139 if (!fw_ref.domains) 140 return; 141 142 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 143 reg &= ~CG_DIS_CNTLBUS; 144 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 145 } 146 147 static void xe_gt_enable_comp_1wcoh(struct xe_gt *gt) 148 { 149 struct xe_device *xe = gt_to_xe(gt); 150 u32 reg; 151 152 if (IS_SRIOV_VF(xe)) 153 return; 154 155 if (GRAPHICS_VER(xe) >= 30 && xe->info.has_flat_ccs) { 156 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 157 if (!fw_ref.domains) 158 return; 159 160 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL); 161 reg |= EN_CMP_1WCOH; 162 xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg); 163 164 if (xe_gt_is_media_type(gt)) { 165 xe_mmio_rmw32(>->mmio, XE2_GAMWALK_CTRL_MEDIA, 0, EN_CMP_1WCOH_GW); 166 } else { 167 reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMWALK_CTRL_3D); 168 reg |= EN_CMP_1WCOH_GW; 169 xe_gt_mcr_multicast_write(gt, XE2_GAMWALK_CTRL_3D, reg); 170 } 171 } 172 } 173 174 static void gt_reset_worker(struct work_struct *w); 175 176 static int emit_job_sync(struct xe_exec_queue *q, struct xe_bb *bb, 177 long timeout_jiffies, bool force_reset) 178 { 179 struct xe_sched_job *job; 180 struct dma_fence *fence; 181 long timeout; 182 183 job = xe_bb_create_job(q, bb); 184 if (IS_ERR(job)) 185 return PTR_ERR(job); 186 187 job->ring_ops_force_reset = force_reset; 188 189 xe_sched_job_arm(job); 190 fence = dma_fence_get(&job->drm.s_fence->finished); 191 xe_sched_job_push(job); 192 193 timeout = dma_fence_wait_timeout(fence, false, timeout_jiffies); 194 dma_fence_put(fence); 195 if (timeout < 0) 196 return timeout; 197 else if (!timeout) 198 return -ETIME; 199 200 return 0; 201 } 202 203 static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q) 204 { 205 struct xe_bb *bb; 206 int ret; 207 208 bb = xe_bb_new(gt, 4, false); 209 if (IS_ERR(bb)) 210 return PTR_ERR(bb); 211 212 ret = emit_job_sync(q, bb, HZ, false); 213 xe_bb_free(bb, NULL); 214 215 return ret; 216 } 217 218 /* Dwords required to emit a RMW of a register */ 219 #define EMIT_RMW_DW 20 220 221 static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) 222 { 223 struct xe_hw_engine *hwe = q->hwe; 224 struct xe_reg_sr *sr = &hwe->reg_lrc; 225 struct xe_reg_sr_entry *entry; 226 int count_rmw = 0, count_rmw_mcr = 0, count = 0, ret; 227 unsigned long idx; 228 struct xe_bb *bb; 229 size_t bb_len = 0; 230 u32 *cs; 231 232 /* count RMW registers as those will be handled separately */ 233 xa_for_each(&sr->xa, idx, entry) { 234 if (entry->reg.masked || entry->clr_bits == ~0) 235 ++count; 236 else if (entry->reg.mcr) 237 ++count_rmw_mcr; 238 else 239 ++count_rmw; 240 } 241 242 if (count) 243 bb_len += count * 2 + 1; 244 245 /* 246 * RMW of MCR registers is the same as a normal RMW, except an 247 * additional LRI (3 dwords) is required per register to steer the read 248 * to a nom-terminated instance. 249 * 250 * We could probably shorten the batch slightly by eliding the 251 * steering for consecutive MCR registers that have the same 252 * group/instance target, but it's not worth the extra complexity to do 253 * so. 254 */ 255 bb_len += count_rmw * EMIT_RMW_DW; 256 bb_len += count_rmw_mcr * (EMIT_RMW_DW + 3); 257 258 /* 259 * After doing all RMW, we need 7 trailing dwords to clean up, 260 * plus an additional 3 dwords to reset steering if any of the 261 * registers were MCR. 262 */ 263 if (count_rmw || count_rmw_mcr) 264 bb_len += 7 + (count_rmw_mcr ? 3 : 0); 265 266 if (hwe->class == XE_ENGINE_CLASS_RENDER) 267 /* 268 * Big enough to emit all of the context's 3DSTATE via 269 * xe_lrc_emit_hwe_state_instructions() 270 */ 271 bb_len += xe_gt_lrc_size(gt, hwe->class) / sizeof(u32); 272 273 xe_gt_dbg(gt, "LRC %s WA job: %zu dwords\n", hwe->name, bb_len); 274 275 bb = xe_bb_new(gt, bb_len, false); 276 if (IS_ERR(bb)) 277 return PTR_ERR(bb); 278 279 cs = bb->cs; 280 281 if (count) { 282 /* 283 * Emit single LRI with all non RMW regs: 1 leading dw + 2dw per 284 * reg + 1 285 */ 286 287 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); 288 289 xa_for_each(&sr->xa, idx, entry) { 290 struct xe_reg reg = entry->reg; 291 u32 val; 292 293 if (reg.masked) 294 val = entry->clr_bits << 16; 295 else if (entry->clr_bits == ~0) 296 val = 0; 297 else 298 continue; 299 300 val |= entry->set_bits; 301 302 *cs++ = reg.addr; 303 *cs++ = val; 304 xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val); 305 } 306 } 307 308 if (count_rmw || count_rmw_mcr) { 309 xa_for_each(&sr->xa, idx, entry) { 310 if (entry->reg.masked || entry->clr_bits == ~0) 311 continue; 312 313 if (entry->reg.mcr) { 314 struct xe_reg_mcr reg = { .__reg.raw = entry->reg.raw }; 315 u8 group, instance; 316 317 xe_gt_mcr_get_nonterminated_steering(gt, reg, &group, &instance); 318 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1); 319 *cs++ = CS_MMIO_GROUP_INSTANCE_SELECT(hwe->mmio_base).addr; 320 *cs++ = SELECTIVE_READ_ADDRESSING | 321 REG_FIELD_PREP(SELECTIVE_READ_GROUP, group) | 322 REG_FIELD_PREP(SELECTIVE_READ_INSTANCE, instance); 323 } 324 325 *cs++ = MI_LOAD_REGISTER_REG | MI_LRR_DST_CS_MMIO; 326 *cs++ = entry->reg.addr; 327 *cs++ = CS_GPR_REG(0, 0).addr; 328 329 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) | 330 MI_LRI_LRM_CS_MMIO; 331 *cs++ = CS_GPR_REG(0, 1).addr; 332 *cs++ = entry->clr_bits; 333 *cs++ = CS_GPR_REG(0, 2).addr; 334 *cs++ = entry->set_bits; 335 336 *cs++ = MI_MATH(8); 337 *cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0); 338 *cs++ = CS_ALU_INSTR_LOADINV(SRCB, REG1); 339 *cs++ = CS_ALU_INSTR_AND; 340 *cs++ = CS_ALU_INSTR_STORE(REG0, ACCU); 341 *cs++ = CS_ALU_INSTR_LOAD(SRCA, REG0); 342 *cs++ = CS_ALU_INSTR_LOAD(SRCB, REG2); 343 *cs++ = CS_ALU_INSTR_OR; 344 *cs++ = CS_ALU_INSTR_STORE(REG0, ACCU); 345 346 *cs++ = MI_LOAD_REGISTER_REG | MI_LRR_SRC_CS_MMIO; 347 *cs++ = CS_GPR_REG(0, 0).addr; 348 *cs++ = entry->reg.addr; 349 350 xe_gt_dbg(gt, "REG[%#x] = ~%#x|%#x%s\n", 351 entry->reg.addr, entry->clr_bits, entry->set_bits, 352 entry->reg.mcr ? " (MCR)" : ""); 353 } 354 355 /* reset used GPR */ 356 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(3) | 357 MI_LRI_LRM_CS_MMIO; 358 *cs++ = CS_GPR_REG(0, 0).addr; 359 *cs++ = 0; 360 *cs++ = CS_GPR_REG(0, 1).addr; 361 *cs++ = 0; 362 *cs++ = CS_GPR_REG(0, 2).addr; 363 *cs++ = 0; 364 365 /* reset steering */ 366 if (count_rmw_mcr) { 367 *cs++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1); 368 *cs++ = CS_MMIO_GROUP_INSTANCE_SELECT(q->hwe->mmio_base).addr; 369 *cs++ = 0; 370 } 371 } 372 373 cs = xe_lrc_emit_hwe_state_instructions(q, cs); 374 375 bb->len = cs - bb->cs; 376 377 /* only VFs need to trigger reset to get a clean NULL context */ 378 ret = emit_job_sync(q, bb, HZ, IS_SRIOV_VF(gt_to_xe(gt))); 379 380 xe_bb_free(bb, NULL); 381 382 return ret; 383 } 384 385 int xe_gt_record_default_lrcs(struct xe_gt *gt) 386 { 387 struct xe_device *xe = gt_to_xe(gt); 388 struct xe_hw_engine *hwe; 389 enum xe_hw_engine_id id; 390 int err = 0; 391 392 for_each_hw_engine(hwe, gt, id) { 393 struct xe_exec_queue *q, *nop_q; 394 void *default_lrc; 395 396 if (gt->default_lrc[hwe->class]) 397 continue; 398 399 xe_hw_engine_setup_reg_lrc(hwe); 400 401 default_lrc = drmm_kzalloc(&xe->drm, 402 xe_gt_lrc_size(gt, hwe->class), 403 GFP_KERNEL); 404 if (!default_lrc) 405 return -ENOMEM; 406 407 q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 1, 408 hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 409 if (IS_ERR(q)) { 410 err = PTR_ERR(q); 411 xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n", 412 hwe->name, q); 413 return err; 414 } 415 416 /* Prime golden LRC with known good state */ 417 err = emit_wa_job(gt, q); 418 if (err) { 419 xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n", 420 hwe->name, ERR_PTR(err), q->guc->id); 421 goto put_exec_queue; 422 } 423 424 nop_q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 425 1, hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 426 if (IS_ERR(nop_q)) { 427 err = PTR_ERR(nop_q); 428 xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n", 429 hwe->name, nop_q); 430 goto put_exec_queue; 431 } 432 433 /* Switch to different LRC */ 434 err = emit_nop_job(gt, nop_q); 435 if (err) { 436 xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n", 437 hwe->name, ERR_PTR(err), nop_q->guc->id); 438 goto put_nop_q; 439 } 440 441 xe_map_memcpy_from(xe, default_lrc, 442 &q->lrc[0]->bo->vmap, 443 xe_lrc_pphwsp_offset(q->lrc[0]), 444 xe_gt_lrc_size(gt, hwe->class)); 445 446 gt->default_lrc[hwe->class] = default_lrc; 447 put_nop_q: 448 xe_exec_queue_put(nop_q); 449 put_exec_queue: 450 xe_exec_queue_put(q); 451 if (err) 452 break; 453 } 454 455 return err; 456 } 457 458 static void wa_14026539277(struct xe_gt *gt) 459 { 460 struct xe_device *xe = gt_to_xe(gt); 461 u32 val; 462 463 /* 464 * FIXME: We currently can't use FUNC(xe_rtp_match_not_sriov_vf) in the 465 * rules for Wa_14026539277 due to xe_wa_process_device_oob() being 466 * called before xe_sriov_probe_early(); and we can't move the call to 467 * the former to happen after the latter because MMIO read functions 468 * already depend on a device OOB workaround. This needs to be fixed by 469 * allowing workaround checks to happen at different stages of driver 470 * initialization. 471 */ 472 if (IS_SRIOV_VF(xe)) 473 return; 474 475 if (!XE_DEVICE_WA(xe, 14026539277)) 476 return; 477 478 if (!xe_gt_is_main_type(gt)) 479 return; 480 481 val = xe_gt_mcr_unicast_read_any(gt, L2COMPUTESIDECTRL); 482 val &= ~CECTRL; 483 val |= CECTRL_CENODATA_ALWAYS; 484 xe_gt_mcr_multicast_write(gt, L2COMPUTESIDECTRL, val); 485 } 486 487 int xe_gt_init_early(struct xe_gt *gt) 488 { 489 int err; 490 491 if (IS_SRIOV_PF(gt_to_xe(gt))) { 492 err = xe_gt_sriov_pf_init_early(gt); 493 if (err) 494 return err; 495 } 496 497 if (IS_SRIOV_VF(gt_to_xe(gt))) { 498 err = xe_gt_sriov_vf_init_early(gt); 499 if (err) 500 return err; 501 } 502 503 xe_reg_sr_init(>->reg_sr, "GT", gt_to_xe(gt)); 504 505 err = xe_wa_gt_init(gt); 506 if (err) 507 return err; 508 509 err = xe_tuning_init(gt); 510 if (err) 511 return err; 512 513 xe_wa_process_gt_oob(gt); 514 515 xe_force_wake_init_gt(gt, gt_to_fw(gt)); 516 spin_lock_init(>->global_invl_lock); 517 518 err = xe_gt_tlb_inval_init_early(gt); 519 if (err) 520 return err; 521 522 xe_mocs_init_early(gt); 523 524 /* 525 * Only after this point can GT-specific MMIO operations 526 * (including things like communication with the GuC) 527 * be performed. 528 */ 529 xe_gt_mmio_init(gt); 530 531 err = xe_uc_init_noalloc(>->uc); 532 if (err) 533 return err; 534 535 err = xe_gt_stats_init(gt); 536 if (err) 537 return err; 538 539 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 540 if (!fw_ref.domains) 541 return -ETIMEDOUT; 542 543 xe_gt_mcr_init_early(gt); 544 xe_pat_init(gt); 545 546 return 0; 547 } 548 549 static void dump_pat_on_error(struct xe_gt *gt) 550 { 551 struct drm_printer p; 552 char prefix[32]; 553 554 snprintf(prefix, sizeof(prefix), "[GT%u Error]", gt->info.id); 555 p = drm_dbg_printer(>_to_xe(gt)->drm, DRM_UT_DRIVER, prefix); 556 557 xe_pat_dump(gt, &p); 558 } 559 560 static int gt_init_with_gt_forcewake(struct xe_gt *gt) 561 { 562 int err; 563 564 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 565 if (!fw_ref.domains) 566 return -ETIMEDOUT; 567 568 err = xe_uc_init(>->uc); 569 if (err) 570 return err; 571 572 xe_gt_topology_init(gt); 573 xe_gt_mcr_init(gt); 574 xe_gt_enable_host_l2_vram(gt); 575 xe_gt_enable_comp_1wcoh(gt); 576 577 if (xe_gt_is_main_type(gt)) { 578 err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt); 579 if (err) 580 return err; 581 if (IS_SRIOV_PF(gt_to_xe(gt))) 582 xe_lmtt_init(>_to_tile(gt)->sriov.pf.lmtt); 583 } 584 585 /* Enable per hw engine IRQs */ 586 xe_irq_enable_hwe(gt); 587 588 /* Rerun MCR init as we now have hw engine list */ 589 xe_gt_mcr_init(gt); 590 591 err = xe_hw_engines_init_early(gt); 592 if (err) { 593 dump_pat_on_error(gt); 594 return err; 595 } 596 597 err = xe_hw_engine_class_sysfs_init(gt); 598 if (err) 599 return err; 600 601 /* Initialize CCS mode sysfs after early initialization of HW engines */ 602 err = xe_gt_ccs_mode_sysfs_init(gt); 603 if (err) 604 return err; 605 606 /* 607 * Stash hardware-reported version. Since this register does not exist 608 * on pre-MTL platforms, reading it there will (correctly) return 0. 609 */ 610 gt->info.gmdid = xe_mmio_read32(>->mmio, GMD_ID); 611 612 /* 613 * Wa_14026539277 can't be implemented as a regular GT workaround (i.e. 614 * as an entry in gt_was[]) for two reasons: it is actually a device 615 * workaround that happens to involve programming a GT register; and it 616 * needs to be applied early to avoid getting the hardware in a bad 617 * state before we have a chance to do the necessary programming. 618 */ 619 wa_14026539277(gt); 620 621 return 0; 622 } 623 624 static int gt_init_with_all_forcewake(struct xe_gt *gt) 625 { 626 int err; 627 628 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 629 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL)) 630 return -ETIMEDOUT; 631 632 xe_gt_mcr_set_implicit_defaults(gt); 633 xe_wa_process_gt(gt); 634 xe_tuning_process_gt(gt); 635 xe_reg_sr_apply_mmio(>->reg_sr, gt); 636 637 err = xe_gt_clock_init(gt); 638 if (err) 639 return err; 640 641 xe_mocs_init(gt); 642 err = xe_execlist_init(gt); 643 if (err) 644 return err; 645 646 err = xe_hw_engines_init(gt); 647 if (err) 648 return err; 649 650 err = xe_uc_init_post_hwconfig(>->uc); 651 if (err) 652 return err; 653 654 if (xe_gt_is_main_type(gt)) { 655 /* 656 * USM has its only SA pool to non-block behind user operations 657 */ 658 if (gt_to_xe(gt)->info.has_usm) { 659 struct xe_device *xe = gt_to_xe(gt); 660 661 gt->usm.bb_pool = xe_sa_bo_manager_init(gt_to_tile(gt), 662 IS_DGFX(xe) ? SZ_1M : SZ_512K, 16); 663 if (IS_ERR(gt->usm.bb_pool)) 664 return PTR_ERR(gt->usm.bb_pool); 665 } 666 } 667 668 if (xe_gt_is_main_type(gt)) { 669 struct xe_tile *tile = gt_to_tile(gt); 670 671 err = xe_migrate_init(tile->migrate); 672 if (err) 673 return err; 674 } 675 676 err = xe_uc_load_hw(>->uc); 677 if (err) 678 return err; 679 680 /* Configure default CCS mode of 1 engine with all resources */ 681 if (xe_gt_ccs_mode_enabled(gt)) { 682 gt->ccs_mode = 1; 683 xe_gt_apply_ccs_mode(gt); 684 } 685 686 if (IS_SRIOV_PF(gt_to_xe(gt)) && xe_gt_is_main_type(gt)) 687 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 688 689 if (IS_SRIOV_PF(gt_to_xe(gt))) 690 xe_gt_sriov_pf_init_hw(gt); 691 692 return 0; 693 } 694 695 static void xe_gt_fini(void *arg) 696 { 697 struct xe_gt *gt = arg; 698 int i; 699 700 if (disable_work_sync(>->reset.worker)) 701 /* 702 * If gt_reset_worker was halted from executing, take care of 703 * releasing the rpm reference here. 704 */ 705 xe_pm_runtime_put(gt_to_xe(gt)); 706 707 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 708 xe_hw_fence_irq_finish(>->fence_irq[i]); 709 710 xe_gt_disable_host_l2_vram(gt); 711 } 712 713 int xe_gt_init(struct xe_gt *gt) 714 { 715 int err; 716 int i; 717 718 INIT_WORK(>->reset.worker, gt_reset_worker); 719 720 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) { 721 gt->ring_ops[i] = xe_ring_ops_get(gt, i); 722 xe_hw_fence_irq_init(>->fence_irq[i]); 723 } 724 725 err = devm_add_action_or_reset(gt_to_xe(gt)->drm.dev, xe_gt_fini, gt); 726 if (err) 727 return err; 728 729 err = xe_gt_sysfs_init(gt); 730 if (err) 731 return err; 732 733 err = gt_init_with_gt_forcewake(gt); 734 if (err) 735 return err; 736 737 err = xe_gt_idle_init(>->gtidle); 738 if (err) 739 return err; 740 741 err = xe_gt_freq_init(gt); 742 if (err) 743 return err; 744 745 xe_force_wake_init_engines(gt, gt_to_fw(gt)); 746 747 err = gt_init_with_all_forcewake(gt); 748 if (err) 749 return err; 750 751 xe_gt_record_user_engines(gt); 752 753 err = xe_eu_stall_init(gt); 754 if (err) 755 return err; 756 757 if (IS_SRIOV_VF(gt_to_xe(gt))) { 758 err = xe_gt_sriov_vf_init(gt); 759 if (err) 760 return err; 761 } 762 763 return 0; 764 } 765 766 /** 767 * xe_gt_mmio_init() - Initialize GT's MMIO access 768 * @gt: the GT object 769 * 770 * Initialize GT's MMIO accessor, which will be used to access registers inside 771 * this GT. 772 */ 773 void xe_gt_mmio_init(struct xe_gt *gt) 774 { 775 struct xe_tile *tile = gt_to_tile(gt); 776 struct xe_device *xe = tile_to_xe(tile); 777 778 xe_mmio_init(>->mmio, tile, tile->mmio.regs, tile->mmio.regs_size); 779 780 if (gt->info.type == XE_GT_TYPE_MEDIA) { 781 gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET; 782 gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH; 783 } else { 784 gt->mmio.adj_offset = 0; 785 gt->mmio.adj_limit = 0; 786 } 787 788 if (IS_SRIOV_VF(xe)) 789 gt->mmio.sriov_vf_gt = gt; 790 } 791 EXPORT_SYMBOL_IF_KUNIT(xe_gt_mmio_init); 792 793 void xe_gt_record_user_engines(struct xe_gt *gt) 794 { 795 struct xe_hw_engine *hwe; 796 enum xe_hw_engine_id id; 797 798 gt->user_engines.mask = 0; 799 memset(gt->user_engines.instances_per_class, 0, 800 sizeof(gt->user_engines.instances_per_class)); 801 802 for_each_hw_engine(hwe, gt, id) { 803 if (xe_hw_engine_is_reserved(hwe)) 804 continue; 805 806 gt->user_engines.mask |= BIT_ULL(id); 807 gt->user_engines.instances_per_class[hwe->class]++; 808 } 809 810 xe_gt_assert(gt, (gt->user_engines.mask | gt->info.engine_mask) 811 == gt->info.engine_mask); 812 } 813 814 static int do_gt_reset(struct xe_gt *gt) 815 { 816 int err; 817 818 if (IS_SRIOV_VF(gt_to_xe(gt))) 819 return xe_gt_sriov_vf_reset(gt); 820 821 xe_gsc_wa_14015076503(gt, true); 822 823 xe_mmio_write32(>->mmio, GDRST, GRDOM_FULL); 824 err = xe_mmio_wait32(>->mmio, GDRST, GRDOM_FULL, 0, 5000, NULL, false); 825 if (err) 826 xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n", 827 ERR_PTR(err)); 828 829 xe_gsc_wa_14015076503(gt, false); 830 831 return err; 832 } 833 834 static int vf_gt_restart(struct xe_gt *gt) 835 { 836 int err; 837 838 err = xe_uc_sanitize_reset(>->uc); 839 if (err) 840 return err; 841 842 err = xe_uc_load_hw(>->uc); 843 if (err) 844 return err; 845 846 err = xe_uc_start(>->uc); 847 if (err) 848 return err; 849 850 return 0; 851 } 852 853 static int do_gt_restart(struct xe_gt *gt) 854 { 855 struct xe_hw_engine *hwe; 856 enum xe_hw_engine_id id; 857 int err; 858 859 if (IS_SRIOV_VF(gt_to_xe(gt))) 860 return vf_gt_restart(gt); 861 862 xe_pat_init(gt); 863 864 xe_gt_enable_host_l2_vram(gt); 865 xe_gt_enable_comp_1wcoh(gt); 866 867 xe_gt_mcr_set_implicit_defaults(gt); 868 xe_reg_sr_apply_mmio(>->reg_sr, gt); 869 870 err = xe_wopcm_init(>->uc.wopcm); 871 if (err) 872 return err; 873 874 for_each_hw_engine(hwe, gt, id) 875 xe_hw_engine_enable_ring(hwe); 876 877 err = xe_uc_sanitize_reset(>->uc); 878 if (err) 879 return err; 880 881 err = xe_uc_load_hw(>->uc); 882 if (err) 883 return err; 884 885 if (IS_SRIOV_PF(gt_to_xe(gt)) && xe_gt_is_main_type(gt)) 886 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 887 888 if (IS_SRIOV_PF(gt_to_xe(gt))) 889 xe_gt_sriov_pf_init_hw(gt); 890 891 xe_mocs_init(gt); 892 893 for_each_hw_engine(hwe, gt, id) 894 xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); 895 896 /* Get CCS mode in sync between sw/hw */ 897 xe_gt_apply_ccs_mode(gt); 898 899 err = xe_uc_start(>->uc); 900 if (err) 901 return err; 902 903 /* Restore GT freq to expected values */ 904 xe_gt_sanitize_freq(gt); 905 906 if (IS_SRIOV_PF(gt_to_xe(gt))) 907 xe_gt_sriov_pf_restart(gt); 908 909 return 0; 910 } 911 912 static void gt_reset_worker(struct work_struct *w) 913 { 914 struct xe_gt *gt = container_of(w, typeof(*gt), reset.worker); 915 unsigned int fw_ref; 916 int err; 917 918 if (xe_device_wedged(gt_to_xe(gt))) 919 goto err_pm_put; 920 921 if (xe_device_is_in_reset(gt_to_xe(gt))) 922 goto err_pm_put; 923 924 /* We only support GT resets with GuC submission */ 925 if (!xe_device_uc_enabled(gt_to_xe(gt))) 926 goto err_pm_put; 927 928 xe_gt_info(gt, "reset started\n"); 929 930 if (xe_fault_gt_reset()) { 931 err = -ECANCELED; 932 goto err_fail; 933 } 934 935 xe_gt_sanitize(gt); 936 937 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 938 if (!xe_force_wake_ref_has_domain(fw_ref, XE_FORCEWAKE_ALL)) { 939 err = -ETIMEDOUT; 940 goto err_out; 941 } 942 943 if (IS_SRIOV_PF(gt_to_xe(gt))) 944 xe_gt_sriov_pf_stop_prepare(gt); 945 946 xe_guc_rc_disable(>->uc.guc); 947 xe_uc_stop_prepare(>->uc); 948 xe_pagefault_reset(gt_to_xe(gt), gt); 949 950 xe_uc_stop(>->uc); 951 952 xe_tlb_inval_reset(>->tlb_inval); 953 954 err = do_gt_reset(gt); 955 if (err) 956 goto err_out; 957 958 err = do_gt_restart(gt); 959 if (err) 960 goto err_out; 961 962 xe_force_wake_put(gt_to_fw(gt), fw_ref); 963 964 /* Pair with get while enqueueing the work in xe_gt_reset_async() */ 965 xe_pm_runtime_put(gt_to_xe(gt)); 966 967 xe_gt_info(gt, "reset done\n"); 968 969 return; 970 971 err_out: 972 xe_force_wake_put(gt_to_fw(gt), fw_ref); 973 XE_WARN_ON(xe_uc_start(>->uc)); 974 975 err_fail: 976 xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err)); 977 xe_device_declare_wedged(gt_to_xe(gt)); 978 err_pm_put: 979 xe_pm_runtime_put(gt_to_xe(gt)); 980 } 981 982 void xe_gt_reset_async(struct xe_gt *gt) 983 { 984 struct xe_device *xe = gt_to_xe(gt); 985 986 if (xe_device_is_in_reset(xe)) 987 return; 988 989 /* Don't do a reset while one is already in flight */ 990 if (!xe_fault_gt_reset() && xe_uc_reset_prepare(>->uc)) 991 return; 992 993 xe_gt_info(gt, "reset queued from %ps\n", __builtin_return_address(0)); 994 995 /* Pair with put in gt_reset_worker() if work is enqueued */ 996 xe_pm_runtime_get_noresume(xe); 997 if (!queue_work(gt->ordered_wq, >->reset.worker)) 998 xe_pm_runtime_put(xe); 999 } 1000 1001 void xe_gt_suspend_prepare(struct xe_gt *gt) 1002 { 1003 xe_uc_suspend_prepare(>->uc); 1004 } 1005 1006 int xe_gt_suspend(struct xe_gt *gt) 1007 { 1008 int err; 1009 1010 xe_gt_dbg(gt, "suspending\n"); 1011 xe_gt_sanitize(gt); 1012 1013 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 1014 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL)) { 1015 xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(-ETIMEDOUT)); 1016 return -ETIMEDOUT; 1017 } 1018 1019 err = xe_uc_suspend(>->uc); 1020 if (err) { 1021 xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(err)); 1022 return err; 1023 } 1024 1025 xe_gt_idle_disable_pg(gt); 1026 1027 xe_gt_disable_host_l2_vram(gt); 1028 1029 xe_gt_dbg(gt, "suspended\n"); 1030 1031 return 0; 1032 } 1033 1034 void xe_gt_shutdown(struct xe_gt *gt) 1035 { 1036 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 1037 do_gt_reset(gt); 1038 } 1039 1040 /** 1041 * xe_gt_sanitize_freq() - Restore saved frequencies if necessary. 1042 * @gt: the GT object 1043 * 1044 * Called after driver init/GSC load completes to restore GT frequencies if we 1045 * limited them for any WAs. 1046 */ 1047 int xe_gt_sanitize_freq(struct xe_gt *gt) 1048 { 1049 int ret = 0; 1050 1051 if ((!xe_uc_fw_is_available(>->uc.gsc.fw) || 1052 xe_uc_fw_is_loaded(>->uc.gsc.fw) || 1053 xe_uc_fw_is_in_error_state(>->uc.gsc.fw)) && 1054 XE_GT_WA(gt, 22019338487)) 1055 ret = xe_guc_pc_restore_stashed_freq(>->uc.guc.pc); 1056 1057 return ret; 1058 } 1059 1060 int xe_gt_resume(struct xe_gt *gt) 1061 { 1062 int err; 1063 1064 xe_gt_dbg(gt, "resuming\n"); 1065 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 1066 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL)) { 1067 xe_gt_err(gt, "resume failed (%pe)\n", ERR_PTR(-ETIMEDOUT)); 1068 return -ETIMEDOUT; 1069 } 1070 1071 err = do_gt_restart(gt); 1072 if (err) 1073 return err; 1074 1075 xe_gt_idle_enable_pg(gt); 1076 1077 xe_gt_dbg(gt, "resumed\n"); 1078 1079 return 0; 1080 } 1081 1082 /** 1083 * xe_gt_runtime_suspend() - GT runtime suspend 1084 * @gt: the GT object 1085 * 1086 * Return: 0 on success, negative error code otherwise. 1087 */ 1088 int xe_gt_runtime_suspend(struct xe_gt *gt) 1089 { 1090 xe_gt_dbg(gt, "runtime suspending\n"); 1091 1092 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 1093 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL)) { 1094 xe_gt_err(gt, "runtime suspend failed (%pe)\n", ERR_PTR(-ETIMEDOUT)); 1095 return -ETIMEDOUT; 1096 } 1097 1098 xe_uc_runtime_suspend(>->uc); 1099 xe_gt_disable_host_l2_vram(gt); 1100 1101 xe_gt_dbg(gt, "runtime suspended\n"); 1102 1103 return 0; 1104 } 1105 1106 /** 1107 * xe_gt_runtime_resume() - GT runtime resume 1108 * @gt: the GT object 1109 * 1110 * Return: 0 on success, negative error code otherwise. 1111 */ 1112 int xe_gt_runtime_resume(struct xe_gt *gt) 1113 { 1114 xe_gt_dbg(gt, "runtime resuming\n"); 1115 1116 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FORCEWAKE_ALL); 1117 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FORCEWAKE_ALL)) { 1118 xe_gt_err(gt, "runtime resume failed (%pe)\n", ERR_PTR(-ETIMEDOUT)); 1119 return -ETIMEDOUT; 1120 } 1121 1122 xe_gt_enable_host_l2_vram(gt); 1123 xe_uc_runtime_resume(>->uc); 1124 1125 xe_gt_dbg(gt, "runtime resumed\n"); 1126 1127 return 0; 1128 } 1129 1130 struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt, 1131 enum xe_engine_class class, 1132 u16 instance, bool logical) 1133 { 1134 struct xe_hw_engine *hwe; 1135 enum xe_hw_engine_id id; 1136 1137 for_each_hw_engine(hwe, gt, id) 1138 if (hwe->class == class && 1139 ((!logical && hwe->instance == instance) || 1140 (logical && hwe->logical_instance == instance))) 1141 return hwe; 1142 1143 return NULL; 1144 } 1145 1146 struct xe_hw_engine *xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt, 1147 enum xe_engine_class class) 1148 { 1149 struct xe_hw_engine *hwe; 1150 enum xe_hw_engine_id id; 1151 1152 for_each_hw_engine(hwe, gt, id) { 1153 switch (class) { 1154 case XE_ENGINE_CLASS_RENDER: 1155 case XE_ENGINE_CLASS_COMPUTE: 1156 if (hwe->class == XE_ENGINE_CLASS_RENDER || 1157 hwe->class == XE_ENGINE_CLASS_COMPUTE) 1158 return hwe; 1159 break; 1160 default: 1161 if (hwe->class == class) 1162 return hwe; 1163 } 1164 } 1165 1166 return NULL; 1167 } 1168 1169 struct xe_hw_engine *xe_gt_any_hw_engine(struct xe_gt *gt) 1170 { 1171 struct xe_hw_engine *hwe; 1172 enum xe_hw_engine_id id; 1173 1174 for_each_hw_engine(hwe, gt, id) 1175 return hwe; 1176 1177 return NULL; 1178 } 1179 1180 /** 1181 * xe_gt_declare_wedged() - Declare GT wedged 1182 * @gt: the GT object 1183 * 1184 * Wedge the GT which stops all submission, saves desired debug state, and 1185 * cleans up anything which could timeout. 1186 */ 1187 void xe_gt_declare_wedged(struct xe_gt *gt) 1188 { 1189 xe_gt_assert(gt, gt_to_xe(gt)->wedged.mode); 1190 1191 xe_uc_declare_wedged(>->uc); 1192 xe_tlb_inval_reset(>->tlb_inval); 1193 } 1194