1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_gt.h" 7 8 #include <linux/minmax.h> 9 10 #include <drm/drm_managed.h> 11 #include <drm/xe_drm.h> 12 #include <generated/xe_wa_oob.h> 13 14 #include <generated/xe_wa_oob.h> 15 16 #include "instructions/xe_gfxpipe_commands.h" 17 #include "instructions/xe_mi_commands.h" 18 #include "regs/xe_gt_regs.h" 19 #include "xe_assert.h" 20 #include "xe_bb.h" 21 #include "xe_bo.h" 22 #include "xe_device.h" 23 #include "xe_exec_queue.h" 24 #include "xe_execlist.h" 25 #include "xe_force_wake.h" 26 #include "xe_ggtt.h" 27 #include "xe_gsc.h" 28 #include "xe_gt_ccs_mode.h" 29 #include "xe_gt_clock.h" 30 #include "xe_gt_freq.h" 31 #include "xe_gt_idle.h" 32 #include "xe_gt_mcr.h" 33 #include "xe_gt_pagefault.h" 34 #include "xe_gt_printk.h" 35 #include "xe_gt_sriov_pf.h" 36 #include "xe_gt_sysfs.h" 37 #include "xe_gt_tlb_invalidation.h" 38 #include "xe_gt_topology.h" 39 #include "xe_guc_exec_queue_types.h" 40 #include "xe_guc_pc.h" 41 #include "xe_hw_fence.h" 42 #include "xe_hw_engine_class_sysfs.h" 43 #include "xe_irq.h" 44 #include "xe_lmtt.h" 45 #include "xe_lrc.h" 46 #include "xe_map.h" 47 #include "xe_migrate.h" 48 #include "xe_mmio.h" 49 #include "xe_pat.h" 50 #include "xe_pcode.h" 51 #include "xe_pm.h" 52 #include "xe_mocs.h" 53 #include "xe_reg_sr.h" 54 #include "xe_ring_ops.h" 55 #include "xe_sa.h" 56 #include "xe_sched_job.h" 57 #include "xe_sriov.h" 58 #include "xe_tuning.h" 59 #include "xe_uc.h" 60 #include "xe_uc_fw.h" 61 #include "xe_vm.h" 62 #include "xe_wa.h" 63 #include "xe_wopcm.h" 64 65 static void gt_fini(struct drm_device *drm, void *arg) 66 { 67 struct xe_gt *gt = arg; 68 69 destroy_workqueue(gt->ordered_wq); 70 } 71 72 struct xe_gt *xe_gt_alloc(struct xe_tile *tile) 73 { 74 struct xe_gt *gt; 75 int err; 76 77 gt = drmm_kzalloc(&tile_to_xe(tile)->drm, sizeof(*gt), GFP_KERNEL); 78 if (!gt) 79 return ERR_PTR(-ENOMEM); 80 81 gt->tile = tile; 82 gt->ordered_wq = alloc_ordered_workqueue("gt-ordered-wq", 0); 83 84 err = drmm_add_action_or_reset(>_to_xe(gt)->drm, gt_fini, gt); 85 if (err) 86 return ERR_PTR(err); 87 88 return gt; 89 } 90 91 void xe_gt_sanitize(struct xe_gt *gt) 92 { 93 /* 94 * FIXME: if xe_uc_sanitize is called here, on TGL driver will not 95 * reload 96 */ 97 gt->uc.guc.submission_state.enabled = false; 98 } 99 100 static void xe_gt_enable_host_l2_vram(struct xe_gt *gt) 101 { 102 u32 reg; 103 int err; 104 105 if (!XE_WA(gt, 16023588340)) 106 return; 107 108 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 109 if (WARN_ON(err)) 110 return; 111 112 if (!xe_gt_is_media_type(gt)) { 113 xe_mmio_write32(gt, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH); 114 reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL); 115 reg |= CG_DIS_CNTLBUS; 116 xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg); 117 } 118 119 xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0x3); 120 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 121 } 122 123 static void xe_gt_disable_host_l2_vram(struct xe_gt *gt) 124 { 125 u32 reg; 126 int err; 127 128 if (!XE_WA(gt, 16023588340)) 129 return; 130 131 if (xe_gt_is_media_type(gt)) 132 return; 133 134 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 135 if (WARN_ON(err)) 136 return; 137 138 reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL); 139 reg &= ~CG_DIS_CNTLBUS; 140 xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg); 141 142 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 143 } 144 145 /** 146 * xe_gt_remove() - Clean up the GT structures before driver removal 147 * @gt: the GT object 148 * 149 * This function should only act on objects/structures that must be cleaned 150 * before the driver removal callback is complete and therefore can't be 151 * deferred to a drmm action. 152 */ 153 void xe_gt_remove(struct xe_gt *gt) 154 { 155 int i; 156 157 xe_uc_remove(>->uc); 158 159 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 160 xe_hw_fence_irq_finish(>->fence_irq[i]); 161 162 xe_gt_disable_host_l2_vram(gt); 163 } 164 165 static void gt_reset_worker(struct work_struct *w); 166 167 static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q) 168 { 169 struct xe_sched_job *job; 170 struct xe_bb *bb; 171 struct dma_fence *fence; 172 long timeout; 173 174 bb = xe_bb_new(gt, 4, false); 175 if (IS_ERR(bb)) 176 return PTR_ERR(bb); 177 178 job = xe_bb_create_job(q, bb); 179 if (IS_ERR(job)) { 180 xe_bb_free(bb, NULL); 181 return PTR_ERR(job); 182 } 183 184 xe_sched_job_arm(job); 185 fence = dma_fence_get(&job->drm.s_fence->finished); 186 xe_sched_job_push(job); 187 188 timeout = dma_fence_wait_timeout(fence, false, HZ); 189 dma_fence_put(fence); 190 xe_bb_free(bb, NULL); 191 if (timeout < 0) 192 return timeout; 193 else if (!timeout) 194 return -ETIME; 195 196 return 0; 197 } 198 199 /* 200 * Convert back from encoded value to type-safe, only to be used when reg.mcr 201 * is true 202 */ 203 static struct xe_reg_mcr to_xe_reg_mcr(const struct xe_reg reg) 204 { 205 return (const struct xe_reg_mcr){.__reg.raw = reg.raw }; 206 } 207 208 static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) 209 { 210 struct xe_reg_sr *sr = &q->hwe->reg_lrc; 211 struct xe_reg_sr_entry *entry; 212 unsigned long idx; 213 struct xe_sched_job *job; 214 struct xe_bb *bb; 215 struct dma_fence *fence; 216 long timeout; 217 int count = 0; 218 219 if (q->hwe->class == XE_ENGINE_CLASS_RENDER) 220 /* Big enough to emit all of the context's 3DSTATE */ 221 bb = xe_bb_new(gt, xe_gt_lrc_size(gt, q->hwe->class), false); 222 else 223 /* Just pick a large BB size */ 224 bb = xe_bb_new(gt, SZ_4K, false); 225 226 if (IS_ERR(bb)) 227 return PTR_ERR(bb); 228 229 xa_for_each(&sr->xa, idx, entry) 230 ++count; 231 232 if (count) { 233 xe_gt_dbg(gt, "LRC WA %s save-restore batch\n", sr->name); 234 235 bb->cs[bb->len++] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(count); 236 237 xa_for_each(&sr->xa, idx, entry) { 238 struct xe_reg reg = entry->reg; 239 struct xe_reg_mcr reg_mcr = to_xe_reg_mcr(reg); 240 u32 val; 241 242 /* 243 * Skip reading the register if it's not really needed 244 */ 245 if (reg.masked) 246 val = entry->clr_bits << 16; 247 else if (entry->clr_bits + 1) 248 val = (reg.mcr ? 249 xe_gt_mcr_unicast_read_any(gt, reg_mcr) : 250 xe_mmio_read32(gt, reg)) & (~entry->clr_bits); 251 else 252 val = 0; 253 254 val |= entry->set_bits; 255 256 bb->cs[bb->len++] = reg.addr; 257 bb->cs[bb->len++] = val; 258 xe_gt_dbg(gt, "REG[0x%x] = 0x%08x", reg.addr, val); 259 } 260 } 261 262 xe_lrc_emit_hwe_state_instructions(q, bb); 263 264 job = xe_bb_create_job(q, bb); 265 if (IS_ERR(job)) { 266 xe_bb_free(bb, NULL); 267 return PTR_ERR(job); 268 } 269 270 xe_sched_job_arm(job); 271 fence = dma_fence_get(&job->drm.s_fence->finished); 272 xe_sched_job_push(job); 273 274 timeout = dma_fence_wait_timeout(fence, false, HZ); 275 dma_fence_put(fence); 276 xe_bb_free(bb, NULL); 277 if (timeout < 0) 278 return timeout; 279 else if (!timeout) 280 return -ETIME; 281 282 return 0; 283 } 284 285 int xe_gt_record_default_lrcs(struct xe_gt *gt) 286 { 287 struct xe_device *xe = gt_to_xe(gt); 288 struct xe_hw_engine *hwe; 289 enum xe_hw_engine_id id; 290 int err = 0; 291 292 for_each_hw_engine(hwe, gt, id) { 293 struct xe_exec_queue *q, *nop_q; 294 void *default_lrc; 295 296 if (gt->default_lrc[hwe->class]) 297 continue; 298 299 xe_reg_sr_init(&hwe->reg_lrc, hwe->name, xe); 300 xe_wa_process_lrc(hwe); 301 xe_hw_engine_setup_default_lrc_state(hwe); 302 xe_tuning_process_lrc(hwe); 303 304 default_lrc = drmm_kzalloc(&xe->drm, 305 xe_gt_lrc_size(gt, hwe->class), 306 GFP_KERNEL); 307 if (!default_lrc) 308 return -ENOMEM; 309 310 q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 1, 311 hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 312 if (IS_ERR(q)) { 313 err = PTR_ERR(q); 314 xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n", 315 hwe->name, q); 316 return err; 317 } 318 319 /* Prime golden LRC with known good state */ 320 err = emit_wa_job(gt, q); 321 if (err) { 322 xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n", 323 hwe->name, ERR_PTR(err), q->guc->id); 324 goto put_exec_queue; 325 } 326 327 nop_q = xe_exec_queue_create(xe, NULL, BIT(hwe->logical_instance), 328 1, hwe, EXEC_QUEUE_FLAG_KERNEL, 0); 329 if (IS_ERR(nop_q)) { 330 err = PTR_ERR(nop_q); 331 xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n", 332 hwe->name, nop_q); 333 goto put_exec_queue; 334 } 335 336 /* Switch to different LRC */ 337 err = emit_nop_job(gt, nop_q); 338 if (err) { 339 xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n", 340 hwe->name, ERR_PTR(err), nop_q->guc->id); 341 goto put_nop_q; 342 } 343 344 /* Reload golden LRC to record the effect of any indirect W/A */ 345 err = emit_nop_job(gt, q); 346 if (err) { 347 xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n", 348 hwe->name, ERR_PTR(err), q->guc->id); 349 goto put_nop_q; 350 } 351 352 xe_map_memcpy_from(xe, default_lrc, 353 &q->lrc[0]->bo->vmap, 354 xe_lrc_pphwsp_offset(q->lrc[0]), 355 xe_gt_lrc_size(gt, hwe->class)); 356 357 gt->default_lrc[hwe->class] = default_lrc; 358 put_nop_q: 359 xe_exec_queue_put(nop_q); 360 put_exec_queue: 361 xe_exec_queue_put(q); 362 if (err) 363 break; 364 } 365 366 return err; 367 } 368 369 int xe_gt_init_early(struct xe_gt *gt) 370 { 371 int err; 372 373 if (IS_SRIOV_PF(gt_to_xe(gt))) { 374 err = xe_gt_sriov_pf_init_early(gt); 375 if (err) 376 return err; 377 } 378 379 xe_reg_sr_init(>->reg_sr, "GT", gt_to_xe(gt)); 380 381 err = xe_wa_init(gt); 382 if (err) 383 return err; 384 385 xe_wa_process_gt(gt); 386 xe_wa_process_oob(gt); 387 xe_tuning_process_gt(gt); 388 389 xe_force_wake_init_gt(gt, gt_to_fw(gt)); 390 xe_pcode_init(gt); 391 spin_lock_init(>->global_invl_lock); 392 393 return 0; 394 } 395 396 static void dump_pat_on_error(struct xe_gt *gt) 397 { 398 struct drm_printer p; 399 char prefix[32]; 400 401 snprintf(prefix, sizeof(prefix), "[GT%u Error]", gt->info.id); 402 p = drm_dbg_printer(>_to_xe(gt)->drm, DRM_UT_DRIVER, prefix); 403 404 xe_pat_dump(gt, &p); 405 } 406 407 static int gt_fw_domain_init(struct xe_gt *gt) 408 { 409 int err, i; 410 411 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 412 if (err) 413 goto err_hw_fence_irq; 414 415 if (!xe_gt_is_media_type(gt)) { 416 err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt); 417 if (err) 418 goto err_force_wake; 419 if (IS_SRIOV_PF(gt_to_xe(gt))) 420 xe_lmtt_init(>_to_tile(gt)->sriov.pf.lmtt); 421 } 422 423 /* Enable per hw engine IRQs */ 424 xe_irq_enable_hwe(gt); 425 426 /* Rerun MCR init as we now have hw engine list */ 427 xe_gt_mcr_init(gt); 428 429 err = xe_hw_engines_init_early(gt); 430 if (err) 431 goto err_force_wake; 432 433 err = xe_hw_engine_class_sysfs_init(gt); 434 if (err) 435 goto err_force_wake; 436 437 /* Initialize CCS mode sysfs after early initialization of HW engines */ 438 err = xe_gt_ccs_mode_sysfs_init(gt); 439 if (err) 440 goto err_force_wake; 441 442 /* 443 * Stash hardware-reported version. Since this register does not exist 444 * on pre-MTL platforms, reading it there will (correctly) return 0. 445 */ 446 gt->info.gmdid = xe_mmio_read32(gt, GMD_ID); 447 448 err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 449 XE_WARN_ON(err); 450 451 return 0; 452 453 err_force_wake: 454 dump_pat_on_error(gt); 455 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 456 err_hw_fence_irq: 457 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 458 xe_hw_fence_irq_finish(>->fence_irq[i]); 459 460 return err; 461 } 462 463 static int all_fw_domain_init(struct xe_gt *gt) 464 { 465 int err, i; 466 467 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 468 if (err) 469 goto err_hw_fence_irq; 470 471 xe_gt_mcr_set_implicit_defaults(gt); 472 xe_reg_sr_apply_mmio(>->reg_sr, gt); 473 474 err = xe_gt_clock_init(gt); 475 if (err) 476 goto err_force_wake; 477 478 xe_mocs_init(gt); 479 err = xe_execlist_init(gt); 480 if (err) 481 goto err_force_wake; 482 483 err = xe_hw_engines_init(gt); 484 if (err) 485 goto err_force_wake; 486 487 err = xe_uc_init_post_hwconfig(>->uc); 488 if (err) 489 goto err_force_wake; 490 491 if (!xe_gt_is_media_type(gt)) { 492 /* 493 * USM has its only SA pool to non-block behind user operations 494 */ 495 if (gt_to_xe(gt)->info.has_usm) { 496 struct xe_device *xe = gt_to_xe(gt); 497 498 gt->usm.bb_pool = xe_sa_bo_manager_init(gt_to_tile(gt), 499 IS_DGFX(xe) ? SZ_1M : SZ_512K, 16); 500 if (IS_ERR(gt->usm.bb_pool)) { 501 err = PTR_ERR(gt->usm.bb_pool); 502 goto err_force_wake; 503 } 504 } 505 } 506 507 if (!xe_gt_is_media_type(gt)) { 508 struct xe_tile *tile = gt_to_tile(gt); 509 510 tile->migrate = xe_migrate_init(tile); 511 if (IS_ERR(tile->migrate)) { 512 err = PTR_ERR(tile->migrate); 513 goto err_force_wake; 514 } 515 } 516 517 err = xe_uc_init_hw(>->uc); 518 if (err) 519 goto err_force_wake; 520 521 /* Configure default CCS mode of 1 engine with all resources */ 522 if (xe_gt_ccs_mode_enabled(gt)) { 523 gt->ccs_mode = 1; 524 xe_gt_apply_ccs_mode(gt); 525 } 526 527 if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt)) 528 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 529 530 if (IS_SRIOV_PF(gt_to_xe(gt))) 531 xe_gt_sriov_pf_init_hw(gt); 532 533 err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 534 XE_WARN_ON(err); 535 536 return 0; 537 538 err_force_wake: 539 xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 540 err_hw_fence_irq: 541 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) 542 xe_hw_fence_irq_finish(>->fence_irq[i]); 543 544 return err; 545 } 546 547 /* 548 * Initialize enough GT to be able to load GuC in order to obtain hwconfig and 549 * enable CTB communication. 550 */ 551 int xe_gt_init_hwconfig(struct xe_gt *gt) 552 { 553 int err; 554 555 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 556 if (err) 557 goto out; 558 559 xe_gt_mcr_init_early(gt); 560 xe_pat_init(gt); 561 xe_gt_enable_host_l2_vram(gt); 562 563 err = xe_uc_init(>->uc); 564 if (err) 565 goto out_fw; 566 567 err = xe_uc_init_hwconfig(>->uc); 568 if (err) 569 goto out_fw; 570 571 xe_gt_topology_init(gt); 572 xe_gt_mcr_init(gt); 573 574 out_fw: 575 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 576 out: 577 return err; 578 } 579 580 int xe_gt_init(struct xe_gt *gt) 581 { 582 int err; 583 int i; 584 585 INIT_WORK(>->reset.worker, gt_reset_worker); 586 587 for (i = 0; i < XE_ENGINE_CLASS_MAX; ++i) { 588 gt->ring_ops[i] = xe_ring_ops_get(gt, i); 589 xe_hw_fence_irq_init(>->fence_irq[i]); 590 } 591 592 err = xe_gt_tlb_invalidation_init(gt); 593 if (err) 594 return err; 595 596 err = xe_gt_pagefault_init(gt); 597 if (err) 598 return err; 599 600 xe_mocs_init_early(gt); 601 602 err = xe_gt_sysfs_init(gt); 603 if (err) 604 return err; 605 606 err = gt_fw_domain_init(gt); 607 if (err) 608 return err; 609 610 err = xe_gt_idle_init(>->gtidle); 611 if (err) 612 return err; 613 614 err = xe_gt_freq_init(gt); 615 if (err) 616 return err; 617 618 xe_force_wake_init_engines(gt, gt_to_fw(gt)); 619 620 err = all_fw_domain_init(gt); 621 if (err) 622 return err; 623 624 xe_gt_record_user_engines(gt); 625 626 return 0; 627 } 628 629 void xe_gt_record_user_engines(struct xe_gt *gt) 630 { 631 struct xe_hw_engine *hwe; 632 enum xe_hw_engine_id id; 633 634 gt->user_engines.mask = 0; 635 memset(gt->user_engines.instances_per_class, 0, 636 sizeof(gt->user_engines.instances_per_class)); 637 638 for_each_hw_engine(hwe, gt, id) { 639 if (xe_hw_engine_is_reserved(hwe)) 640 continue; 641 642 gt->user_engines.mask |= BIT_ULL(id); 643 gt->user_engines.instances_per_class[hwe->class]++; 644 } 645 646 xe_gt_assert(gt, (gt->user_engines.mask | gt->info.engine_mask) 647 == gt->info.engine_mask); 648 } 649 650 static int do_gt_reset(struct xe_gt *gt) 651 { 652 int err; 653 654 xe_gsc_wa_14015076503(gt, true); 655 656 xe_mmio_write32(gt, GDRST, GRDOM_FULL); 657 err = xe_mmio_wait32(gt, GDRST, GRDOM_FULL, 0, 5000, NULL, false); 658 if (err) 659 xe_gt_err(gt, "failed to clear GRDOM_FULL (%pe)\n", 660 ERR_PTR(err)); 661 662 xe_gsc_wa_14015076503(gt, false); 663 664 return err; 665 } 666 667 static int vf_gt_restart(struct xe_gt *gt) 668 { 669 int err; 670 671 err = xe_uc_sanitize_reset(>->uc); 672 if (err) 673 return err; 674 675 err = xe_uc_init_hw(>->uc); 676 if (err) 677 return err; 678 679 err = xe_uc_start(>->uc); 680 if (err) 681 return err; 682 683 return 0; 684 } 685 686 static int do_gt_restart(struct xe_gt *gt) 687 { 688 struct xe_hw_engine *hwe; 689 enum xe_hw_engine_id id; 690 int err; 691 692 if (IS_SRIOV_VF(gt_to_xe(gt))) 693 return vf_gt_restart(gt); 694 695 xe_pat_init(gt); 696 697 xe_gt_enable_host_l2_vram(gt); 698 699 xe_gt_mcr_set_implicit_defaults(gt); 700 xe_reg_sr_apply_mmio(>->reg_sr, gt); 701 702 err = xe_wopcm_init(>->uc.wopcm); 703 if (err) 704 return err; 705 706 for_each_hw_engine(hwe, gt, id) 707 xe_hw_engine_enable_ring(hwe); 708 709 err = xe_uc_sanitize_reset(>->uc); 710 if (err) 711 return err; 712 713 err = xe_uc_init_hw(>->uc); 714 if (err) 715 return err; 716 717 if (IS_SRIOV_PF(gt_to_xe(gt)) && !xe_gt_is_media_type(gt)) 718 xe_lmtt_init_hw(>_to_tile(gt)->sriov.pf.lmtt); 719 720 if (IS_SRIOV_PF(gt_to_xe(gt))) 721 xe_gt_sriov_pf_init_hw(gt); 722 723 xe_mocs_init(gt); 724 err = xe_uc_start(>->uc); 725 if (err) 726 return err; 727 728 for_each_hw_engine(hwe, gt, id) { 729 xe_reg_sr_apply_mmio(&hwe->reg_sr, gt); 730 xe_reg_sr_apply_whitelist(hwe); 731 } 732 733 /* Get CCS mode in sync between sw/hw */ 734 xe_gt_apply_ccs_mode(gt); 735 736 /* Restore GT freq to expected values */ 737 xe_gt_sanitize_freq(gt); 738 739 if (IS_SRIOV_PF(gt_to_xe(gt))) 740 xe_gt_sriov_pf_restart(gt); 741 742 return 0; 743 } 744 745 static int gt_reset(struct xe_gt *gt) 746 { 747 int err; 748 749 if (xe_device_wedged(gt_to_xe(gt))) 750 return -ECANCELED; 751 752 /* We only support GT resets with GuC submission */ 753 if (!xe_device_uc_enabled(gt_to_xe(gt))) 754 return -ENODEV; 755 756 xe_gt_info(gt, "reset started\n"); 757 758 if (xe_fault_inject_gt_reset()) { 759 err = -ECANCELED; 760 goto err_fail; 761 } 762 763 xe_pm_runtime_get(gt_to_xe(gt)); 764 xe_gt_sanitize(gt); 765 766 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 767 if (err) 768 goto err_msg; 769 770 xe_uc_gucrc_disable(>->uc); 771 xe_uc_stop_prepare(>->uc); 772 xe_gt_pagefault_reset(gt); 773 774 xe_uc_stop(>->uc); 775 776 xe_gt_tlb_invalidation_reset(gt); 777 778 err = do_gt_reset(gt); 779 if (err) 780 goto err_out; 781 782 err = do_gt_restart(gt); 783 if (err) 784 goto err_out; 785 786 err = xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 787 XE_WARN_ON(err); 788 xe_pm_runtime_put(gt_to_xe(gt)); 789 790 xe_gt_info(gt, "reset done\n"); 791 792 return 0; 793 794 err_out: 795 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 796 err_msg: 797 XE_WARN_ON(xe_uc_start(>->uc)); 798 xe_pm_runtime_put(gt_to_xe(gt)); 799 err_fail: 800 xe_gt_err(gt, "reset failed (%pe)\n", ERR_PTR(err)); 801 802 xe_device_declare_wedged(gt_to_xe(gt)); 803 804 return err; 805 } 806 807 static void gt_reset_worker(struct work_struct *w) 808 { 809 struct xe_gt *gt = container_of(w, typeof(*gt), reset.worker); 810 811 gt_reset(gt); 812 } 813 814 void xe_gt_reset_async(struct xe_gt *gt) 815 { 816 xe_gt_info(gt, "trying reset\n"); 817 818 /* Don't do a reset while one is already in flight */ 819 if (!xe_fault_inject_gt_reset() && xe_uc_reset_prepare(>->uc)) 820 return; 821 822 xe_gt_info(gt, "reset queued\n"); 823 queue_work(gt->ordered_wq, >->reset.worker); 824 } 825 826 void xe_gt_suspend_prepare(struct xe_gt *gt) 827 { 828 XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 829 830 xe_uc_stop_prepare(>->uc); 831 832 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 833 } 834 835 int xe_gt_suspend(struct xe_gt *gt) 836 { 837 int err; 838 839 xe_gt_dbg(gt, "suspending\n"); 840 xe_gt_sanitize(gt); 841 842 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 843 if (err) 844 goto err_msg; 845 846 err = xe_uc_suspend(>->uc); 847 if (err) 848 goto err_force_wake; 849 850 xe_gt_idle_disable_pg(gt); 851 852 xe_gt_disable_host_l2_vram(gt); 853 854 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 855 xe_gt_dbg(gt, "suspended\n"); 856 857 return 0; 858 859 err_force_wake: 860 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 861 err_msg: 862 xe_gt_err(gt, "suspend failed (%pe)\n", ERR_PTR(err)); 863 864 return err; 865 } 866 867 /** 868 * xe_gt_sanitize_freq() - Restore saved frequencies if necessary. 869 * @gt: the GT object 870 * 871 * Called after driver init/GSC load completes to restore GT frequencies if we 872 * limited them for any WAs. 873 */ 874 int xe_gt_sanitize_freq(struct xe_gt *gt) 875 { 876 int ret = 0; 877 878 if ((!xe_uc_fw_is_available(>->uc.gsc.fw) || 879 xe_uc_fw_is_loaded(>->uc.gsc.fw)) && XE_WA(gt, 22019338487)) 880 ret = xe_guc_pc_restore_stashed_freq(>->uc.guc.pc); 881 882 return ret; 883 } 884 885 int xe_gt_resume(struct xe_gt *gt) 886 { 887 int err; 888 889 xe_gt_dbg(gt, "resuming\n"); 890 err = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 891 if (err) 892 goto err_msg; 893 894 err = do_gt_restart(gt); 895 if (err) 896 goto err_force_wake; 897 898 xe_gt_idle_enable_pg(gt); 899 900 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 901 xe_gt_dbg(gt, "resumed\n"); 902 903 return 0; 904 905 err_force_wake: 906 XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 907 err_msg: 908 xe_gt_err(gt, "resume failed (%pe)\n", ERR_PTR(err)); 909 910 return err; 911 } 912 913 struct xe_hw_engine *xe_gt_hw_engine(struct xe_gt *gt, 914 enum xe_engine_class class, 915 u16 instance, bool logical) 916 { 917 struct xe_hw_engine *hwe; 918 enum xe_hw_engine_id id; 919 920 for_each_hw_engine(hwe, gt, id) 921 if (hwe->class == class && 922 ((!logical && hwe->instance == instance) || 923 (logical && hwe->logical_instance == instance))) 924 return hwe; 925 926 return NULL; 927 } 928 929 struct xe_hw_engine *xe_gt_any_hw_engine_by_reset_domain(struct xe_gt *gt, 930 enum xe_engine_class class) 931 { 932 struct xe_hw_engine *hwe; 933 enum xe_hw_engine_id id; 934 935 for_each_hw_engine(hwe, gt, id) { 936 switch (class) { 937 case XE_ENGINE_CLASS_RENDER: 938 case XE_ENGINE_CLASS_COMPUTE: 939 if (hwe->class == XE_ENGINE_CLASS_RENDER || 940 hwe->class == XE_ENGINE_CLASS_COMPUTE) 941 return hwe; 942 break; 943 default: 944 if (hwe->class == class) 945 return hwe; 946 } 947 } 948 949 return NULL; 950 } 951 952 struct xe_hw_engine *xe_gt_any_hw_engine(struct xe_gt *gt) 953 { 954 struct xe_hw_engine *hwe; 955 enum xe_hw_engine_id id; 956 957 for_each_hw_engine(hwe, gt, id) 958 return hwe; 959 960 return NULL; 961 } 962 963 /** 964 * xe_gt_declare_wedged() - Declare GT wedged 965 * @gt: the GT object 966 * 967 * Wedge the GT which stops all submission, saves desired debug state, and 968 * cleans up anything which could timeout. 969 */ 970 void xe_gt_declare_wedged(struct xe_gt *gt) 971 { 972 xe_gt_assert(gt, gt_to_xe(gt)->wedged.mode); 973 974 xe_uc_declare_wedged(>->uc); 975 xe_gt_tlb_invalidation_reset(gt); 976 } 977