1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #include <linux/device.h> 7 #include <linux/kobject.h> 8 #include <linux/pci.h> 9 #include <linux/sysfs.h> 10 11 #include "xe_device.h" 12 #include "xe_device_sysfs.h" 13 #include "xe_mmio.h" 14 #include "xe_pcode_api.h" 15 #include "xe_pcode.h" 16 #include "xe_pm.h" 17 18 /** 19 * DOC: Xe device sysfs 20 * Xe driver requires exposing certain tunable knobs controlled by user space for 21 * each graphics device. Considering this, we need to add sysfs attributes at device 22 * level granularity. 23 * These sysfs attributes will be available under pci device kobj directory. 24 * 25 * vram_d3cold_threshold - Report/change vram used threshold(in MB) below 26 * which vram save/restore is permissible during runtime D3cold entry/exit. 27 * 28 * lb_fan_control_version - Fan control version provisioned by late binding. 29 * Exposed only if supported by the device. 30 * 31 * lb_voltage_regulator_version - Voltage regulator version provisioned by late 32 * binding. Exposed only if supported by the device. 33 */ 34 35 static ssize_t 36 vram_d3cold_threshold_show(struct device *dev, 37 struct device_attribute *attr, char *buf) 38 { 39 struct pci_dev *pdev = to_pci_dev(dev); 40 struct xe_device *xe = pdev_to_xe_device(pdev); 41 42 return sysfs_emit(buf, "%d\n", xe->d3cold.vram_threshold); 43 } 44 45 static ssize_t 46 vram_d3cold_threshold_store(struct device *dev, struct device_attribute *attr, 47 const char *buff, size_t count) 48 { 49 struct pci_dev *pdev = to_pci_dev(dev); 50 struct xe_device *xe = pdev_to_xe_device(pdev); 51 u32 vram_d3cold_threshold; 52 int ret; 53 54 ret = kstrtou32(buff, 0, &vram_d3cold_threshold); 55 if (ret) 56 return ret; 57 58 drm_dbg(&xe->drm, "vram_d3cold_threshold: %u\n", vram_d3cold_threshold); 59 60 guard(xe_pm_runtime)(xe); 61 ret = xe_pm_set_vram_threshold(xe, vram_d3cold_threshold); 62 63 return ret ?: count; 64 } 65 66 static DEVICE_ATTR_RW(vram_d3cold_threshold); 67 68 static struct attribute *vram_attrs[] = { 69 &dev_attr_vram_d3cold_threshold.attr, 70 NULL 71 }; 72 73 static const struct attribute_group vram_attr_group = { 74 .attrs = vram_attrs, 75 }; 76 77 static ssize_t 78 lb_fan_control_version_show(struct device *dev, struct device_attribute *attr, char *buf) 79 { 80 struct xe_device *xe = pdev_to_xe_device(to_pci_dev(dev)); 81 struct xe_tile *root = xe_device_get_root_tile(xe); 82 u32 cap = 0, ver_low = FAN_TABLE, ver_high = FAN_TABLE; 83 u16 major = 0, minor = 0, hotfix = 0, build = 0; 84 int ret; 85 86 guard(xe_pm_runtime)(xe); 87 88 ret = xe_pcode_read(root, PCODE_MBOX(PCODE_LATE_BINDING, GET_CAPABILITY_STATUS, 0), 89 &cap, NULL); 90 if (ret) 91 return ret; 92 93 if (REG_FIELD_GET(V1_FAN_PROVISIONED, cap)) { 94 ret = xe_pcode_read(root, PCODE_MBOX(PCODE_LATE_BINDING, GET_VERSION_LOW, 0), 95 &ver_low, NULL); 96 if (ret) 97 return ret; 98 99 ret = xe_pcode_read(root, PCODE_MBOX(PCODE_LATE_BINDING, GET_VERSION_HIGH, 0), 100 &ver_high, NULL); 101 if (ret) 102 return ret; 103 104 major = REG_FIELD_GET(MAJOR_VERSION_MASK, ver_low); 105 minor = REG_FIELD_GET(MINOR_VERSION_MASK, ver_low); 106 hotfix = REG_FIELD_GET(HOTFIX_VERSION_MASK, ver_high); 107 build = REG_FIELD_GET(BUILD_VERSION_MASK, ver_high); 108 } 109 110 return sysfs_emit(buf, "%u.%u.%u.%u\n", major, minor, hotfix, build); 111 } 112 static DEVICE_ATTR_ADMIN_RO(lb_fan_control_version); 113 114 static ssize_t 115 lb_voltage_regulator_version_show(struct device *dev, struct device_attribute *attr, char *buf) 116 { 117 struct xe_device *xe = pdev_to_xe_device(to_pci_dev(dev)); 118 struct xe_tile *root = xe_device_get_root_tile(xe); 119 u32 cap = 0, ver_low = VR_CONFIG, ver_high = VR_CONFIG; 120 u16 major = 0, minor = 0, hotfix = 0, build = 0; 121 int ret; 122 123 guard(xe_pm_runtime)(xe); 124 125 ret = xe_pcode_read(root, PCODE_MBOX(PCODE_LATE_BINDING, GET_CAPABILITY_STATUS, 0), 126 &cap, NULL); 127 if (ret) 128 return ret; 129 130 if (REG_FIELD_GET(VR_PARAMS_PROVISIONED, cap)) { 131 ret = xe_pcode_read(root, PCODE_MBOX(PCODE_LATE_BINDING, GET_VERSION_LOW, 0), 132 &ver_low, NULL); 133 if (ret) 134 return ret; 135 136 ret = xe_pcode_read(root, PCODE_MBOX(PCODE_LATE_BINDING, GET_VERSION_HIGH, 0), 137 &ver_high, NULL); 138 if (ret) 139 return ret; 140 141 major = REG_FIELD_GET(MAJOR_VERSION_MASK, ver_low); 142 minor = REG_FIELD_GET(MINOR_VERSION_MASK, ver_low); 143 hotfix = REG_FIELD_GET(HOTFIX_VERSION_MASK, ver_high); 144 build = REG_FIELD_GET(BUILD_VERSION_MASK, ver_high); 145 } 146 147 return sysfs_emit(buf, "%u.%u.%u.%u\n", major, minor, hotfix, build); 148 } 149 static DEVICE_ATTR_ADMIN_RO(lb_voltage_regulator_version); 150 151 static struct attribute *late_bind_attrs[] = { 152 &dev_attr_lb_fan_control_version.attr, 153 &dev_attr_lb_voltage_regulator_version.attr, 154 NULL 155 }; 156 157 static umode_t late_bind_attr_is_visible(struct kobject *kobj, 158 struct attribute *attr, int n) 159 { 160 struct device *dev = kobj_to_dev(kobj); 161 struct xe_device *xe = pdev_to_xe_device(to_pci_dev(dev)); 162 struct xe_tile *root = xe_device_get_root_tile(xe); 163 u32 cap = 0; 164 int ret; 165 166 ret = xe_pcode_read(root, PCODE_MBOX(PCODE_LATE_BINDING, GET_CAPABILITY_STATUS, 0), 167 &cap, NULL); 168 if (ret) 169 return 0; 170 171 if (attr == &dev_attr_lb_fan_control_version.attr && 172 REG_FIELD_GET(V1_FAN_SUPPORTED, cap)) 173 return attr->mode; 174 if (attr == &dev_attr_lb_voltage_regulator_version.attr && 175 REG_FIELD_GET(VR_PARAMS_SUPPORTED, cap)) 176 return attr->mode; 177 178 return 0; 179 } 180 181 static const struct attribute_group late_bind_attr_group = { 182 .attrs = late_bind_attrs, 183 .is_visible = late_bind_attr_is_visible, 184 }; 185 186 /** 187 * DOC: PCIe Gen5 Limitations 188 * 189 * Default link speed of discrete GPUs is determined by configuration parameters 190 * stored in their flash memory, which are subject to override through user 191 * initiated firmware updates. It has been observed that devices configured with 192 * PCIe Gen5 as their default link speed can come across link quality issues due 193 * to host or motherboard limitations and may have to auto-downgrade their link 194 * to PCIe Gen4 speed when faced with unstable link at Gen5, which makes 195 * firmware updates rather risky on such setups. It is required to ensure that 196 * the device is capable of auto-downgrading its link to PCIe Gen4 speed before 197 * pushing the firmware image with PCIe Gen5 as default configuration. This can 198 * be done by reading ``auto_link_downgrade_capable`` sysfs entry, which will 199 * denote if the device is capable of auto-downgrading its link to PCIe Gen4 200 * speed with boolean output value of ``0`` or ``1``, meaning `incapable` or 201 * `capable` respectively. 202 * 203 * .. code-block:: shell 204 * 205 * $ cat /sys/bus/pci/devices/<bdf>/auto_link_downgrade_capable 206 * 207 * Pushing the firmware image with PCIe Gen5 as default configuration on a auto 208 * link downgrade incapable device and facing link instability due to host or 209 * motherboard limitations can result in driver failing to bind to the device, 210 * making further firmware updates impossible with RMA being the only last 211 * resort. 212 * 213 * Link downgrade status of auto link downgrade capable devices is available 214 * through ``auto_link_downgrade_status`` sysfs entry with boolean output value 215 * of ``0`` or ``1``, where ``0`` means no auto-downgrading was required during 216 * link training (which is the optimal scenario) and ``1`` means the device has 217 * auto-downgraded its link to PCIe Gen4 speed due to unstable Gen5 link. 218 * 219 * .. code-block:: shell 220 * 221 * $ cat /sys/bus/pci/devices/<bdf>/auto_link_downgrade_status 222 */ 223 224 static ssize_t 225 auto_link_downgrade_capable_show(struct device *dev, struct device_attribute *attr, char *buf) 226 { 227 struct pci_dev *pdev = to_pci_dev(dev); 228 struct xe_device *xe = pdev_to_xe_device(pdev); 229 u32 cap, val; 230 231 guard(xe_pm_runtime)(xe); 232 val = xe_mmio_read32(xe_root_tile_mmio(xe), BMG_PCIE_CAP); 233 234 cap = REG_FIELD_GET(LINK_DOWNGRADE, val); 235 return sysfs_emit(buf, "%u\n", cap == DOWNGRADE_CAPABLE); 236 } 237 static DEVICE_ATTR_ADMIN_RO(auto_link_downgrade_capable); 238 239 static ssize_t 240 auto_link_downgrade_status_show(struct device *dev, struct device_attribute *attr, char *buf) 241 { 242 struct pci_dev *pdev = to_pci_dev(dev); 243 struct xe_device *xe = pdev_to_xe_device(pdev); 244 /* default the auto_link_downgrade status to 0 */ 245 u32 val = 0; 246 int ret; 247 248 guard(xe_pm_runtime)(xe); 249 ret = xe_pcode_read(xe_device_get_root_tile(xe), 250 PCODE_MBOX(DGFX_PCODE_STATUS, DGFX_GET_INIT_STATUS, 0), 251 &val, NULL); 252 253 return ret ?: sysfs_emit(buf, "%u\n", REG_FIELD_GET(DGFX_LINK_DOWNGRADE_STATUS, val)); 254 } 255 static DEVICE_ATTR_ADMIN_RO(auto_link_downgrade_status); 256 257 static struct attribute *auto_link_downgrade_attrs[] = { 258 &dev_attr_auto_link_downgrade_capable.attr, 259 &dev_attr_auto_link_downgrade_status.attr, 260 NULL 261 }; 262 263 static const struct attribute_group auto_link_downgrade_attr_group = { 264 .attrs = auto_link_downgrade_attrs, 265 }; 266 267 int xe_device_sysfs_init(struct xe_device *xe) 268 { 269 struct device *dev = xe->drm.dev; 270 int ret; 271 272 if (xe->d3cold.capable) { 273 ret = devm_device_add_group(dev, &vram_attr_group); 274 if (ret) 275 return ret; 276 } 277 278 if (xe->info.platform == XE_BATTLEMAGE && !IS_SRIOV_VF(xe)) { 279 ret = devm_device_add_group(dev, &auto_link_downgrade_attr_group); 280 if (ret) 281 return ret; 282 283 ret = devm_device_add_group(dev, &late_bind_attr_group); 284 if (ret) 285 return ret; 286 } 287 288 return 0; 289 } 290