1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_device.h" 7 8 #include <linux/aperture.h> 9 #include <linux/delay.h> 10 #include <linux/fault-inject.h> 11 #include <linux/units.h> 12 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_client.h> 15 #include <drm/drm_gem_ttm_helper.h> 16 #include <drm/drm_ioctl.h> 17 #include <drm/drm_managed.h> 18 #include <drm/drm_print.h> 19 #include <uapi/drm/xe_drm.h> 20 21 #include "display/xe_display.h" 22 #include "instructions/xe_gpu_commands.h" 23 #include "regs/xe_gt_regs.h" 24 #include "regs/xe_regs.h" 25 #include "xe_bo.h" 26 #include "xe_bo_evict.h" 27 #include "xe_debugfs.h" 28 #include "xe_devcoredump.h" 29 #include "xe_device_sysfs.h" 30 #include "xe_dma_buf.h" 31 #include "xe_drm_client.h" 32 #include "xe_drv.h" 33 #include "xe_exec.h" 34 #include "xe_exec_queue.h" 35 #include "xe_force_wake.h" 36 #include "xe_ggtt.h" 37 #include "xe_gsc_proxy.h" 38 #include "xe_gt.h" 39 #include "xe_gt_mcr.h" 40 #include "xe_gt_printk.h" 41 #include "xe_gt_sriov_vf.h" 42 #include "xe_guc.h" 43 #include "xe_hw_engine_group.h" 44 #include "xe_hwmon.h" 45 #include "xe_irq.h" 46 #include "xe_memirq.h" 47 #include "xe_mmio.h" 48 #include "xe_module.h" 49 #include "xe_oa.h" 50 #include "xe_observation.h" 51 #include "xe_pat.h" 52 #include "xe_pcode.h" 53 #include "xe_pm.h" 54 #include "xe_pmu.h" 55 #include "xe_pxp.h" 56 #include "xe_query.h" 57 #include "xe_shrinker.h" 58 #include "xe_survivability_mode.h" 59 #include "xe_sriov.h" 60 #include "xe_tile.h" 61 #include "xe_ttm_stolen_mgr.h" 62 #include "xe_ttm_sys_mgr.h" 63 #include "xe_vm.h" 64 #include "xe_vram.h" 65 #include "xe_vsec.h" 66 #include "xe_wait_user_fence.h" 67 #include "xe_wa.h" 68 69 #include <generated/xe_wa_oob.h> 70 71 static int xe_file_open(struct drm_device *dev, struct drm_file *file) 72 { 73 struct xe_device *xe = to_xe_device(dev); 74 struct xe_drm_client *client; 75 struct xe_file *xef; 76 int ret = -ENOMEM; 77 struct task_struct *task = NULL; 78 79 xef = kzalloc(sizeof(*xef), GFP_KERNEL); 80 if (!xef) 81 return ret; 82 83 client = xe_drm_client_alloc(); 84 if (!client) { 85 kfree(xef); 86 return ret; 87 } 88 89 xef->drm = file; 90 xef->client = client; 91 xef->xe = xe; 92 93 mutex_init(&xef->vm.lock); 94 xa_init_flags(&xef->vm.xa, XA_FLAGS_ALLOC1); 95 96 mutex_init(&xef->exec_queue.lock); 97 xa_init_flags(&xef->exec_queue.xa, XA_FLAGS_ALLOC1); 98 99 file->driver_priv = xef; 100 kref_init(&xef->refcount); 101 102 task = get_pid_task(rcu_access_pointer(file->pid), PIDTYPE_PID); 103 if (task) { 104 xef->process_name = kstrdup(task->comm, GFP_KERNEL); 105 xef->pid = task->pid; 106 put_task_struct(task); 107 } 108 109 return 0; 110 } 111 112 static void xe_file_destroy(struct kref *ref) 113 { 114 struct xe_file *xef = container_of(ref, struct xe_file, refcount); 115 116 xa_destroy(&xef->exec_queue.xa); 117 mutex_destroy(&xef->exec_queue.lock); 118 xa_destroy(&xef->vm.xa); 119 mutex_destroy(&xef->vm.lock); 120 121 xe_drm_client_put(xef->client); 122 kfree(xef->process_name); 123 kfree(xef); 124 } 125 126 /** 127 * xe_file_get() - Take a reference to the xe file object 128 * @xef: Pointer to the xe file 129 * 130 * Anyone with a pointer to xef must take a reference to the xe file 131 * object using this call. 132 * 133 * Return: xe file pointer 134 */ 135 struct xe_file *xe_file_get(struct xe_file *xef) 136 { 137 kref_get(&xef->refcount); 138 return xef; 139 } 140 141 /** 142 * xe_file_put() - Drop a reference to the xe file object 143 * @xef: Pointer to the xe file 144 * 145 * Used to drop reference to the xef object 146 */ 147 void xe_file_put(struct xe_file *xef) 148 { 149 kref_put(&xef->refcount, xe_file_destroy); 150 } 151 152 static void xe_file_close(struct drm_device *dev, struct drm_file *file) 153 { 154 struct xe_device *xe = to_xe_device(dev); 155 struct xe_file *xef = file->driver_priv; 156 struct xe_vm *vm; 157 struct xe_exec_queue *q; 158 unsigned long idx; 159 160 xe_pm_runtime_get(xe); 161 162 /* 163 * No need for exec_queue.lock here as there is no contention for it 164 * when FD is closing as IOCTLs presumably can't be modifying the 165 * xarray. Taking exec_queue.lock here causes undue dependency on 166 * vm->lock taken during xe_exec_queue_kill(). 167 */ 168 xa_for_each(&xef->exec_queue.xa, idx, q) { 169 if (q->vm && q->hwe->hw_engine_group) 170 xe_hw_engine_group_del_exec_queue(q->hwe->hw_engine_group, q); 171 xe_exec_queue_kill(q); 172 xe_exec_queue_put(q); 173 } 174 xa_for_each(&xef->vm.xa, idx, vm) 175 xe_vm_close_and_put(vm); 176 177 xe_file_put(xef); 178 179 xe_pm_runtime_put(xe); 180 } 181 182 static const struct drm_ioctl_desc xe_ioctls[] = { 183 DRM_IOCTL_DEF_DRV(XE_DEVICE_QUERY, xe_query_ioctl, DRM_RENDER_ALLOW), 184 DRM_IOCTL_DEF_DRV(XE_GEM_CREATE, xe_gem_create_ioctl, DRM_RENDER_ALLOW), 185 DRM_IOCTL_DEF_DRV(XE_GEM_MMAP_OFFSET, xe_gem_mmap_offset_ioctl, 186 DRM_RENDER_ALLOW), 187 DRM_IOCTL_DEF_DRV(XE_VM_CREATE, xe_vm_create_ioctl, DRM_RENDER_ALLOW), 188 DRM_IOCTL_DEF_DRV(XE_VM_DESTROY, xe_vm_destroy_ioctl, DRM_RENDER_ALLOW), 189 DRM_IOCTL_DEF_DRV(XE_VM_BIND, xe_vm_bind_ioctl, DRM_RENDER_ALLOW), 190 DRM_IOCTL_DEF_DRV(XE_EXEC, xe_exec_ioctl, DRM_RENDER_ALLOW), 191 DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_CREATE, xe_exec_queue_create_ioctl, 192 DRM_RENDER_ALLOW), 193 DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_DESTROY, xe_exec_queue_destroy_ioctl, 194 DRM_RENDER_ALLOW), 195 DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_GET_PROPERTY, xe_exec_queue_get_property_ioctl, 196 DRM_RENDER_ALLOW), 197 DRM_IOCTL_DEF_DRV(XE_WAIT_USER_FENCE, xe_wait_user_fence_ioctl, 198 DRM_RENDER_ALLOW), 199 DRM_IOCTL_DEF_DRV(XE_OBSERVATION, xe_observation_ioctl, DRM_RENDER_ALLOW), 200 }; 201 202 static long xe_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 203 { 204 struct drm_file *file_priv = file->private_data; 205 struct xe_device *xe = to_xe_device(file_priv->minor->dev); 206 long ret; 207 208 if (xe_device_wedged(xe)) 209 return -ECANCELED; 210 211 ret = xe_pm_runtime_get_ioctl(xe); 212 if (ret >= 0) 213 ret = drm_ioctl(file, cmd, arg); 214 xe_pm_runtime_put(xe); 215 216 return ret; 217 } 218 219 #ifdef CONFIG_COMPAT 220 static long xe_drm_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 221 { 222 struct drm_file *file_priv = file->private_data; 223 struct xe_device *xe = to_xe_device(file_priv->minor->dev); 224 long ret; 225 226 if (xe_device_wedged(xe)) 227 return -ECANCELED; 228 229 ret = xe_pm_runtime_get_ioctl(xe); 230 if (ret >= 0) 231 ret = drm_compat_ioctl(file, cmd, arg); 232 xe_pm_runtime_put(xe); 233 234 return ret; 235 } 236 #else 237 /* similarly to drm_compat_ioctl, let's it be assigned to .compat_ioct unconditionally */ 238 #define xe_drm_compat_ioctl NULL 239 #endif 240 241 static void barrier_open(struct vm_area_struct *vma) 242 { 243 drm_dev_get(vma->vm_private_data); 244 } 245 246 static void barrier_close(struct vm_area_struct *vma) 247 { 248 drm_dev_put(vma->vm_private_data); 249 } 250 251 static void barrier_release_dummy_page(struct drm_device *dev, void *res) 252 { 253 struct page *dummy_page = (struct page *)res; 254 255 __free_page(dummy_page); 256 } 257 258 static vm_fault_t barrier_fault(struct vm_fault *vmf) 259 { 260 struct drm_device *dev = vmf->vma->vm_private_data; 261 struct vm_area_struct *vma = vmf->vma; 262 vm_fault_t ret = VM_FAULT_NOPAGE; 263 pgprot_t prot; 264 int idx; 265 266 prot = vm_get_page_prot(vma->vm_flags); 267 268 if (drm_dev_enter(dev, &idx)) { 269 unsigned long pfn; 270 271 #define LAST_DB_PAGE_OFFSET 0x7ff001 272 pfn = PHYS_PFN(pci_resource_start(to_pci_dev(dev->dev), 0) + 273 LAST_DB_PAGE_OFFSET); 274 ret = vmf_insert_pfn_prot(vma, vma->vm_start, pfn, 275 pgprot_noncached(prot)); 276 drm_dev_exit(idx); 277 } else { 278 struct page *page; 279 280 /* Allocate new dummy page to map all the VA range in this VMA to it*/ 281 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 282 if (!page) 283 return VM_FAULT_OOM; 284 285 /* Set the page to be freed using drmm release action */ 286 if (drmm_add_action_or_reset(dev, barrier_release_dummy_page, page)) 287 return VM_FAULT_OOM; 288 289 ret = vmf_insert_pfn_prot(vma, vma->vm_start, page_to_pfn(page), 290 prot); 291 } 292 293 return ret; 294 } 295 296 static const struct vm_operations_struct vm_ops_barrier = { 297 .open = barrier_open, 298 .close = barrier_close, 299 .fault = barrier_fault, 300 }; 301 302 static int xe_pci_barrier_mmap(struct file *filp, 303 struct vm_area_struct *vma) 304 { 305 struct drm_file *priv = filp->private_data; 306 struct drm_device *dev = priv->minor->dev; 307 struct xe_device *xe = to_xe_device(dev); 308 309 if (!IS_DGFX(xe)) 310 return -EINVAL; 311 312 if (vma->vm_end - vma->vm_start > SZ_4K) 313 return -EINVAL; 314 315 if (is_cow_mapping(vma->vm_flags)) 316 return -EINVAL; 317 318 if (vma->vm_flags & (VM_READ | VM_EXEC)) 319 return -EINVAL; 320 321 vm_flags_clear(vma, VM_MAYREAD | VM_MAYEXEC); 322 vm_flags_set(vma, VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | VM_IO); 323 vma->vm_ops = &vm_ops_barrier; 324 vma->vm_private_data = dev; 325 drm_dev_get(vma->vm_private_data); 326 327 return 0; 328 } 329 330 static int xe_mmap(struct file *filp, struct vm_area_struct *vma) 331 { 332 struct drm_file *priv = filp->private_data; 333 struct drm_device *dev = priv->minor->dev; 334 335 if (drm_dev_is_unplugged(dev)) 336 return -ENODEV; 337 338 switch (vma->vm_pgoff) { 339 case XE_PCI_BARRIER_MMAP_OFFSET >> XE_PTE_SHIFT: 340 return xe_pci_barrier_mmap(filp, vma); 341 } 342 343 return drm_gem_mmap(filp, vma); 344 } 345 346 static const struct file_operations xe_driver_fops = { 347 .owner = THIS_MODULE, 348 .open = drm_open, 349 .release = drm_release_noglobal, 350 .unlocked_ioctl = xe_drm_ioctl, 351 .mmap = xe_mmap, 352 .poll = drm_poll, 353 .read = drm_read, 354 .compat_ioctl = xe_drm_compat_ioctl, 355 .llseek = noop_llseek, 356 #ifdef CONFIG_PROC_FS 357 .show_fdinfo = drm_show_fdinfo, 358 #endif 359 .fop_flags = FOP_UNSIGNED_OFFSET, 360 }; 361 362 static struct drm_driver driver = { 363 /* Don't use MTRRs here; the Xserver or userspace app should 364 * deal with them for Intel hardware. 365 */ 366 .driver_features = 367 DRIVER_GEM | 368 DRIVER_RENDER | DRIVER_SYNCOBJ | 369 DRIVER_SYNCOBJ_TIMELINE | DRIVER_GEM_GPUVA, 370 .open = xe_file_open, 371 .postclose = xe_file_close, 372 373 .gem_prime_import = xe_gem_prime_import, 374 375 .dumb_create = xe_bo_dumb_create, 376 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 377 #ifdef CONFIG_PROC_FS 378 .show_fdinfo = xe_drm_client_fdinfo, 379 #endif 380 .ioctls = xe_ioctls, 381 .num_ioctls = ARRAY_SIZE(xe_ioctls), 382 .fops = &xe_driver_fops, 383 .name = DRIVER_NAME, 384 .desc = DRIVER_DESC, 385 .major = DRIVER_MAJOR, 386 .minor = DRIVER_MINOR, 387 .patchlevel = DRIVER_PATCHLEVEL, 388 }; 389 390 static void xe_device_destroy(struct drm_device *dev, void *dummy) 391 { 392 struct xe_device *xe = to_xe_device(dev); 393 394 xe_bo_dev_fini(&xe->bo_device); 395 396 if (xe->preempt_fence_wq) 397 destroy_workqueue(xe->preempt_fence_wq); 398 399 if (xe->ordered_wq) 400 destroy_workqueue(xe->ordered_wq); 401 402 if (xe->unordered_wq) 403 destroy_workqueue(xe->unordered_wq); 404 405 if (xe->destroy_wq) 406 destroy_workqueue(xe->destroy_wq); 407 408 ttm_device_fini(&xe->ttm); 409 } 410 411 struct xe_device *xe_device_create(struct pci_dev *pdev, 412 const struct pci_device_id *ent) 413 { 414 struct xe_device *xe; 415 int err; 416 417 xe_display_driver_set_hooks(&driver); 418 419 err = aperture_remove_conflicting_pci_devices(pdev, driver.name); 420 if (err) 421 return ERR_PTR(err); 422 423 xe = devm_drm_dev_alloc(&pdev->dev, &driver, struct xe_device, drm); 424 if (IS_ERR(xe)) 425 return xe; 426 427 err = ttm_device_init(&xe->ttm, &xe_ttm_funcs, xe->drm.dev, 428 xe->drm.anon_inode->i_mapping, 429 xe->drm.vma_offset_manager, false, false); 430 if (WARN_ON(err)) 431 goto err; 432 433 xe_bo_dev_init(&xe->bo_device); 434 err = drmm_add_action_or_reset(&xe->drm, xe_device_destroy, NULL); 435 if (err) 436 goto err; 437 438 err = xe_shrinker_create(xe); 439 if (err) 440 goto err; 441 442 xe->info.devid = pdev->device; 443 xe->info.revid = pdev->revision; 444 xe->info.force_execlist = xe_modparam.force_execlist; 445 446 err = xe_irq_init(xe); 447 if (err) 448 goto err; 449 450 init_waitqueue_head(&xe->ufence_wq); 451 452 init_rwsem(&xe->usm.lock); 453 454 xa_init_flags(&xe->usm.asid_to_vm, XA_FLAGS_ALLOC); 455 456 if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) { 457 /* Trigger a large asid and an early asid wrap. */ 458 u32 asid; 459 460 BUILD_BUG_ON(XE_MAX_ASID < 2); 461 err = xa_alloc_cyclic(&xe->usm.asid_to_vm, &asid, NULL, 462 XA_LIMIT(XE_MAX_ASID - 2, XE_MAX_ASID - 1), 463 &xe->usm.next_asid, GFP_KERNEL); 464 drm_WARN_ON(&xe->drm, err); 465 if (err >= 0) 466 xa_erase(&xe->usm.asid_to_vm, asid); 467 } 468 469 err = xe_bo_pinned_init(xe); 470 if (err) 471 goto err; 472 473 xe->preempt_fence_wq = alloc_ordered_workqueue("xe-preempt-fence-wq", 474 WQ_MEM_RECLAIM); 475 xe->ordered_wq = alloc_ordered_workqueue("xe-ordered-wq", 0); 476 xe->unordered_wq = alloc_workqueue("xe-unordered-wq", 0, 0); 477 xe->destroy_wq = alloc_workqueue("xe-destroy-wq", 0, 0); 478 if (!xe->ordered_wq || !xe->unordered_wq || 479 !xe->preempt_fence_wq || !xe->destroy_wq) { 480 /* 481 * Cleanup done in xe_device_destroy via 482 * drmm_add_action_or_reset register above 483 */ 484 drm_err(&xe->drm, "Failed to allocate xe workqueues\n"); 485 err = -ENOMEM; 486 goto err; 487 } 488 489 err = drmm_mutex_init(&xe->drm, &xe->pmt.lock); 490 if (err) 491 goto err; 492 493 err = xe_display_create(xe); 494 if (WARN_ON(err)) 495 goto err; 496 497 return xe; 498 499 err: 500 return ERR_PTR(err); 501 } 502 ALLOW_ERROR_INJECTION(xe_device_create, ERRNO); /* See xe_pci_probe() */ 503 504 static bool xe_driver_flr_disabled(struct xe_device *xe) 505 { 506 if (IS_SRIOV_VF(xe)) 507 return true; 508 509 if (xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL_PROTECTED) & DRIVERINT_FLR_DIS) { 510 drm_info(&xe->drm, "Driver-FLR disabled by BIOS\n"); 511 return true; 512 } 513 514 return false; 515 } 516 517 /* 518 * The driver-initiated FLR is the highest level of reset that we can trigger 519 * from within the driver. It is different from the PCI FLR in that it doesn't 520 * fully reset the SGUnit and doesn't modify the PCI config space and therefore 521 * it doesn't require a re-enumeration of the PCI BARs. However, the 522 * driver-initiated FLR does still cause a reset of both GT and display and a 523 * memory wipe of local and stolen memory, so recovery would require a full HW 524 * re-init and saving/restoring (or re-populating) the wiped memory. Since we 525 * perform the FLR as the very last action before releasing access to the HW 526 * during the driver release flow, we don't attempt recovery at all, because 527 * if/when a new instance of i915 is bound to the device it will do a full 528 * re-init anyway. 529 */ 530 static void __xe_driver_flr(struct xe_device *xe) 531 { 532 const unsigned int flr_timeout = 3 * USEC_PER_SEC; /* specs recommend a 3s wait */ 533 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 534 int ret; 535 536 drm_dbg(&xe->drm, "Triggering Driver-FLR\n"); 537 538 /* 539 * Make sure any pending FLR requests have cleared by waiting for the 540 * FLR trigger bit to go to zero. Also clear GU_DEBUG's DRIVERFLR_STATUS 541 * to make sure it's not still set from a prior attempt (it's a write to 542 * clear bit). 543 * Note that we should never be in a situation where a previous attempt 544 * is still pending (unless the HW is totally dead), but better to be 545 * safe in case something unexpected happens 546 */ 547 ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); 548 if (ret) { 549 drm_err(&xe->drm, "Driver-FLR-prepare wait for ready failed! %d\n", ret); 550 return; 551 } 552 xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS); 553 554 /* Trigger the actual Driver-FLR */ 555 xe_mmio_rmw32(mmio, GU_CNTL, 0, DRIVERFLR); 556 557 /* Wait for hardware teardown to complete */ 558 ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); 559 if (ret) { 560 drm_err(&xe->drm, "Driver-FLR-teardown wait completion failed! %d\n", ret); 561 return; 562 } 563 564 /* Wait for hardware/firmware re-init to complete */ 565 ret = xe_mmio_wait32(mmio, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS, 566 flr_timeout, NULL, false); 567 if (ret) { 568 drm_err(&xe->drm, "Driver-FLR-reinit wait completion failed! %d\n", ret); 569 return; 570 } 571 572 /* Clear sticky completion status */ 573 xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS); 574 } 575 576 static void xe_driver_flr(struct xe_device *xe) 577 { 578 if (xe_driver_flr_disabled(xe)) 579 return; 580 581 __xe_driver_flr(xe); 582 } 583 584 static void xe_driver_flr_fini(void *arg) 585 { 586 struct xe_device *xe = arg; 587 588 if (xe->needs_flr_on_fini) 589 xe_driver_flr(xe); 590 } 591 592 static void xe_device_sanitize(void *arg) 593 { 594 struct xe_device *xe = arg; 595 struct xe_gt *gt; 596 u8 id; 597 598 for_each_gt(gt, xe, id) 599 xe_gt_sanitize(gt); 600 } 601 602 static int xe_set_dma_info(struct xe_device *xe) 603 { 604 unsigned int mask_size = xe->info.dma_mask_size; 605 int err; 606 607 dma_set_max_seg_size(xe->drm.dev, xe_sg_segment_size(xe->drm.dev)); 608 609 err = dma_set_mask(xe->drm.dev, DMA_BIT_MASK(mask_size)); 610 if (err) 611 goto mask_err; 612 613 err = dma_set_coherent_mask(xe->drm.dev, DMA_BIT_MASK(mask_size)); 614 if (err) 615 goto mask_err; 616 617 return 0; 618 619 mask_err: 620 drm_err(&xe->drm, "Can't set DMA mask/consistent mask (%d)\n", err); 621 return err; 622 } 623 624 static bool verify_lmem_ready(struct xe_device *xe) 625 { 626 u32 val = xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL) & LMEM_INIT; 627 628 return !!val; 629 } 630 631 static int wait_for_lmem_ready(struct xe_device *xe) 632 { 633 unsigned long timeout, start; 634 635 if (!IS_DGFX(xe)) 636 return 0; 637 638 if (IS_SRIOV_VF(xe)) 639 return 0; 640 641 if (verify_lmem_ready(xe)) 642 return 0; 643 644 drm_dbg(&xe->drm, "Waiting for lmem initialization\n"); 645 646 start = jiffies; 647 timeout = start + secs_to_jiffies(60); /* 60 sec! */ 648 649 do { 650 if (signal_pending(current)) 651 return -EINTR; 652 653 /* 654 * The boot firmware initializes local memory and 655 * assesses its health. If memory training fails, 656 * the punit will have been instructed to keep the GT powered 657 * down.we won't be able to communicate with it 658 * 659 * If the status check is done before punit updates the register, 660 * it can lead to the system being unusable. 661 * use a timeout and defer the probe to prevent this. 662 */ 663 if (time_after(jiffies, timeout)) { 664 drm_dbg(&xe->drm, "lmem not initialized by firmware\n"); 665 return -EPROBE_DEFER; 666 } 667 668 msleep(20); 669 670 } while (!verify_lmem_ready(xe)); 671 672 drm_dbg(&xe->drm, "lmem ready after %ums", 673 jiffies_to_msecs(jiffies - start)); 674 675 return 0; 676 } 677 ALLOW_ERROR_INJECTION(wait_for_lmem_ready, ERRNO); /* See xe_pci_probe() */ 678 679 static void sriov_update_device_info(struct xe_device *xe) 680 { 681 /* disable features that are not available/applicable to VFs */ 682 if (IS_SRIOV_VF(xe)) { 683 xe->info.probe_display = 0; 684 xe->info.has_heci_gscfi = 0; 685 xe->info.skip_guc_pc = 1; 686 xe->info.skip_pcode = 1; 687 } 688 } 689 690 /** 691 * xe_device_probe_early: Device early probe 692 * @xe: xe device instance 693 * 694 * Initialize MMIO resources that don't require any 695 * knowledge about tile count. Also initialize pcode and 696 * check vram initialization on root tile. 697 * 698 * Return: 0 on success, error code on failure 699 */ 700 int xe_device_probe_early(struct xe_device *xe) 701 { 702 int err; 703 704 err = xe_mmio_probe_early(xe); 705 if (err) 706 return err; 707 708 xe_sriov_probe_early(xe); 709 710 sriov_update_device_info(xe); 711 712 err = xe_pcode_probe_early(xe); 713 if (err || xe_survivability_mode_is_requested(xe)) { 714 int save_err = err; 715 716 /* 717 * Try to leave device in survivability mode if device is 718 * possible, but still return the previous error for error 719 * propagation 720 */ 721 err = xe_survivability_mode_enable(xe); 722 if (err) 723 return err; 724 725 return save_err; 726 } 727 728 err = wait_for_lmem_ready(xe); 729 if (err) 730 return err; 731 732 xe->wedged.mode = xe_modparam.wedged_mode; 733 734 return 0; 735 } 736 ALLOW_ERROR_INJECTION(xe_device_probe_early, ERRNO); /* See xe_pci_probe() */ 737 738 static int probe_has_flat_ccs(struct xe_device *xe) 739 { 740 struct xe_gt *gt; 741 unsigned int fw_ref; 742 u32 reg; 743 744 /* Always enabled/disabled, no runtime check to do */ 745 if (GRAPHICS_VER(xe) < 20 || !xe->info.has_flat_ccs || IS_SRIOV_VF(xe)) 746 return 0; 747 748 gt = xe_root_mmio_gt(xe); 749 750 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 751 if (!fw_ref) 752 return -ETIMEDOUT; 753 754 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER); 755 xe->info.has_flat_ccs = (reg & XE2_FLAT_CCS_ENABLE); 756 757 if (!xe->info.has_flat_ccs) 758 drm_dbg(&xe->drm, 759 "Flat CCS has been disabled in bios, May lead to performance impact"); 760 761 xe_force_wake_put(gt_to_fw(gt), fw_ref); 762 763 return 0; 764 } 765 766 int xe_device_probe(struct xe_device *xe) 767 { 768 struct xe_tile *tile; 769 struct xe_gt *gt; 770 int err; 771 u8 id; 772 773 xe_pat_init_early(xe); 774 775 err = xe_sriov_init(xe); 776 if (err) 777 return err; 778 779 xe->info.mem_region_mask = 1; 780 781 err = xe_set_dma_info(xe); 782 if (err) 783 return err; 784 785 err = xe_mmio_probe_tiles(xe); 786 if (err) 787 return err; 788 789 err = xe_ttm_sys_mgr_init(xe); 790 if (err) 791 return err; 792 793 for_each_gt(gt, xe, id) { 794 err = xe_gt_init_early(gt); 795 if (err) 796 return err; 797 798 /* 799 * Only after this point can GT-specific MMIO operations 800 * (including things like communication with the GuC) 801 * be performed. 802 */ 803 xe_gt_mmio_init(gt); 804 } 805 806 for_each_tile(tile, xe, id) { 807 if (IS_SRIOV_VF(xe)) { 808 xe_guc_comm_init_early(&tile->primary_gt->uc.guc); 809 err = xe_gt_sriov_vf_bootstrap(tile->primary_gt); 810 if (err) 811 return err; 812 err = xe_gt_sriov_vf_query_config(tile->primary_gt); 813 if (err) 814 return err; 815 } 816 err = xe_ggtt_init_early(tile->mem.ggtt); 817 if (err) 818 return err; 819 err = xe_memirq_init(&tile->memirq); 820 if (err) 821 return err; 822 } 823 824 for_each_gt(gt, xe, id) { 825 err = xe_gt_init_hwconfig(gt); 826 if (err) 827 return err; 828 } 829 830 err = xe_devcoredump_init(xe); 831 if (err) 832 return err; 833 834 /* 835 * From here on, if a step fails, make sure a Driver-FLR is triggereed 836 */ 837 err = devm_add_action_or_reset(xe->drm.dev, xe_driver_flr_fini, xe); 838 if (err) 839 return err; 840 841 err = probe_has_flat_ccs(xe); 842 if (err) 843 return err; 844 845 err = xe_vram_probe(xe); 846 if (err) 847 return err; 848 849 for_each_tile(tile, xe, id) { 850 err = xe_tile_init_noalloc(tile); 851 if (err) 852 return err; 853 } 854 855 /* Allocate and map stolen after potential VRAM resize */ 856 err = xe_ttm_stolen_mgr_init(xe); 857 if (err) 858 return err; 859 860 /* 861 * Now that GT is initialized (TTM in particular), 862 * we can try to init display, and inherit the initial fb. 863 * This is the reason the first allocation needs to be done 864 * inside display. 865 */ 866 err = xe_display_init_early(xe); 867 if (err) 868 return err; 869 870 for_each_tile(tile, xe, id) { 871 err = xe_tile_init(tile); 872 if (err) 873 return err; 874 } 875 876 err = xe_irq_install(xe); 877 if (err) 878 return err; 879 880 for_each_gt(gt, xe, id) { 881 err = xe_gt_init(gt); 882 if (err) 883 return err; 884 } 885 886 err = xe_heci_gsc_init(xe); 887 if (err) 888 return err; 889 890 err = xe_oa_init(xe); 891 if (err) 892 return err; 893 894 err = xe_display_init(xe); 895 if (err) 896 return err; 897 898 err = xe_pxp_init(xe); 899 if (err) 900 return err; 901 902 err = drm_dev_register(&xe->drm, 0); 903 if (err) 904 return err; 905 906 xe_display_register(xe); 907 908 err = xe_oa_register(xe); 909 if (err) 910 goto err_unregister_display; 911 912 err = xe_pmu_register(&xe->pmu); 913 if (err) 914 goto err_unregister_display; 915 916 err = xe_device_sysfs_init(xe); 917 if (err) 918 goto err_unregister_display; 919 920 xe_debugfs_register(xe); 921 922 err = xe_hwmon_register(xe); 923 if (err) 924 goto err_unregister_display; 925 926 for_each_gt(gt, xe, id) 927 xe_gt_sanitize_freq(gt); 928 929 xe_vsec_init(xe); 930 931 return devm_add_action_or_reset(xe->drm.dev, xe_device_sanitize, xe); 932 933 err_unregister_display: 934 xe_display_unregister(xe); 935 936 return err; 937 } 938 939 void xe_device_remove(struct xe_device *xe) 940 { 941 xe_display_unregister(xe); 942 943 drm_dev_unplug(&xe->drm); 944 945 xe_bo_pci_dev_remove_all(xe); 946 } 947 948 void xe_device_shutdown(struct xe_device *xe) 949 { 950 struct xe_gt *gt; 951 u8 id; 952 953 drm_dbg(&xe->drm, "Shutting down device\n"); 954 955 if (xe_driver_flr_disabled(xe)) { 956 xe_display_pm_shutdown(xe); 957 958 xe_irq_suspend(xe); 959 960 for_each_gt(gt, xe, id) 961 xe_gt_shutdown(gt); 962 963 xe_display_pm_shutdown_late(xe); 964 } else { 965 /* BOOM! */ 966 __xe_driver_flr(xe); 967 } 968 } 969 970 /** 971 * xe_device_wmb() - Device specific write memory barrier 972 * @xe: the &xe_device 973 * 974 * While wmb() is sufficient for a barrier if we use system memory, on discrete 975 * platforms with device memory we additionally need to issue a register write. 976 * Since it doesn't matter which register we write to, use the read-only VF_CAP 977 * register that is also marked as accessible by the VFs. 978 */ 979 void xe_device_wmb(struct xe_device *xe) 980 { 981 wmb(); 982 if (IS_DGFX(xe)) 983 xe_mmio_write32(xe_root_tile_mmio(xe), VF_CAP_REG, 0); 984 } 985 986 /** 987 * xe_device_td_flush() - Flush transient L3 cache entries 988 * @xe: The device 989 * 990 * Display engine has direct access to memory and is never coherent with L3/L4 991 * caches (or CPU caches), however KMD is responsible for specifically flushing 992 * transient L3 GPU cache entries prior to the flip sequence to ensure scanout 993 * can happen from such a surface without seeing corruption. 994 * 995 * Display surfaces can be tagged as transient by mapping it using one of the 996 * various L3:XD PAT index modes on Xe2. 997 * 998 * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is flushed 999 * at the end of each submission via PIPE_CONTROL for compute/render, since SA 1000 * Media is not coherent with L3 and we want to support render-vs-media 1001 * usescases. For other engines like copy/blt the HW internally forces uncached 1002 * behaviour, hence why we can skip the TDF on such platforms. 1003 */ 1004 void xe_device_td_flush(struct xe_device *xe) 1005 { 1006 struct xe_gt *gt; 1007 unsigned int fw_ref; 1008 u8 id; 1009 1010 if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20) 1011 return; 1012 1013 if (XE_WA(xe_root_mmio_gt(xe), 16023588340)) { 1014 xe_device_l2_flush(xe); 1015 return; 1016 } 1017 1018 for_each_gt(gt, xe, id) { 1019 if (xe_gt_is_media_type(gt)) 1020 continue; 1021 1022 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1023 if (!fw_ref) 1024 return; 1025 1026 xe_mmio_write32(>->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST); 1027 /* 1028 * FIXME: We can likely do better here with our choice of 1029 * timeout. Currently we just assume the worst case, i.e. 150us, 1030 * which is believed to be sufficient to cover the worst case 1031 * scenario on current platforms if all cache entries are 1032 * transient and need to be flushed.. 1033 */ 1034 if (xe_mmio_wait32(>->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0, 1035 150, NULL, false)) 1036 xe_gt_err_once(gt, "TD flush timeout\n"); 1037 1038 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1039 } 1040 } 1041 1042 void xe_device_l2_flush(struct xe_device *xe) 1043 { 1044 struct xe_gt *gt; 1045 unsigned int fw_ref; 1046 1047 gt = xe_root_mmio_gt(xe); 1048 1049 if (!XE_WA(gt, 16023588340)) 1050 return; 1051 1052 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1053 if (!fw_ref) 1054 return; 1055 1056 spin_lock(>->global_invl_lock); 1057 xe_mmio_write32(>->mmio, XE2_GLOBAL_INVAL, 0x1); 1058 1059 if (xe_mmio_wait32(>->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 500, NULL, true)) 1060 xe_gt_err_once(gt, "Global invalidation timeout\n"); 1061 spin_unlock(>->global_invl_lock); 1062 1063 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1064 } 1065 1066 u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size) 1067 { 1068 return xe_device_has_flat_ccs(xe) ? 1069 DIV_ROUND_UP_ULL(size, NUM_BYTES_PER_CCS_BYTE(xe)) : 0; 1070 } 1071 1072 /** 1073 * xe_device_assert_mem_access - Inspect the current runtime_pm state. 1074 * @xe: xe device instance 1075 * 1076 * To be used before any kind of memory access. It will splat a debug warning 1077 * if the device is currently sleeping. But it doesn't guarantee in any way 1078 * that the device is going to remain awake. Xe PM runtime get and put 1079 * functions might be added to the outer bound of the memory access, while 1080 * this check is intended for inner usage to splat some warning if the worst 1081 * case has just happened. 1082 */ 1083 void xe_device_assert_mem_access(struct xe_device *xe) 1084 { 1085 xe_assert(xe, !xe_pm_runtime_suspended(xe)); 1086 } 1087 1088 void xe_device_snapshot_print(struct xe_device *xe, struct drm_printer *p) 1089 { 1090 struct xe_gt *gt; 1091 u8 id; 1092 1093 drm_printf(p, "PCI ID: 0x%04x\n", xe->info.devid); 1094 drm_printf(p, "PCI revision: 0x%02x\n", xe->info.revid); 1095 1096 for_each_gt(gt, xe, id) { 1097 drm_printf(p, "GT id: %u\n", id); 1098 drm_printf(p, "\tTile: %u\n", gt->tile->id); 1099 drm_printf(p, "\tType: %s\n", 1100 gt->info.type == XE_GT_TYPE_MAIN ? "main" : "media"); 1101 drm_printf(p, "\tIP ver: %u.%u.%u\n", 1102 REG_FIELD_GET(GMD_ID_ARCH_MASK, gt->info.gmdid), 1103 REG_FIELD_GET(GMD_ID_RELEASE_MASK, gt->info.gmdid), 1104 REG_FIELD_GET(GMD_ID_REVID, gt->info.gmdid)); 1105 drm_printf(p, "\tCS reference clock: %u\n", gt->info.reference_clock); 1106 } 1107 } 1108 1109 u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address) 1110 { 1111 return sign_extend64(address, xe->info.va_bits - 1); 1112 } 1113 1114 u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address) 1115 { 1116 return address & GENMASK_ULL(xe->info.va_bits - 1, 0); 1117 } 1118 1119 static void xe_device_wedged_fini(struct drm_device *drm, void *arg) 1120 { 1121 struct xe_device *xe = arg; 1122 1123 xe_pm_runtime_put(xe); 1124 } 1125 1126 /** 1127 * xe_device_declare_wedged - Declare device wedged 1128 * @xe: xe device instance 1129 * 1130 * This is a final state that can only be cleared with a module 1131 * re-probe (unbind + bind). 1132 * In this state every IOCTL will be blocked so the GT cannot be used. 1133 * In general it will be called upon any critical error such as gt reset 1134 * failure or guc loading failure. Userspace will be notified of this state 1135 * through device wedged uevent. 1136 * If xe.wedged module parameter is set to 2, this function will be called 1137 * on every single execution timeout (a.k.a. GPU hang) right after devcoredump 1138 * snapshot capture. In this mode, GT reset won't be attempted so the state of 1139 * the issue is preserved for further debugging. 1140 */ 1141 void xe_device_declare_wedged(struct xe_device *xe) 1142 { 1143 struct xe_gt *gt; 1144 u8 id; 1145 1146 if (xe->wedged.mode == 0) { 1147 drm_dbg(&xe->drm, "Wedged mode is forcibly disabled\n"); 1148 return; 1149 } 1150 1151 xe_pm_runtime_get_noresume(xe); 1152 1153 if (drmm_add_action_or_reset(&xe->drm, xe_device_wedged_fini, xe)) { 1154 drm_err(&xe->drm, "Failed to register xe_device_wedged_fini clean-up. Although device is wedged.\n"); 1155 return; 1156 } 1157 1158 if (!atomic_xchg(&xe->wedged.flag, 1)) { 1159 xe->needs_flr_on_fini = true; 1160 drm_err(&xe->drm, 1161 "CRITICAL: Xe has declared device %s as wedged.\n" 1162 "IOCTLs and executions are blocked. Only a rebind may clear the failure\n" 1163 "Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/xe/kernel/issues/new\n", 1164 dev_name(xe->drm.dev)); 1165 1166 /* Notify userspace of wedged device */ 1167 drm_dev_wedged_event(&xe->drm, 1168 DRM_WEDGE_RECOVERY_REBIND | DRM_WEDGE_RECOVERY_BUS_RESET); 1169 } 1170 1171 for_each_gt(gt, xe, id) 1172 xe_gt_declare_wedged(gt); 1173 } 1174