1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_device.h" 7 8 #include <linux/aperture.h> 9 #include <linux/delay.h> 10 #include <linux/fault-inject.h> 11 #include <linux/units.h> 12 13 #include <drm/drm_client.h> 14 #include <drm/drm_gem_ttm_helper.h> 15 #include <drm/drm_ioctl.h> 16 #include <drm/drm_managed.h> 17 #include <drm/drm_pagemap_util.h> 18 #include <drm/drm_print.h> 19 #include <kunit/static_stub.h> 20 #include <uapi/drm/xe_drm.h> 21 22 #include "display/xe_display.h" 23 #include "instructions/xe_gpu_commands.h" 24 #include "regs/xe_gt_regs.h" 25 #include "regs/xe_regs.h" 26 #include "xe_bo.h" 27 #include "xe_bo_evict.h" 28 #include "xe_configfs.h" 29 #include "xe_debugfs.h" 30 #include "xe_defaults.h" 31 #include "xe_devcoredump.h" 32 #include "xe_device_sysfs.h" 33 #include "xe_dma_buf.h" 34 #include "xe_drm_client.h" 35 #include "xe_drv.h" 36 #include "xe_exec.h" 37 #include "xe_exec_queue.h" 38 #include "xe_force_wake.h" 39 #include "xe_ggtt.h" 40 #include "xe_gt.h" 41 #include "xe_gt_mcr.h" 42 #include "xe_gt_printk.h" 43 #include "xe_gt_sriov_vf.h" 44 #include "xe_guc.h" 45 #include "xe_guc_pc.h" 46 #include "xe_hw_engine_group.h" 47 #include "xe_hwmon.h" 48 #include "xe_i2c.h" 49 #include "xe_irq.h" 50 #include "xe_late_bind_fw.h" 51 #include "xe_mmio.h" 52 #include "xe_module.h" 53 #include "xe_nvm.h" 54 #include "xe_oa.h" 55 #include "xe_observation.h" 56 #include "xe_pagefault.h" 57 #include "xe_pat.h" 58 #include "xe_pcode.h" 59 #include "xe_pm.h" 60 #include "xe_pmu.h" 61 #include "xe_psmi.h" 62 #include "xe_pxp.h" 63 #include "xe_query.h" 64 #include "xe_shrinker.h" 65 #include "xe_soc_remapper.h" 66 #include "xe_survivability_mode.h" 67 #include "xe_sriov.h" 68 #include "xe_svm.h" 69 #include "xe_sysctrl.h" 70 #include "xe_tile.h" 71 #include "xe_ttm_stolen_mgr.h" 72 #include "xe_ttm_sys_mgr.h" 73 #include "xe_vm.h" 74 #include "xe_vm_madvise.h" 75 #include "xe_vram.h" 76 #include "xe_vram_types.h" 77 #include "xe_vsec.h" 78 #include "xe_wait_user_fence.h" 79 #include "xe_wa.h" 80 81 #include <generated/xe_device_wa_oob.h> 82 #include <generated/xe_wa_oob.h> 83 84 static int xe_file_open(struct drm_device *dev, struct drm_file *file) 85 { 86 struct xe_device *xe = to_xe_device(dev); 87 struct xe_drm_client *client; 88 struct xe_file *xef; 89 int ret = -ENOMEM; 90 struct task_struct *task = NULL; 91 92 xef = kzalloc_obj(*xef); 93 if (!xef) 94 return ret; 95 96 client = xe_drm_client_alloc(); 97 if (!client) { 98 kfree(xef); 99 return ret; 100 } 101 102 xef->drm = file; 103 xef->client = client; 104 xef->xe = xe; 105 106 mutex_init(&xef->vm.lock); 107 xa_init_flags(&xef->vm.xa, XA_FLAGS_ALLOC1); 108 109 mutex_init(&xef->exec_queue.lock); 110 xa_init_flags(&xef->exec_queue.xa, XA_FLAGS_ALLOC1); 111 112 file->driver_priv = xef; 113 kref_init(&xef->refcount); 114 115 task = get_pid_task(rcu_access_pointer(file->pid), PIDTYPE_PID); 116 if (task) { 117 xef->process_name = kstrdup(task->comm, GFP_KERNEL); 118 xef->pid = task->pid; 119 put_task_struct(task); 120 } 121 122 return 0; 123 } 124 125 static void xe_file_destroy(struct kref *ref) 126 { 127 struct xe_file *xef = container_of(ref, struct xe_file, refcount); 128 129 xa_destroy(&xef->exec_queue.xa); 130 mutex_destroy(&xef->exec_queue.lock); 131 xa_destroy(&xef->vm.xa); 132 mutex_destroy(&xef->vm.lock); 133 134 xe_drm_client_put(xef->client); 135 kfree(xef->process_name); 136 kfree(xef); 137 } 138 139 /** 140 * xe_file_get() - Take a reference to the xe file object 141 * @xef: Pointer to the xe file 142 * 143 * Anyone with a pointer to xef must take a reference to the xe file 144 * object using this call. 145 * 146 * Return: xe file pointer 147 */ 148 struct xe_file *xe_file_get(struct xe_file *xef) 149 { 150 kref_get(&xef->refcount); 151 return xef; 152 } 153 154 /** 155 * xe_file_put() - Drop a reference to the xe file object 156 * @xef: Pointer to the xe file 157 * 158 * Used to drop reference to the xef object 159 */ 160 void xe_file_put(struct xe_file *xef) 161 { 162 kref_put(&xef->refcount, xe_file_destroy); 163 } 164 165 static void xe_file_close(struct drm_device *dev, struct drm_file *file) 166 { 167 struct xe_device *xe = to_xe_device(dev); 168 struct xe_file *xef = file->driver_priv; 169 struct xe_vm *vm; 170 struct xe_exec_queue *q; 171 unsigned long idx; 172 173 guard(xe_pm_runtime)(xe); 174 175 /* 176 * No need for exec_queue.lock here as there is no contention for it 177 * when FD is closing as IOCTLs presumably can't be modifying the 178 * xarray. Taking exec_queue.lock here causes undue dependency on 179 * vm->lock taken during xe_exec_queue_kill(). 180 */ 181 xa_for_each(&xef->exec_queue.xa, idx, q) { 182 if (q->vm && q->hwe->hw_engine_group) 183 xe_hw_engine_group_del_exec_queue(q->hwe->hw_engine_group, q); 184 xe_exec_queue_kill(q); 185 xe_exec_queue_put(q); 186 } 187 xa_for_each(&xef->vm.xa, idx, vm) 188 xe_vm_close_and_put(vm); 189 190 xe_file_put(xef); 191 } 192 193 static const struct drm_ioctl_desc xe_ioctls[] = { 194 DRM_IOCTL_DEF_DRV(XE_DEVICE_QUERY, xe_query_ioctl, DRM_RENDER_ALLOW), 195 DRM_IOCTL_DEF_DRV(XE_GEM_CREATE, xe_gem_create_ioctl, DRM_RENDER_ALLOW), 196 DRM_IOCTL_DEF_DRV(XE_GEM_MMAP_OFFSET, xe_gem_mmap_offset_ioctl, 197 DRM_RENDER_ALLOW), 198 DRM_IOCTL_DEF_DRV(XE_VM_CREATE, xe_vm_create_ioctl, DRM_RENDER_ALLOW), 199 DRM_IOCTL_DEF_DRV(XE_VM_DESTROY, xe_vm_destroy_ioctl, DRM_RENDER_ALLOW), 200 DRM_IOCTL_DEF_DRV(XE_VM_BIND, xe_vm_bind_ioctl, DRM_RENDER_ALLOW), 201 DRM_IOCTL_DEF_DRV(XE_EXEC, xe_exec_ioctl, DRM_RENDER_ALLOW), 202 DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_CREATE, xe_exec_queue_create_ioctl, 203 DRM_RENDER_ALLOW), 204 DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_DESTROY, xe_exec_queue_destroy_ioctl, 205 DRM_RENDER_ALLOW), 206 DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_GET_PROPERTY, xe_exec_queue_get_property_ioctl, 207 DRM_RENDER_ALLOW), 208 DRM_IOCTL_DEF_DRV(XE_WAIT_USER_FENCE, xe_wait_user_fence_ioctl, 209 DRM_RENDER_ALLOW), 210 DRM_IOCTL_DEF_DRV(XE_OBSERVATION, xe_observation_ioctl, DRM_RENDER_ALLOW), 211 DRM_IOCTL_DEF_DRV(XE_MADVISE, xe_vm_madvise_ioctl, DRM_RENDER_ALLOW), 212 DRM_IOCTL_DEF_DRV(XE_VM_QUERY_MEM_RANGE_ATTRS, xe_vm_query_vmas_attrs_ioctl, 213 DRM_RENDER_ALLOW), 214 DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_SET_PROPERTY, xe_exec_queue_set_property_ioctl, 215 DRM_RENDER_ALLOW), 216 DRM_IOCTL_DEF_DRV(XE_VM_GET_PROPERTY, xe_vm_get_property_ioctl, 217 DRM_RENDER_ALLOW), 218 }; 219 220 static long xe_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 221 { 222 struct drm_file *file_priv = file->private_data; 223 struct xe_device *xe = to_xe_device(file_priv->minor->dev); 224 long ret; 225 226 if (xe_device_wedged(xe)) 227 return -ECANCELED; 228 229 ACQUIRE(xe_pm_runtime_ioctl, pm)(xe); 230 ret = ACQUIRE_ERR(xe_pm_runtime_ioctl, &pm); 231 if (ret >= 0) 232 ret = drm_ioctl(file, cmd, arg); 233 234 return ret; 235 } 236 237 #ifdef CONFIG_COMPAT 238 static long xe_drm_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 239 { 240 struct drm_file *file_priv = file->private_data; 241 struct xe_device *xe = to_xe_device(file_priv->minor->dev); 242 long ret; 243 244 if (xe_device_wedged(xe)) 245 return -ECANCELED; 246 247 ACQUIRE(xe_pm_runtime_ioctl, pm)(xe); 248 ret = ACQUIRE_ERR(xe_pm_runtime_ioctl, &pm); 249 if (ret >= 0) 250 ret = drm_compat_ioctl(file, cmd, arg); 251 252 return ret; 253 } 254 #else 255 /* similarly to drm_compat_ioctl, let's it be assigned to .compat_ioct unconditionally */ 256 #define xe_drm_compat_ioctl NULL 257 #endif 258 259 static void barrier_open(struct vm_area_struct *vma) 260 { 261 drm_dev_get(vma->vm_private_data); 262 } 263 264 static void barrier_close(struct vm_area_struct *vma) 265 { 266 drm_dev_put(vma->vm_private_data); 267 } 268 269 static void barrier_release_dummy_page(struct drm_device *dev, void *res) 270 { 271 struct page *dummy_page = (struct page *)res; 272 273 __free_page(dummy_page); 274 } 275 276 static vm_fault_t barrier_fault(struct vm_fault *vmf) 277 { 278 struct drm_device *dev = vmf->vma->vm_private_data; 279 struct vm_area_struct *vma = vmf->vma; 280 vm_fault_t ret = VM_FAULT_NOPAGE; 281 pgprot_t prot; 282 int idx; 283 284 prot = vm_get_page_prot(vma->vm_flags); 285 286 if (drm_dev_enter(dev, &idx)) { 287 unsigned long pfn; 288 289 #define LAST_DB_PAGE_OFFSET 0x7ff001 290 pfn = PHYS_PFN(pci_resource_start(to_pci_dev(dev->dev), 0) + 291 LAST_DB_PAGE_OFFSET); 292 ret = vmf_insert_pfn_prot(vma, vma->vm_start, pfn, 293 pgprot_noncached(prot)); 294 drm_dev_exit(idx); 295 } else { 296 struct page *page; 297 298 /* Allocate new dummy page to map all the VA range in this VMA to it*/ 299 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 300 if (!page) 301 return VM_FAULT_OOM; 302 303 /* Set the page to be freed using drmm release action */ 304 if (drmm_add_action_or_reset(dev, barrier_release_dummy_page, page)) 305 return VM_FAULT_OOM; 306 307 ret = vmf_insert_pfn_prot(vma, vma->vm_start, page_to_pfn(page), 308 prot); 309 } 310 311 return ret; 312 } 313 314 static const struct vm_operations_struct vm_ops_barrier = { 315 .open = barrier_open, 316 .close = barrier_close, 317 .fault = barrier_fault, 318 }; 319 320 static int xe_pci_barrier_mmap(struct file *filp, 321 struct vm_area_struct *vma) 322 { 323 struct drm_file *priv = filp->private_data; 324 struct drm_device *dev = priv->minor->dev; 325 struct xe_device *xe = to_xe_device(dev); 326 327 if (!IS_DGFX(xe)) 328 return -EINVAL; 329 330 if (vma->vm_end - vma->vm_start > SZ_4K) 331 return -EINVAL; 332 333 if (is_cow_mapping(vma->vm_flags)) 334 return -EINVAL; 335 336 if (vma->vm_flags & (VM_READ | VM_EXEC)) 337 return -EINVAL; 338 339 vm_flags_clear(vma, VM_MAYREAD | VM_MAYEXEC); 340 vm_flags_set(vma, VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | VM_IO); 341 vma->vm_ops = &vm_ops_barrier; 342 vma->vm_private_data = dev; 343 drm_dev_get(vma->vm_private_data); 344 345 return 0; 346 } 347 348 static int xe_mmap(struct file *filp, struct vm_area_struct *vma) 349 { 350 struct drm_file *priv = filp->private_data; 351 struct drm_device *dev = priv->minor->dev; 352 353 if (drm_dev_is_unplugged(dev)) 354 return -ENODEV; 355 356 switch (vma->vm_pgoff) { 357 case XE_PCI_BARRIER_MMAP_OFFSET >> XE_PTE_SHIFT: 358 return xe_pci_barrier_mmap(filp, vma); 359 } 360 361 return drm_gem_mmap(filp, vma); 362 } 363 364 static const struct file_operations xe_driver_fops = { 365 .owner = THIS_MODULE, 366 .open = drm_open, 367 .release = drm_release_noglobal, 368 .unlocked_ioctl = xe_drm_ioctl, 369 .mmap = xe_mmap, 370 .poll = drm_poll, 371 .read = drm_read, 372 .compat_ioctl = xe_drm_compat_ioctl, 373 .llseek = noop_llseek, 374 #ifdef CONFIG_PROC_FS 375 .show_fdinfo = drm_show_fdinfo, 376 #endif 377 .fop_flags = FOP_UNSIGNED_OFFSET, 378 }; 379 380 /** 381 * xe_is_xe_file() - Is the file an xe device file? 382 * @file: The file. 383 * 384 * Checks whether the file is opened against 385 * an xe device. 386 * 387 * Return: %true if an xe file, %false if not. 388 */ 389 bool xe_is_xe_file(const struct file *file) 390 { 391 return file->f_op == &xe_driver_fops; 392 } 393 394 static const struct drm_driver regular_driver = { 395 .driver_features = 396 XE_DISPLAY_DRIVER_FEATURES | 397 DRIVER_GEM | 398 DRIVER_RENDER | DRIVER_SYNCOBJ | 399 DRIVER_SYNCOBJ_TIMELINE | DRIVER_GEM_GPUVA, 400 .open = xe_file_open, 401 .postclose = xe_file_close, 402 403 .gem_prime_import = xe_gem_prime_import, 404 405 .dumb_create = xe_bo_dumb_create, 406 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 407 #ifdef CONFIG_PROC_FS 408 .show_fdinfo = xe_drm_client_fdinfo, 409 #endif 410 .ioctls = xe_ioctls, 411 .num_ioctls = ARRAY_SIZE(xe_ioctls), 412 .fops = &xe_driver_fops, 413 .name = DRIVER_NAME, 414 .desc = DRIVER_DESC, 415 .major = DRIVER_MAJOR, 416 .minor = DRIVER_MINOR, 417 .patchlevel = DRIVER_PATCHLEVEL, 418 XE_DISPLAY_DRIVER_OPS, 419 }; 420 421 #ifdef CONFIG_PCI_IOV 422 static const struct drm_ioctl_desc xe_ioctls_admin_only[] = { 423 DRM_IOCTL_DEF_DRV(XE_DEVICE_QUERY, xe_query_ioctl, DRM_RENDER_ALLOW), 424 DRM_IOCTL_DEF_DRV(XE_OBSERVATION, xe_observation_ioctl, DRM_RENDER_ALLOW), 425 }; 426 427 static const struct drm_driver admin_only_driver = { 428 .driver_features = 429 XE_DISPLAY_DRIVER_FEATURES | 430 DRIVER_GEM | DRIVER_RENDER | DRIVER_GEM_GPUVA, 431 .open = xe_file_open, 432 .postclose = xe_file_close, 433 .ioctls = xe_ioctls_admin_only, 434 .num_ioctls = ARRAY_SIZE(xe_ioctls_admin_only), 435 .fops = &xe_driver_fops, 436 .name = DRIVER_NAME, 437 .desc = DRIVER_DESC, 438 .major = DRIVER_MAJOR, 439 .minor = DRIVER_MINOR, 440 .patchlevel = DRIVER_PATCHLEVEL, 441 XE_DISPLAY_DRIVER_OPS, 442 }; 443 444 /** 445 * xe_device_is_admin_only() - Check whether device is admin only or not. 446 * @xe: the &xe_device to check 447 * 448 * Return: true if the device is admin only, false otherwise. 449 */ 450 bool xe_device_is_admin_only(const struct xe_device *xe) 451 { 452 KUNIT_STATIC_STUB_REDIRECT(xe_device_is_admin_only, xe); 453 return xe->drm.driver == &admin_only_driver; 454 } 455 #endif 456 457 static void xe_device_destroy(struct drm_device *dev, void *dummy) 458 { 459 struct xe_device *xe = to_xe_device(dev); 460 461 xe_bo_dev_fini(&xe->bo_device); 462 463 if (xe->preempt_fence_wq) 464 destroy_workqueue(xe->preempt_fence_wq); 465 466 if (xe->ordered_wq) 467 destroy_workqueue(xe->ordered_wq); 468 469 if (xe->unordered_wq) 470 destroy_workqueue(xe->unordered_wq); 471 472 if (xe->destroy_wq) 473 destroy_workqueue(xe->destroy_wq); 474 475 ttm_device_fini(&xe->ttm); 476 } 477 478 /** 479 * xe_device_create() - Create a new &xe_device instance 480 * @pdev: the parent &pci_dev 481 * 482 * Allocate and initialize a device managed Xe device structure. 483 * 484 * Return: pointer to new &xe_device on success, or ERR_PTR on failure. 485 */ 486 struct xe_device *xe_device_create(struct pci_dev *pdev) 487 { 488 const struct drm_driver *driver = ®ular_driver; 489 struct xe_device *xe; 490 int err; 491 492 #ifdef CONFIG_PCI_IOV 493 /* 494 * Since XE device is not initialized yet, read from configfs 495 * directly to decide whether we are in admin-only PF mode or not. 496 */ 497 if (xe_configfs_admin_only_pf(pdev)) 498 driver = &admin_only_driver; 499 #endif 500 501 err = aperture_remove_conflicting_pci_devices(pdev, driver->name); 502 if (err) 503 return ERR_PTR(err); 504 505 xe = devm_drm_dev_alloc(&pdev->dev, driver, struct xe_device, drm); 506 if (IS_ERR(xe)) 507 return xe; 508 509 err = xe_device_init_early(xe); 510 if (err) 511 return ERR_PTR(err); 512 513 return xe; 514 } 515 ALLOW_ERROR_INJECTION(xe_device_create, ERRNO); /* See xe_pci_probe() */ 516 517 /** 518 * xe_device_init_early() - Initialize a new &xe_device instance 519 * @xe: the &xe_device to initialize 520 * 521 * Return: 0 on success or a negative error code on failure. 522 */ 523 int xe_device_init_early(struct xe_device *xe) 524 { 525 int err; 526 527 err = ttm_device_init(&xe->ttm, &xe_ttm_funcs, xe->drm.dev, 528 xe->drm.anon_inode->i_mapping, 529 xe->drm.vma_offset_manager, 0); 530 if (err) 531 return err; 532 533 xe_bo_dev_init(&xe->bo_device); 534 err = drmm_add_action_or_reset(&xe->drm, xe_device_destroy, NULL); 535 if (err) 536 return err; 537 538 err = xe_shrinker_create(xe); 539 if (err) 540 return err; 541 542 xe->atomic_svm_timeslice_ms = 5; 543 xe->min_run_period_lr_ms = 5; 544 545 err = xe_irq_init(xe); 546 if (err) 547 return err; 548 549 xe_validation_device_init(&xe->val); 550 551 init_waitqueue_head(&xe->ufence_wq); 552 553 init_rwsem(&xe->usm.lock); 554 555 err = xe_pagemap_shrinker_create(xe); 556 if (err) 557 return err; 558 559 xa_init_flags(&xe->usm.asid_to_vm, XA_FLAGS_ALLOC); 560 561 if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) { 562 /* Trigger a large asid and an early asid wrap. */ 563 u32 asid; 564 565 BUILD_BUG_ON(XE_MAX_ASID < 2); 566 err = xa_alloc_cyclic(&xe->usm.asid_to_vm, &asid, NULL, 567 XA_LIMIT(XE_MAX_ASID - 2, XE_MAX_ASID - 1), 568 &xe->usm.next_asid, GFP_KERNEL); 569 drm_WARN_ON(&xe->drm, err); 570 if (err >= 0) 571 xa_erase(&xe->usm.asid_to_vm, asid); 572 } 573 574 err = xe_bo_pinned_init(xe); 575 if (err) 576 return err; 577 578 xe->preempt_fence_wq = alloc_ordered_workqueue("xe-preempt-fence-wq", 579 WQ_MEM_RECLAIM); 580 xe->ordered_wq = alloc_ordered_workqueue("xe-ordered-wq", 0); 581 xe->unordered_wq = alloc_workqueue("xe-unordered-wq", WQ_PERCPU, 0); 582 xe->destroy_wq = alloc_workqueue("xe-destroy-wq", WQ_PERCPU, 0); 583 if (!xe->ordered_wq || !xe->unordered_wq || 584 !xe->preempt_fence_wq || !xe->destroy_wq) { 585 /* 586 * Cleanup done in xe_device_destroy via 587 * drmm_add_action_or_reset register above 588 */ 589 drm_err(&xe->drm, "Failed to allocate xe workqueues\n"); 590 return -ENOMEM; 591 } 592 593 err = drmm_mutex_init(&xe->drm, &xe->pmt.lock); 594 if (err) 595 return err; 596 597 err = xe_pm_init_early(xe); 598 if (err) 599 return err; 600 601 return 0; 602 } 603 604 static bool xe_driver_flr_disabled(struct xe_device *xe) 605 { 606 if (IS_SRIOV_VF(xe)) 607 return true; 608 609 if (xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL_PROTECTED) & DRIVERINT_FLR_DIS) { 610 drm_info(&xe->drm, "Driver-FLR disabled by BIOS\n"); 611 return true; 612 } 613 614 return false; 615 } 616 617 /* 618 * The driver-initiated FLR is the highest level of reset that we can trigger 619 * from within the driver. It is different from the PCI FLR in that it doesn't 620 * fully reset the SGUnit and doesn't modify the PCI config space and therefore 621 * it doesn't require a re-enumeration of the PCI BARs. However, the 622 * driver-initiated FLR does still cause a reset of both GT and display and a 623 * memory wipe of local and stolen memory, so recovery would require a full HW 624 * re-init and saving/restoring (or re-populating) the wiped memory. Since we 625 * perform the FLR as the very last action before releasing access to the HW 626 * during the driver release flow, we don't attempt recovery at all, because 627 * if/when a new instance of Xe is bound to the device it will do a full 628 * re-init anyway. 629 */ 630 static void __xe_driver_flr(struct xe_device *xe) 631 { 632 const unsigned int flr_timeout = 3 * USEC_PER_SEC; /* specs recommend a 3s wait */ 633 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 634 int ret; 635 636 drm_dbg(&xe->drm, "Triggering Driver-FLR\n"); 637 638 /* 639 * Make sure any pending FLR requests have cleared by waiting for the 640 * FLR trigger bit to go to zero. Also clear GU_DEBUG's DRIVERFLR_STATUS 641 * to make sure it's not still set from a prior attempt (it's a write to 642 * clear bit). 643 * Note that we should never be in a situation where a previous attempt 644 * is still pending (unless the HW is totally dead), but better to be 645 * safe in case something unexpected happens 646 */ 647 ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); 648 if (ret) { 649 drm_err(&xe->drm, "Driver-FLR-prepare wait for ready failed! %d\n", ret); 650 return; 651 } 652 xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS); 653 654 /* Trigger the actual Driver-FLR */ 655 xe_mmio_rmw32(mmio, GU_CNTL, 0, DRIVERFLR); 656 657 /* Wait for hardware teardown to complete */ 658 ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); 659 if (ret) { 660 drm_err(&xe->drm, "Driver-FLR-teardown wait completion failed! %d\n", ret); 661 return; 662 } 663 664 /* Wait for hardware/firmware re-init to complete */ 665 ret = xe_mmio_wait32(mmio, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS, 666 flr_timeout, NULL, false); 667 if (ret) { 668 drm_err(&xe->drm, "Driver-FLR-reinit wait completion failed! %d\n", ret); 669 return; 670 } 671 672 /* Clear sticky completion status */ 673 xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS); 674 } 675 676 static void xe_driver_flr(struct xe_device *xe) 677 { 678 if (xe_driver_flr_disabled(xe)) 679 return; 680 681 __xe_driver_flr(xe); 682 } 683 684 static void xe_driver_flr_fini(void *arg) 685 { 686 struct xe_device *xe = arg; 687 688 if (xe->needs_flr_on_fini) 689 xe_driver_flr(xe); 690 } 691 692 static void xe_device_sanitize(void *arg) 693 { 694 struct xe_device *xe = arg; 695 struct xe_gt *gt; 696 u8 id; 697 698 for_each_gt(gt, xe, id) 699 xe_gt_sanitize(gt); 700 } 701 702 static int xe_set_dma_info(struct xe_device *xe) 703 { 704 unsigned int mask_size = xe->info.dma_mask_size; 705 int err; 706 707 dma_set_max_seg_size(xe->drm.dev, xe_sg_segment_size(xe->drm.dev)); 708 709 err = dma_set_mask(xe->drm.dev, DMA_BIT_MASK(mask_size)); 710 if (err) 711 goto mask_err; 712 713 err = dma_set_coherent_mask(xe->drm.dev, DMA_BIT_MASK(mask_size)); 714 if (err) 715 goto mask_err; 716 717 return 0; 718 719 mask_err: 720 drm_err(&xe->drm, "Can't set DMA mask/consistent mask (%d)\n", err); 721 return err; 722 } 723 724 static void assert_lmem_ready(struct xe_device *xe) 725 { 726 if (!IS_DGFX(xe) || IS_SRIOV_VF(xe)) 727 return; 728 729 xe_assert(xe, xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL) & 730 LMEM_INIT); 731 } 732 733 static void vf_update_device_info(struct xe_device *xe) 734 { 735 xe_assert(xe, IS_SRIOV_VF(xe)); 736 /* disable features that are not available/applicable to VFs */ 737 xe->info.probe_display = 0; 738 xe->info.has_heci_cscfi = 0; 739 xe->info.has_heci_gscfi = 0; 740 xe->info.has_late_bind = 0; 741 xe->info.skip_guc_pc = 1; 742 xe->info.skip_pcode = 1; 743 } 744 745 static int xe_device_vram_alloc(struct xe_device *xe) 746 { 747 struct xe_vram_region *vram; 748 749 if (!IS_DGFX(xe)) 750 return 0; 751 752 vram = drmm_kzalloc(&xe->drm, sizeof(*vram), GFP_KERNEL); 753 if (!vram) 754 return -ENOMEM; 755 756 xe->mem.vram = vram; 757 return 0; 758 } 759 760 /** 761 * xe_device_probe_early: Device early probe 762 * @xe: xe device instance 763 * 764 * Initialize MMIO resources that don't require any 765 * knowledge about tile count. Also initialize pcode and 766 * check vram initialization on root tile. 767 * 768 * Return: 0 on success, error code on failure 769 */ 770 int xe_device_probe_early(struct xe_device *xe) 771 { 772 int err; 773 774 xe_wa_device_init(xe); 775 xe_wa_process_device_oob(xe); 776 777 err = xe_mmio_probe_early(xe); 778 if (err) 779 return err; 780 781 xe_sriov_probe_early(xe); 782 783 if (xe_device_is_admin_only(xe) && !IS_SRIOV_PF(xe)) { 784 xe_err(xe, "Can't run Admin-only mode without SR-IOV PF mode!\n"); 785 return -ENODEV; 786 } 787 788 if (IS_SRIOV_VF(xe)) 789 vf_update_device_info(xe); 790 791 /* 792 * Check for pcode uncore_init status to confirm if the SoC 793 * initialization is complete. Until done, any MMIO or lmem access from 794 * the driver will be blocked 795 */ 796 err = xe_pcode_probe_early(xe); 797 if (err || xe_survivability_mode_is_requested(xe)) { 798 int save_err = err; 799 800 /* 801 * Try to leave device in survivability mode if device is 802 * possible, but still return the previous error for error 803 * propagation 804 */ 805 err = xe_survivability_mode_boot_enable(xe); 806 if (err) 807 return err; 808 809 return save_err; 810 } 811 812 /* 813 * Make sure the lmem is initialized and ready to use. xe_pcode_ready() 814 * is flagged after full initialization is complete. Assert if lmem is 815 * not initialized. 816 */ 817 assert_lmem_ready(xe); 818 819 xe->wedged.mode = xe_device_validate_wedged_mode(xe, xe_modparam.wedged_mode) ? 820 XE_DEFAULT_WEDGED_MODE : xe_modparam.wedged_mode; 821 drm_dbg(&xe->drm, "wedged_mode: setting mode (%u) %s\n", 822 xe->wedged.mode, xe_wedged_mode_to_string(xe->wedged.mode)); 823 824 err = xe_device_vram_alloc(xe); 825 if (err) 826 return err; 827 828 return 0; 829 } 830 ALLOW_ERROR_INJECTION(xe_device_probe_early, ERRNO); /* See xe_pci_probe() */ 831 832 static int probe_has_flat_ccs(struct xe_device *xe) 833 { 834 struct xe_gt *gt; 835 u32 reg; 836 837 /* Always enabled/disabled, no runtime check to do */ 838 if (GRAPHICS_VER(xe) < 20 || !xe->info.has_flat_ccs || IS_SRIOV_VF(xe)) 839 return 0; 840 841 gt = xe_root_mmio_gt(xe); 842 if (!gt) 843 return 0; 844 845 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 846 if (!fw_ref.domains) 847 return -ETIMEDOUT; 848 849 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER); 850 xe->info.has_flat_ccs = (reg & XE2_FLAT_CCS_ENABLE); 851 852 if (!xe->info.has_flat_ccs) 853 drm_dbg(&xe->drm, 854 "Flat CCS has been disabled in bios, May lead to performance impact"); 855 856 return 0; 857 } 858 859 /* 860 * Detect if the driver is being run on pre-production hardware. We don't 861 * keep workarounds for pre-production hardware long term, so print an 862 * error and add taint if we're being loaded on a pre-production platform 863 * for which the pre-prod workarounds have already been removed. 864 * 865 * The general policy is that we'll remove any workarounds that only apply to 866 * pre-production hardware around the time force_probe restrictions are lifted 867 * for a platform of the next major IP generation (for example, Xe2 pre-prod 868 * workarounds should be removed around the time the first Xe3 platforms have 869 * force_probe lifted). 870 */ 871 static void detect_preproduction_hw(struct xe_device *xe) 872 { 873 struct xe_gt *gt; 874 int id; 875 876 /* 877 * SR-IOV VFs don't have access to the FUSE2 register, so we can't 878 * check pre-production status there. But the host OS will notice 879 * and report the pre-production status, which should be enough to 880 * help us catch mistaken use of pre-production hardware. 881 */ 882 if (IS_SRIOV_VF(xe)) 883 return; 884 885 /* 886 * The "SW_CAP" fuse contains a bit indicating whether the device is a 887 * production or pre-production device. This fuse is reflected through 888 * the GT "FUSE2" register, even though the contents of the fuse are 889 * not GT-specific. Every GT's reflection of this fuse should show the 890 * same value, so we'll just use the first available GT for lookup. 891 */ 892 for_each_gt(gt, xe, id) 893 break; 894 895 if (!gt) 896 return; 897 898 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 899 if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FW_GT)) { 900 xe_gt_err(gt, "Forcewake failure; cannot determine production/pre-production hw status.\n"); 901 return; 902 } 903 904 if (xe_mmio_read32(>->mmio, FUSE2) & PRODUCTION_HW) 905 return; 906 907 xe_info(xe, "Pre-production hardware detected.\n"); 908 if (!xe->info.has_pre_prod_wa) { 909 xe_err(xe, "Pre-production workarounds for this platform have already been removed.\n"); 910 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK); 911 } 912 } 913 914 static void xe_device_wedged_fini(struct drm_device *drm, void *arg) 915 { 916 struct xe_device *xe = arg; 917 918 if (atomic_read(&xe->wedged.flag)) 919 xe_pm_runtime_put(xe); 920 } 921 922 int xe_device_probe(struct xe_device *xe) 923 { 924 struct xe_tile *tile; 925 struct xe_gt *gt; 926 int err; 927 u8 id; 928 929 xe_pat_init_early(xe); 930 931 err = xe_sriov_init(xe); 932 if (err) 933 return err; 934 935 xe->info.mem_region_mask = 1; 936 937 err = xe_set_dma_info(xe); 938 if (err) 939 return err; 940 941 err = xe_mmio_probe_tiles(xe); 942 if (err) 943 return err; 944 945 for_each_gt(gt, xe, id) { 946 err = xe_gt_init_early(gt); 947 if (err) 948 return err; 949 } 950 951 for_each_tile(tile, xe, id) { 952 err = xe_ggtt_init_early(tile->mem.ggtt); 953 if (err) 954 return err; 955 } 956 957 /* 958 * From here on, if a step fails, make sure a Driver-FLR is triggereed 959 */ 960 err = devm_add_action_or_reset(xe->drm.dev, xe_driver_flr_fini, xe); 961 if (err) 962 return err; 963 964 err = probe_has_flat_ccs(xe); 965 if (err) 966 return err; 967 968 err = xe_vram_probe(xe); 969 if (err) 970 return err; 971 972 for_each_tile(tile, xe, id) { 973 err = xe_tile_init_noalloc(tile); 974 if (err) 975 return err; 976 } 977 978 /* 979 * Allow allocations only now to ensure xe_display_init_early() 980 * is the first to allocate, always. 981 */ 982 err = xe_ttm_sys_mgr_init(xe); 983 if (err) 984 return err; 985 986 /* Allocate and map stolen after potential VRAM resize */ 987 err = xe_ttm_stolen_mgr_init(xe); 988 if (err) 989 return err; 990 991 /* 992 * Now that GT is initialized (TTM in particular), 993 * we can try to init display, and inherit the initial fb. 994 * This is the reason the first allocation needs to be done 995 * inside display. 996 */ 997 err = xe_display_init_early(xe); 998 if (err) 999 return err; 1000 1001 for_each_tile(tile, xe, id) { 1002 err = xe_tile_init(tile); 1003 if (err) 1004 return err; 1005 } 1006 1007 err = xe_irq_install(xe); 1008 if (err) 1009 return err; 1010 1011 for_each_gt(gt, xe, id) { 1012 err = xe_gt_init(gt); 1013 if (err) 1014 return err; 1015 } 1016 1017 err = xe_pagefault_init(xe); 1018 if (err) 1019 return err; 1020 1021 if (xe->tiles->media_gt && 1022 XE_GT_WA(xe->tiles->media_gt, 15015404425_disable)) 1023 XE_DEVICE_WA_DISABLE(xe, 15015404425); 1024 1025 err = xe_devcoredump_init(xe); 1026 if (err) 1027 return err; 1028 1029 xe_nvm_init(xe); 1030 1031 err = xe_soc_remapper_init(xe); 1032 if (err) 1033 return err; 1034 1035 err = xe_heci_gsc_init(xe); 1036 if (err) 1037 return err; 1038 1039 err = xe_late_bind_init(&xe->late_bind); 1040 if (err) 1041 return err; 1042 1043 err = xe_oa_init(xe); 1044 if (err) 1045 return err; 1046 1047 err = xe_display_init(xe); 1048 if (err) 1049 return err; 1050 1051 err = xe_pxp_init(xe); 1052 if (err) 1053 return err; 1054 1055 err = xe_psmi_init(xe); 1056 if (err) 1057 return err; 1058 1059 err = drm_dev_register(&xe->drm, 0); 1060 if (err) 1061 return err; 1062 1063 xe_display_register(xe); 1064 1065 err = xe_oa_register(xe); 1066 if (err) 1067 goto err_unregister_display; 1068 1069 err = xe_pmu_register(&xe->pmu); 1070 if (err) 1071 goto err_unregister_display; 1072 1073 err = xe_sysctrl_init(xe); 1074 if (err) 1075 goto err_unregister_display; 1076 1077 err = xe_device_sysfs_init(xe); 1078 if (err) 1079 goto err_unregister_display; 1080 1081 xe_debugfs_register(xe); 1082 1083 err = xe_hwmon_register(xe); 1084 if (err) 1085 goto err_unregister_display; 1086 1087 err = xe_i2c_probe(xe); 1088 if (err) 1089 goto err_unregister_display; 1090 1091 for_each_gt(gt, xe, id) 1092 xe_gt_sanitize_freq(gt); 1093 1094 xe_vsec_init(xe); 1095 1096 err = xe_sriov_init_late(xe); 1097 if (err) 1098 goto err_unregister_display; 1099 1100 detect_preproduction_hw(xe); 1101 1102 err = drmm_add_action_or_reset(&xe->drm, xe_device_wedged_fini, xe); 1103 if (err) 1104 goto err_unregister_display; 1105 1106 return devm_add_action_or_reset(xe->drm.dev, xe_device_sanitize, xe); 1107 1108 err_unregister_display: 1109 xe_display_unregister(xe); 1110 drm_dev_unregister(&xe->drm); 1111 1112 return err; 1113 } 1114 1115 void xe_device_remove(struct xe_device *xe) 1116 { 1117 xe_display_unregister(xe); 1118 1119 drm_dev_unplug(&xe->drm); 1120 1121 xe_bo_pci_dev_remove_all(xe); 1122 } 1123 1124 void xe_device_shutdown(struct xe_device *xe) 1125 { 1126 struct xe_gt *gt; 1127 u8 id; 1128 1129 drm_dbg(&xe->drm, "Shutting down device\n"); 1130 1131 xe_display_pm_shutdown(xe); 1132 1133 xe_irq_suspend(xe); 1134 1135 for_each_gt(gt, xe, id) 1136 xe_gt_shutdown(gt); 1137 1138 xe_display_pm_shutdown_late(xe); 1139 1140 if (!xe_driver_flr_disabled(xe)) { 1141 /* BOOM! */ 1142 __xe_driver_flr(xe); 1143 } 1144 } 1145 1146 /** 1147 * xe_device_wmb() - Device specific write memory barrier 1148 * @xe: the &xe_device 1149 * 1150 * While wmb() is sufficient for a barrier if we use system memory, on discrete 1151 * platforms with device memory we additionally need to issue a register write. 1152 * Since it doesn't matter which register we write to, use the read-only VF_CAP 1153 * register that is also marked as accessible by the VFs. 1154 */ 1155 void xe_device_wmb(struct xe_device *xe) 1156 { 1157 wmb(); 1158 if (IS_DGFX(xe)) 1159 xe_mmio_write32(xe_root_tile_mmio(xe), VF_CAP_REG, 0); 1160 } 1161 1162 /* 1163 * Issue a TRANSIENT_FLUSH_REQUEST and wait for completion on each gt. 1164 */ 1165 static void tdf_request_sync(struct xe_device *xe) 1166 { 1167 struct xe_gt *gt; 1168 u8 id; 1169 1170 for_each_gt_with_type(gt, xe, id, BIT(XE_GT_TYPE_MAIN)) { 1171 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 1172 if (!fw_ref.domains) 1173 return; 1174 1175 xe_mmio_write32(>->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST); 1176 1177 /* 1178 * FIXME: We can likely do better here with our choice of 1179 * timeout. Currently we just assume the worst case, i.e. 150us, 1180 * which is believed to be sufficient to cover the worst case 1181 * scenario on current platforms if all cache entries are 1182 * transient and need to be flushed.. 1183 */ 1184 if (xe_mmio_wait32(>->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0, 1185 300, NULL, false)) 1186 xe_gt_err_once(gt, "TD flush timeout\n"); 1187 } 1188 } 1189 1190 /** 1191 * xe_device_is_l2_flush_optimized - if L2 flush is optimized by HW 1192 * @xe: The device to check. 1193 * 1194 * Return: true if the HW device optimizing L2 flush, false otherwise. 1195 */ 1196 bool xe_device_is_l2_flush_optimized(struct xe_device *xe) 1197 { 1198 /* XA is *always* flushed, like at the end-of-submssion (and maybe other 1199 * places), just that internally as an optimisation hw doesn't need to make 1200 * that a full flush (which will also include XA) when Media is 1201 * off/powergated, since it doesn't need to worry about GT caches vs Media 1202 * coherency, and only CPU vs GPU coherency, so can make that flush a 1203 * targeted XA flush, since stuff tagged with XA now means it's shared with 1204 * the CPU. The main implication is that we now need to somehow flush non-XA before 1205 * freeing system memory pages, otherwise dirty cachelines could be flushed after the free 1206 * (like if Media suddenly turns on and does a full flush) 1207 */ 1208 if (GRAPHICS_VER(xe) >= 35 && !IS_DGFX(xe)) 1209 return true; 1210 return false; 1211 } 1212 1213 void xe_device_l2_flush(struct xe_device *xe) 1214 { 1215 struct xe_gt *gt; 1216 1217 gt = xe_root_mmio_gt(xe); 1218 if (!gt) 1219 return; 1220 1221 if (!XE_GT_WA(gt, 16023588340)) 1222 return; 1223 1224 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 1225 if (!fw_ref.domains) 1226 return; 1227 1228 spin_lock(>->global_invl_lock); 1229 1230 xe_mmio_write32(>->mmio, XE2_GLOBAL_INVAL, 0x1); 1231 if (xe_mmio_wait32(>->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 1000, NULL, true)) 1232 xe_gt_err_once(gt, "Global invalidation timeout\n"); 1233 1234 spin_unlock(>->global_invl_lock); 1235 } 1236 1237 /** 1238 * xe_device_td_flush() - Flush transient L3 cache entries 1239 * @xe: The device 1240 * 1241 * Display engine has direct access to memory and is never coherent with L3/L4 1242 * caches (or CPU caches), however KMD is responsible for specifically flushing 1243 * transient L3 GPU cache entries prior to the flip sequence to ensure scanout 1244 * can happen from such a surface without seeing corruption. 1245 * 1246 * Display surfaces can be tagged as transient by mapping it using one of the 1247 * various L3:XD PAT index modes on Xe2. 1248 * 1249 * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is flushed 1250 * at the end of each submission via PIPE_CONTROL for compute/render, since SA 1251 * Media is not coherent with L3 and we want to support render-vs-media 1252 * usescases. For other engines like copy/blt the HW internally forces uncached 1253 * behaviour, hence why we can skip the TDF on such platforms. 1254 */ 1255 void xe_device_td_flush(struct xe_device *xe) 1256 { 1257 struct xe_gt *root_gt; 1258 1259 /* 1260 * From Xe3p onward the HW takes care of flush of TD entries also along 1261 * with flushing XA entries, which will be at the usual sync points, 1262 * like at the end of submission, so no manual flush is needed here. 1263 */ 1264 if (GRAPHICS_VER(xe) >= 35) 1265 return; 1266 1267 if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20) 1268 return; 1269 1270 root_gt = xe_root_mmio_gt(xe); 1271 if (!root_gt) 1272 return; 1273 1274 if (XE_GT_WA(root_gt, 16023588340)) { 1275 /* A transient flush is not sufficient: flush the L2 */ 1276 xe_device_l2_flush(xe); 1277 } else { 1278 xe_guc_pc_apply_flush_freq_limit(&root_gt->uc.guc.pc); 1279 tdf_request_sync(xe); 1280 xe_guc_pc_remove_flush_freq_limit(&root_gt->uc.guc.pc); 1281 } 1282 } 1283 1284 u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size) 1285 { 1286 return xe_device_has_flat_ccs(xe) ? 1287 DIV_ROUND_UP_ULL(size, NUM_BYTES_PER_CCS_BYTE(xe)) : 0; 1288 } 1289 1290 /** 1291 * xe_device_assert_mem_access - Inspect the current runtime_pm state. 1292 * @xe: xe device instance 1293 * 1294 * To be used before any kind of memory access. It will splat a debug warning 1295 * if the device is currently sleeping. But it doesn't guarantee in any way 1296 * that the device is going to remain awake. Xe PM runtime get and put 1297 * functions might be added to the outer bound of the memory access, while 1298 * this check is intended for inner usage to splat some warning if the worst 1299 * case has just happened. 1300 */ 1301 void xe_device_assert_mem_access(struct xe_device *xe) 1302 { 1303 xe_assert(xe, !xe_pm_runtime_suspended(xe)); 1304 } 1305 1306 void xe_device_snapshot_print(struct xe_device *xe, struct drm_printer *p) 1307 { 1308 struct xe_gt *gt; 1309 u8 id; 1310 1311 drm_printf(p, "PCI ID: 0x%04x\n", xe->info.devid); 1312 drm_printf(p, "PCI revision: 0x%02x\n", xe->info.revid); 1313 1314 for_each_gt(gt, xe, id) { 1315 drm_printf(p, "GT id: %u\n", id); 1316 drm_printf(p, "\tTile: %u\n", gt->tile->id); 1317 drm_printf(p, "\tType: %s\n", 1318 gt->info.type == XE_GT_TYPE_MAIN ? "main" : "media"); 1319 drm_printf(p, "\tIP ver: %u.%u.%u\n", 1320 REG_FIELD_GET(GMD_ID_ARCH_MASK, gt->info.gmdid), 1321 REG_FIELD_GET(GMD_ID_RELEASE_MASK, gt->info.gmdid), 1322 REG_FIELD_GET(GMD_ID_REVID, gt->info.gmdid)); 1323 drm_printf(p, "\tCS reference clock: %u\n", gt->info.reference_clock); 1324 } 1325 } 1326 1327 u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address) 1328 { 1329 return sign_extend64(address, xe->info.va_bits - 1); 1330 } 1331 1332 u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address) 1333 { 1334 return address & GENMASK_ULL(xe->info.va_bits - 1, 0); 1335 } 1336 1337 /** 1338 * DOC: Xe Device Wedging 1339 * 1340 * Xe driver uses drm device wedged uevent as documented in Documentation/gpu/drm-uapi.rst. 1341 * When device is in wedged state, every IOCTL will be blocked and GT cannot 1342 * be used. The conditions under which the driver declares the device wedged 1343 * depend on the wedged mode configuration (see &enum xe_wedged_mode). The 1344 * default recovery method for a wedged state is rebind/bus-reset. 1345 * 1346 * Another recovery method is vendor-specific. Below are the cases that send 1347 * ``WEDGED=vendor-specific`` recovery method in drm device wedged uevent. 1348 * 1349 * Case: Firmware Flash 1350 * -------------------- 1351 * 1352 * Identification Hint 1353 * +++++++++++++++++++ 1354 * 1355 * ``WEDGED=vendor-specific`` drm device wedged uevent with 1356 * :ref:`Runtime Survivability mode <xe-survivability-mode>` is used to notify 1357 * admin/userspace consumer about the need for a firmware flash. 1358 * 1359 * Recovery Procedure 1360 * ++++++++++++++++++ 1361 * 1362 * Once ``WEDGED=vendor-specific`` drm device wedged uevent is received, follow 1363 * the below steps 1364 * 1365 * - Check Runtime Survivability mode sysfs. 1366 * If enabled, firmware flash is required to recover the device. 1367 * 1368 * /sys/bus/pci/devices/<device>/survivability_mode 1369 * 1370 * - Admin/userspace consumer can use firmware flashing tools like fwupd to flash 1371 * firmware and restore device to normal operation. 1372 */ 1373 1374 /** 1375 * xe_device_set_wedged_method - Set wedged recovery method 1376 * @xe: xe device instance 1377 * @method: recovery method to set 1378 * 1379 * Set wedged recovery method to be sent in drm wedged uevent. 1380 */ 1381 void xe_device_set_wedged_method(struct xe_device *xe, unsigned long method) 1382 { 1383 xe->wedged.method = method; 1384 } 1385 1386 /** 1387 * xe_device_declare_wedged - Declare device wedged 1388 * @xe: xe device instance 1389 * 1390 * This is a final state that can only be cleared with the recovery method 1391 * specified in the drm wedged uevent. The method can be set using 1392 * xe_device_set_wedged_method before declaring the device as wedged. If no method 1393 * is set, reprobe (unbind/re-bind) will be sent by default. 1394 * 1395 * In this state every IOCTL will be blocked so the GT cannot be used. 1396 * In general it will be called upon any critical error such as gt reset 1397 * failure or guc loading failure. Userspace will be notified of this state 1398 * through device wedged uevent. 1399 * If xe.wedged module parameter is set to 2, this function will be called 1400 * on every single execution timeout (a.k.a. GPU hang) right after devcoredump 1401 * snapshot capture. In this mode, GT reset won't be attempted so the state of 1402 * the issue is preserved for further debugging. 1403 */ 1404 void xe_device_declare_wedged(struct xe_device *xe) 1405 { 1406 struct xe_gt *gt; 1407 u8 id; 1408 1409 if (xe->wedged.mode == XE_WEDGED_MODE_NEVER) { 1410 drm_dbg(&xe->drm, "Wedged mode is forcibly disabled\n"); 1411 return; 1412 } 1413 1414 if (!atomic_xchg(&xe->wedged.flag, 1)) { 1415 xe->needs_flr_on_fini = true; 1416 xe_pm_runtime_get_noresume(xe); 1417 drm_err(&xe->drm, 1418 "CRITICAL: Xe has declared device %s as wedged.\n" 1419 "IOCTLs and executions are blocked.\n" 1420 "For recovery procedure, refer to https://docs.kernel.org/gpu/drm-uapi.html#device-wedging\n" 1421 "Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/xe/kernel/issues/new\n", 1422 dev_name(xe->drm.dev)); 1423 } 1424 1425 for_each_gt(gt, xe, id) 1426 xe_gt_declare_wedged(gt); 1427 1428 if (xe_device_wedged(xe)) { 1429 /* 1430 * XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET is intended for debugging 1431 * hangs, so wedge the device with 'none' recovery method and have 1432 * it available to the user for debugging. 1433 */ 1434 if (xe->wedged.mode == XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET) 1435 xe_device_set_wedged_method(xe, DRM_WEDGE_RECOVERY_NONE); 1436 /* If no wedge recovery method is set, use default */ 1437 else if (!xe->wedged.method) 1438 xe_device_set_wedged_method(xe, DRM_WEDGE_RECOVERY_REBIND | 1439 DRM_WEDGE_RECOVERY_BUS_RESET); 1440 1441 /* Notify userspace of wedged device */ 1442 drm_dev_wedged_event(&xe->drm, xe->wedged.method, NULL); 1443 } 1444 } 1445 1446 /** 1447 * xe_device_validate_wedged_mode - Check if given mode is supported 1448 * @xe: the &xe_device 1449 * @mode: requested mode to validate 1450 * 1451 * Check whether the provided wedged mode is supported. 1452 * 1453 * Return: 0 if mode is supported, error code otherwise. 1454 */ 1455 int xe_device_validate_wedged_mode(struct xe_device *xe, unsigned int mode) 1456 { 1457 if (mode > XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET) { 1458 drm_dbg(&xe->drm, "wedged_mode: invalid value (%u)\n", mode); 1459 return -EINVAL; 1460 } else if (mode == XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET && (IS_SRIOV_VF(xe) || 1461 (IS_SRIOV_PF(xe) && !IS_ENABLED(CONFIG_DRM_XE_DEBUG)))) { 1462 drm_dbg(&xe->drm, "wedged_mode: (%u) %s mode is not supported for %s\n", 1463 mode, xe_wedged_mode_to_string(mode), 1464 xe_sriov_mode_to_string(xe_device_sriov_mode(xe))); 1465 return -EPERM; 1466 } 1467 1468 return 0; 1469 } 1470 1471 /** 1472 * xe_wedged_mode_to_string - Convert enum value to string. 1473 * @mode: the &xe_wedged_mode to convert 1474 * 1475 * Returns: wedged mode as a user friendly string. 1476 */ 1477 const char *xe_wedged_mode_to_string(enum xe_wedged_mode mode) 1478 { 1479 switch (mode) { 1480 case XE_WEDGED_MODE_NEVER: 1481 return "never"; 1482 case XE_WEDGED_MODE_UPON_CRITICAL_ERROR: 1483 return "upon-critical-error"; 1484 case XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET: 1485 return "upon-any-hang-no-reset"; 1486 default: 1487 return "<invalid>"; 1488 } 1489 } 1490 1491 /** 1492 * xe_device_asid_to_vm() - Find VM from ASID 1493 * @xe: the &xe_device 1494 * @asid: Address space ID 1495 * 1496 * Find a VM from ASID and take a reference to VM which caller must drop. 1497 * Reclaim safe. 1498 * 1499 * Return: VM on success, ERR_PTR on failure 1500 */ 1501 struct xe_vm *xe_device_asid_to_vm(struct xe_device *xe, u32 asid) 1502 { 1503 struct xe_vm *vm; 1504 1505 down_read(&xe->usm.lock); 1506 vm = xa_load(&xe->usm.asid_to_vm, asid); 1507 if (vm) 1508 xe_vm_get(vm); 1509 else 1510 vm = ERR_PTR(-EINVAL); 1511 up_read(&xe->usm.lock); 1512 1513 return vm; 1514 } 1515