1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include "xe_device.h" 7 8 #include <linux/aperture.h> 9 #include <linux/delay.h> 10 #include <linux/fault-inject.h> 11 #include <linux/units.h> 12 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_client.h> 15 #include <drm/drm_gem_ttm_helper.h> 16 #include <drm/drm_ioctl.h> 17 #include <drm/drm_managed.h> 18 #include <drm/drm_print.h> 19 #include <uapi/drm/xe_drm.h> 20 21 #include "display/xe_display.h" 22 #include "instructions/xe_gpu_commands.h" 23 #include "regs/xe_gt_regs.h" 24 #include "regs/xe_regs.h" 25 #include "xe_bo.h" 26 #include "xe_bo_evict.h" 27 #include "xe_debugfs.h" 28 #include "xe_devcoredump.h" 29 #include "xe_device_sysfs.h" 30 #include "xe_dma_buf.h" 31 #include "xe_drm_client.h" 32 #include "xe_drv.h" 33 #include "xe_exec.h" 34 #include "xe_exec_queue.h" 35 #include "xe_force_wake.h" 36 #include "xe_ggtt.h" 37 #include "xe_gsc_proxy.h" 38 #include "xe_gt.h" 39 #include "xe_gt_mcr.h" 40 #include "xe_gt_printk.h" 41 #include "xe_gt_sriov_vf.h" 42 #include "xe_guc.h" 43 #include "xe_guc_pc.h" 44 #include "xe_hw_engine_group.h" 45 #include "xe_hwmon.h" 46 #include "xe_i2c.h" 47 #include "xe_irq.h" 48 #include "xe_mmio.h" 49 #include "xe_module.h" 50 #include "xe_nvm.h" 51 #include "xe_oa.h" 52 #include "xe_observation.h" 53 #include "xe_pat.h" 54 #include "xe_pcode.h" 55 #include "xe_pm.h" 56 #include "xe_pmu.h" 57 #include "xe_psmi.h" 58 #include "xe_pxp.h" 59 #include "xe_query.h" 60 #include "xe_shrinker.h" 61 #include "xe_survivability_mode.h" 62 #include "xe_sriov.h" 63 #include "xe_tile.h" 64 #include "xe_ttm_stolen_mgr.h" 65 #include "xe_ttm_sys_mgr.h" 66 #include "xe_vm.h" 67 #include "xe_vm_madvise.h" 68 #include "xe_vram.h" 69 #include "xe_vram_types.h" 70 #include "xe_vsec.h" 71 #include "xe_wait_user_fence.h" 72 #include "xe_wa.h" 73 74 #include <generated/xe_device_wa_oob.h> 75 #include <generated/xe_wa_oob.h> 76 77 static int xe_file_open(struct drm_device *dev, struct drm_file *file) 78 { 79 struct xe_device *xe = to_xe_device(dev); 80 struct xe_drm_client *client; 81 struct xe_file *xef; 82 int ret = -ENOMEM; 83 struct task_struct *task = NULL; 84 85 xef = kzalloc(sizeof(*xef), GFP_KERNEL); 86 if (!xef) 87 return ret; 88 89 client = xe_drm_client_alloc(); 90 if (!client) { 91 kfree(xef); 92 return ret; 93 } 94 95 xef->drm = file; 96 xef->client = client; 97 xef->xe = xe; 98 99 mutex_init(&xef->vm.lock); 100 xa_init_flags(&xef->vm.xa, XA_FLAGS_ALLOC1); 101 102 mutex_init(&xef->exec_queue.lock); 103 xa_init_flags(&xef->exec_queue.xa, XA_FLAGS_ALLOC1); 104 105 file->driver_priv = xef; 106 kref_init(&xef->refcount); 107 108 task = get_pid_task(rcu_access_pointer(file->pid), PIDTYPE_PID); 109 if (task) { 110 xef->process_name = kstrdup(task->comm, GFP_KERNEL); 111 xef->pid = task->pid; 112 put_task_struct(task); 113 } 114 115 return 0; 116 } 117 118 static void xe_file_destroy(struct kref *ref) 119 { 120 struct xe_file *xef = container_of(ref, struct xe_file, refcount); 121 122 xa_destroy(&xef->exec_queue.xa); 123 mutex_destroy(&xef->exec_queue.lock); 124 xa_destroy(&xef->vm.xa); 125 mutex_destroy(&xef->vm.lock); 126 127 xe_drm_client_put(xef->client); 128 kfree(xef->process_name); 129 kfree(xef); 130 } 131 132 /** 133 * xe_file_get() - Take a reference to the xe file object 134 * @xef: Pointer to the xe file 135 * 136 * Anyone with a pointer to xef must take a reference to the xe file 137 * object using this call. 138 * 139 * Return: xe file pointer 140 */ 141 struct xe_file *xe_file_get(struct xe_file *xef) 142 { 143 kref_get(&xef->refcount); 144 return xef; 145 } 146 147 /** 148 * xe_file_put() - Drop a reference to the xe file object 149 * @xef: Pointer to the xe file 150 * 151 * Used to drop reference to the xef object 152 */ 153 void xe_file_put(struct xe_file *xef) 154 { 155 kref_put(&xef->refcount, xe_file_destroy); 156 } 157 158 static void xe_file_close(struct drm_device *dev, struct drm_file *file) 159 { 160 struct xe_device *xe = to_xe_device(dev); 161 struct xe_file *xef = file->driver_priv; 162 struct xe_vm *vm; 163 struct xe_exec_queue *q; 164 unsigned long idx; 165 166 xe_pm_runtime_get(xe); 167 168 /* 169 * No need for exec_queue.lock here as there is no contention for it 170 * when FD is closing as IOCTLs presumably can't be modifying the 171 * xarray. Taking exec_queue.lock here causes undue dependency on 172 * vm->lock taken during xe_exec_queue_kill(). 173 */ 174 xa_for_each(&xef->exec_queue.xa, idx, q) { 175 if (q->vm && q->hwe->hw_engine_group) 176 xe_hw_engine_group_del_exec_queue(q->hwe->hw_engine_group, q); 177 xe_exec_queue_kill(q); 178 xe_exec_queue_put(q); 179 } 180 xa_for_each(&xef->vm.xa, idx, vm) 181 xe_vm_close_and_put(vm); 182 183 xe_file_put(xef); 184 185 xe_pm_runtime_put(xe); 186 } 187 188 static const struct drm_ioctl_desc xe_ioctls[] = { 189 DRM_IOCTL_DEF_DRV(XE_DEVICE_QUERY, xe_query_ioctl, DRM_RENDER_ALLOW), 190 DRM_IOCTL_DEF_DRV(XE_GEM_CREATE, xe_gem_create_ioctl, DRM_RENDER_ALLOW), 191 DRM_IOCTL_DEF_DRV(XE_GEM_MMAP_OFFSET, xe_gem_mmap_offset_ioctl, 192 DRM_RENDER_ALLOW), 193 DRM_IOCTL_DEF_DRV(XE_VM_CREATE, xe_vm_create_ioctl, DRM_RENDER_ALLOW), 194 DRM_IOCTL_DEF_DRV(XE_VM_DESTROY, xe_vm_destroy_ioctl, DRM_RENDER_ALLOW), 195 DRM_IOCTL_DEF_DRV(XE_VM_BIND, xe_vm_bind_ioctl, DRM_RENDER_ALLOW), 196 DRM_IOCTL_DEF_DRV(XE_EXEC, xe_exec_ioctl, DRM_RENDER_ALLOW), 197 DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_CREATE, xe_exec_queue_create_ioctl, 198 DRM_RENDER_ALLOW), 199 DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_DESTROY, xe_exec_queue_destroy_ioctl, 200 DRM_RENDER_ALLOW), 201 DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_GET_PROPERTY, xe_exec_queue_get_property_ioctl, 202 DRM_RENDER_ALLOW), 203 DRM_IOCTL_DEF_DRV(XE_WAIT_USER_FENCE, xe_wait_user_fence_ioctl, 204 DRM_RENDER_ALLOW), 205 DRM_IOCTL_DEF_DRV(XE_OBSERVATION, xe_observation_ioctl, DRM_RENDER_ALLOW), 206 DRM_IOCTL_DEF_DRV(XE_MADVISE, xe_vm_madvise_ioctl, DRM_RENDER_ALLOW), 207 DRM_IOCTL_DEF_DRV(XE_VM_QUERY_MEM_RANGE_ATTRS, xe_vm_query_vmas_attrs_ioctl, 208 DRM_RENDER_ALLOW), 209 }; 210 211 static long xe_drm_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 212 { 213 struct drm_file *file_priv = file->private_data; 214 struct xe_device *xe = to_xe_device(file_priv->minor->dev); 215 long ret; 216 217 if (xe_device_wedged(xe)) 218 return -ECANCELED; 219 220 ret = xe_pm_runtime_get_ioctl(xe); 221 if (ret >= 0) 222 ret = drm_ioctl(file, cmd, arg); 223 xe_pm_runtime_put(xe); 224 225 return ret; 226 } 227 228 #ifdef CONFIG_COMPAT 229 static long xe_drm_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 230 { 231 struct drm_file *file_priv = file->private_data; 232 struct xe_device *xe = to_xe_device(file_priv->minor->dev); 233 long ret; 234 235 if (xe_device_wedged(xe)) 236 return -ECANCELED; 237 238 ret = xe_pm_runtime_get_ioctl(xe); 239 if (ret >= 0) 240 ret = drm_compat_ioctl(file, cmd, arg); 241 xe_pm_runtime_put(xe); 242 243 return ret; 244 } 245 #else 246 /* similarly to drm_compat_ioctl, let's it be assigned to .compat_ioct unconditionally */ 247 #define xe_drm_compat_ioctl NULL 248 #endif 249 250 static void barrier_open(struct vm_area_struct *vma) 251 { 252 drm_dev_get(vma->vm_private_data); 253 } 254 255 static void barrier_close(struct vm_area_struct *vma) 256 { 257 drm_dev_put(vma->vm_private_data); 258 } 259 260 static void barrier_release_dummy_page(struct drm_device *dev, void *res) 261 { 262 struct page *dummy_page = (struct page *)res; 263 264 __free_page(dummy_page); 265 } 266 267 static vm_fault_t barrier_fault(struct vm_fault *vmf) 268 { 269 struct drm_device *dev = vmf->vma->vm_private_data; 270 struct vm_area_struct *vma = vmf->vma; 271 vm_fault_t ret = VM_FAULT_NOPAGE; 272 pgprot_t prot; 273 int idx; 274 275 prot = vm_get_page_prot(vma->vm_flags); 276 277 if (drm_dev_enter(dev, &idx)) { 278 unsigned long pfn; 279 280 #define LAST_DB_PAGE_OFFSET 0x7ff001 281 pfn = PHYS_PFN(pci_resource_start(to_pci_dev(dev->dev), 0) + 282 LAST_DB_PAGE_OFFSET); 283 ret = vmf_insert_pfn_prot(vma, vma->vm_start, pfn, 284 pgprot_noncached(prot)); 285 drm_dev_exit(idx); 286 } else { 287 struct page *page; 288 289 /* Allocate new dummy page to map all the VA range in this VMA to it*/ 290 page = alloc_page(GFP_KERNEL | __GFP_ZERO); 291 if (!page) 292 return VM_FAULT_OOM; 293 294 /* Set the page to be freed using drmm release action */ 295 if (drmm_add_action_or_reset(dev, barrier_release_dummy_page, page)) 296 return VM_FAULT_OOM; 297 298 ret = vmf_insert_pfn_prot(vma, vma->vm_start, page_to_pfn(page), 299 prot); 300 } 301 302 return ret; 303 } 304 305 static const struct vm_operations_struct vm_ops_barrier = { 306 .open = barrier_open, 307 .close = barrier_close, 308 .fault = barrier_fault, 309 }; 310 311 static int xe_pci_barrier_mmap(struct file *filp, 312 struct vm_area_struct *vma) 313 { 314 struct drm_file *priv = filp->private_data; 315 struct drm_device *dev = priv->minor->dev; 316 struct xe_device *xe = to_xe_device(dev); 317 318 if (!IS_DGFX(xe)) 319 return -EINVAL; 320 321 if (vma->vm_end - vma->vm_start > SZ_4K) 322 return -EINVAL; 323 324 if (is_cow_mapping(vma->vm_flags)) 325 return -EINVAL; 326 327 if (vma->vm_flags & (VM_READ | VM_EXEC)) 328 return -EINVAL; 329 330 vm_flags_clear(vma, VM_MAYREAD | VM_MAYEXEC); 331 vm_flags_set(vma, VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP | VM_IO); 332 vma->vm_ops = &vm_ops_barrier; 333 vma->vm_private_data = dev; 334 drm_dev_get(vma->vm_private_data); 335 336 return 0; 337 } 338 339 static int xe_mmap(struct file *filp, struct vm_area_struct *vma) 340 { 341 struct drm_file *priv = filp->private_data; 342 struct drm_device *dev = priv->minor->dev; 343 344 if (drm_dev_is_unplugged(dev)) 345 return -ENODEV; 346 347 switch (vma->vm_pgoff) { 348 case XE_PCI_BARRIER_MMAP_OFFSET >> XE_PTE_SHIFT: 349 return xe_pci_barrier_mmap(filp, vma); 350 } 351 352 return drm_gem_mmap(filp, vma); 353 } 354 355 static const struct file_operations xe_driver_fops = { 356 .owner = THIS_MODULE, 357 .open = drm_open, 358 .release = drm_release_noglobal, 359 .unlocked_ioctl = xe_drm_ioctl, 360 .mmap = xe_mmap, 361 .poll = drm_poll, 362 .read = drm_read, 363 .compat_ioctl = xe_drm_compat_ioctl, 364 .llseek = noop_llseek, 365 #ifdef CONFIG_PROC_FS 366 .show_fdinfo = drm_show_fdinfo, 367 #endif 368 .fop_flags = FOP_UNSIGNED_OFFSET, 369 }; 370 371 static struct drm_driver driver = { 372 /* Don't use MTRRs here; the Xserver or userspace app should 373 * deal with them for Intel hardware. 374 */ 375 .driver_features = 376 DRIVER_GEM | 377 DRIVER_RENDER | DRIVER_SYNCOBJ | 378 DRIVER_SYNCOBJ_TIMELINE | DRIVER_GEM_GPUVA, 379 .open = xe_file_open, 380 .postclose = xe_file_close, 381 382 .gem_prime_import = xe_gem_prime_import, 383 384 .dumb_create = xe_bo_dumb_create, 385 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 386 #ifdef CONFIG_PROC_FS 387 .show_fdinfo = xe_drm_client_fdinfo, 388 #endif 389 .ioctls = xe_ioctls, 390 .num_ioctls = ARRAY_SIZE(xe_ioctls), 391 .fops = &xe_driver_fops, 392 .name = DRIVER_NAME, 393 .desc = DRIVER_DESC, 394 .major = DRIVER_MAJOR, 395 .minor = DRIVER_MINOR, 396 .patchlevel = DRIVER_PATCHLEVEL, 397 }; 398 399 static void xe_device_destroy(struct drm_device *dev, void *dummy) 400 { 401 struct xe_device *xe = to_xe_device(dev); 402 403 xe_bo_dev_fini(&xe->bo_device); 404 405 if (xe->preempt_fence_wq) 406 destroy_workqueue(xe->preempt_fence_wq); 407 408 if (xe->ordered_wq) 409 destroy_workqueue(xe->ordered_wq); 410 411 if (xe->unordered_wq) 412 destroy_workqueue(xe->unordered_wq); 413 414 if (xe->destroy_wq) 415 destroy_workqueue(xe->destroy_wq); 416 417 ttm_device_fini(&xe->ttm); 418 } 419 420 struct xe_device *xe_device_create(struct pci_dev *pdev, 421 const struct pci_device_id *ent) 422 { 423 struct xe_device *xe; 424 int err; 425 426 xe_display_driver_set_hooks(&driver); 427 428 err = aperture_remove_conflicting_pci_devices(pdev, driver.name); 429 if (err) 430 return ERR_PTR(err); 431 432 xe = devm_drm_dev_alloc(&pdev->dev, &driver, struct xe_device, drm); 433 if (IS_ERR(xe)) 434 return xe; 435 436 err = ttm_device_init(&xe->ttm, &xe_ttm_funcs, xe->drm.dev, 437 xe->drm.anon_inode->i_mapping, 438 xe->drm.vma_offset_manager, false, false); 439 if (WARN_ON(err)) 440 goto err; 441 442 xe_bo_dev_init(&xe->bo_device); 443 err = drmm_add_action_or_reset(&xe->drm, xe_device_destroy, NULL); 444 if (err) 445 goto err; 446 447 err = xe_shrinker_create(xe); 448 if (err) 449 goto err; 450 451 xe->info.devid = pdev->device; 452 xe->info.revid = pdev->revision; 453 xe->info.force_execlist = xe_modparam.force_execlist; 454 xe->atomic_svm_timeslice_ms = 5; 455 456 err = xe_irq_init(xe); 457 if (err) 458 goto err; 459 460 init_waitqueue_head(&xe->ufence_wq); 461 462 init_rwsem(&xe->usm.lock); 463 464 xa_init_flags(&xe->usm.asid_to_vm, XA_FLAGS_ALLOC); 465 466 if (IS_ENABLED(CONFIG_DRM_XE_DEBUG)) { 467 /* Trigger a large asid and an early asid wrap. */ 468 u32 asid; 469 470 BUILD_BUG_ON(XE_MAX_ASID < 2); 471 err = xa_alloc_cyclic(&xe->usm.asid_to_vm, &asid, NULL, 472 XA_LIMIT(XE_MAX_ASID - 2, XE_MAX_ASID - 1), 473 &xe->usm.next_asid, GFP_KERNEL); 474 drm_WARN_ON(&xe->drm, err); 475 if (err >= 0) 476 xa_erase(&xe->usm.asid_to_vm, asid); 477 } 478 479 err = xe_bo_pinned_init(xe); 480 if (err) 481 goto err; 482 483 xe->preempt_fence_wq = alloc_ordered_workqueue("xe-preempt-fence-wq", 484 WQ_MEM_RECLAIM); 485 xe->ordered_wq = alloc_ordered_workqueue("xe-ordered-wq", 0); 486 xe->unordered_wq = alloc_workqueue("xe-unordered-wq", 0, 0); 487 xe->destroy_wq = alloc_workqueue("xe-destroy-wq", 0, 0); 488 if (!xe->ordered_wq || !xe->unordered_wq || 489 !xe->preempt_fence_wq || !xe->destroy_wq) { 490 /* 491 * Cleanup done in xe_device_destroy via 492 * drmm_add_action_or_reset register above 493 */ 494 drm_err(&xe->drm, "Failed to allocate xe workqueues\n"); 495 err = -ENOMEM; 496 goto err; 497 } 498 499 err = drmm_mutex_init(&xe->drm, &xe->pmt.lock); 500 if (err) 501 goto err; 502 503 return xe; 504 505 err: 506 return ERR_PTR(err); 507 } 508 ALLOW_ERROR_INJECTION(xe_device_create, ERRNO); /* See xe_pci_probe() */ 509 510 static bool xe_driver_flr_disabled(struct xe_device *xe) 511 { 512 if (IS_SRIOV_VF(xe)) 513 return true; 514 515 if (xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL_PROTECTED) & DRIVERINT_FLR_DIS) { 516 drm_info(&xe->drm, "Driver-FLR disabled by BIOS\n"); 517 return true; 518 } 519 520 return false; 521 } 522 523 /* 524 * The driver-initiated FLR is the highest level of reset that we can trigger 525 * from within the driver. It is different from the PCI FLR in that it doesn't 526 * fully reset the SGUnit and doesn't modify the PCI config space and therefore 527 * it doesn't require a re-enumeration of the PCI BARs. However, the 528 * driver-initiated FLR does still cause a reset of both GT and display and a 529 * memory wipe of local and stolen memory, so recovery would require a full HW 530 * re-init and saving/restoring (or re-populating) the wiped memory. Since we 531 * perform the FLR as the very last action before releasing access to the HW 532 * during the driver release flow, we don't attempt recovery at all, because 533 * if/when a new instance of i915 is bound to the device it will do a full 534 * re-init anyway. 535 */ 536 static void __xe_driver_flr(struct xe_device *xe) 537 { 538 const unsigned int flr_timeout = 3 * USEC_PER_SEC; /* specs recommend a 3s wait */ 539 struct xe_mmio *mmio = xe_root_tile_mmio(xe); 540 int ret; 541 542 drm_dbg(&xe->drm, "Triggering Driver-FLR\n"); 543 544 /* 545 * Make sure any pending FLR requests have cleared by waiting for the 546 * FLR trigger bit to go to zero. Also clear GU_DEBUG's DRIVERFLR_STATUS 547 * to make sure it's not still set from a prior attempt (it's a write to 548 * clear bit). 549 * Note that we should never be in a situation where a previous attempt 550 * is still pending (unless the HW is totally dead), but better to be 551 * safe in case something unexpected happens 552 */ 553 ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); 554 if (ret) { 555 drm_err(&xe->drm, "Driver-FLR-prepare wait for ready failed! %d\n", ret); 556 return; 557 } 558 xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS); 559 560 /* Trigger the actual Driver-FLR */ 561 xe_mmio_rmw32(mmio, GU_CNTL, 0, DRIVERFLR); 562 563 /* Wait for hardware teardown to complete */ 564 ret = xe_mmio_wait32(mmio, GU_CNTL, DRIVERFLR, 0, flr_timeout, NULL, false); 565 if (ret) { 566 drm_err(&xe->drm, "Driver-FLR-teardown wait completion failed! %d\n", ret); 567 return; 568 } 569 570 /* Wait for hardware/firmware re-init to complete */ 571 ret = xe_mmio_wait32(mmio, GU_DEBUG, DRIVERFLR_STATUS, DRIVERFLR_STATUS, 572 flr_timeout, NULL, false); 573 if (ret) { 574 drm_err(&xe->drm, "Driver-FLR-reinit wait completion failed! %d\n", ret); 575 return; 576 } 577 578 /* Clear sticky completion status */ 579 xe_mmio_write32(mmio, GU_DEBUG, DRIVERFLR_STATUS); 580 } 581 582 static void xe_driver_flr(struct xe_device *xe) 583 { 584 if (xe_driver_flr_disabled(xe)) 585 return; 586 587 __xe_driver_flr(xe); 588 } 589 590 static void xe_driver_flr_fini(void *arg) 591 { 592 struct xe_device *xe = arg; 593 594 if (xe->needs_flr_on_fini) 595 xe_driver_flr(xe); 596 } 597 598 static void xe_device_sanitize(void *arg) 599 { 600 struct xe_device *xe = arg; 601 struct xe_gt *gt; 602 u8 id; 603 604 for_each_gt(gt, xe, id) 605 xe_gt_sanitize(gt); 606 } 607 608 static int xe_set_dma_info(struct xe_device *xe) 609 { 610 unsigned int mask_size = xe->info.dma_mask_size; 611 int err; 612 613 dma_set_max_seg_size(xe->drm.dev, xe_sg_segment_size(xe->drm.dev)); 614 615 err = dma_set_mask(xe->drm.dev, DMA_BIT_MASK(mask_size)); 616 if (err) 617 goto mask_err; 618 619 err = dma_set_coherent_mask(xe->drm.dev, DMA_BIT_MASK(mask_size)); 620 if (err) 621 goto mask_err; 622 623 return 0; 624 625 mask_err: 626 drm_err(&xe->drm, "Can't set DMA mask/consistent mask (%d)\n", err); 627 return err; 628 } 629 630 static bool verify_lmem_ready(struct xe_device *xe) 631 { 632 u32 val = xe_mmio_read32(xe_root_tile_mmio(xe), GU_CNTL) & LMEM_INIT; 633 634 return !!val; 635 } 636 637 static int wait_for_lmem_ready(struct xe_device *xe) 638 { 639 unsigned long timeout, start; 640 641 if (!IS_DGFX(xe)) 642 return 0; 643 644 if (IS_SRIOV_VF(xe)) 645 return 0; 646 647 if (verify_lmem_ready(xe)) 648 return 0; 649 650 drm_dbg(&xe->drm, "Waiting for lmem initialization\n"); 651 652 start = jiffies; 653 timeout = start + secs_to_jiffies(60); /* 60 sec! */ 654 655 do { 656 if (signal_pending(current)) 657 return -EINTR; 658 659 /* 660 * The boot firmware initializes local memory and 661 * assesses its health. If memory training fails, 662 * the punit will have been instructed to keep the GT powered 663 * down.we won't be able to communicate with it 664 * 665 * If the status check is done before punit updates the register, 666 * it can lead to the system being unusable. 667 * use a timeout and defer the probe to prevent this. 668 */ 669 if (time_after(jiffies, timeout)) { 670 drm_dbg(&xe->drm, "lmem not initialized by firmware\n"); 671 return -EPROBE_DEFER; 672 } 673 674 msleep(20); 675 676 } while (!verify_lmem_ready(xe)); 677 678 drm_dbg(&xe->drm, "lmem ready after %ums", 679 jiffies_to_msecs(jiffies - start)); 680 681 return 0; 682 } 683 ALLOW_ERROR_INJECTION(wait_for_lmem_ready, ERRNO); /* See xe_pci_probe() */ 684 685 static void sriov_update_device_info(struct xe_device *xe) 686 { 687 /* disable features that are not available/applicable to VFs */ 688 if (IS_SRIOV_VF(xe)) { 689 xe->info.probe_display = 0; 690 xe->info.has_heci_cscfi = 0; 691 xe->info.has_heci_gscfi = 0; 692 xe->info.skip_guc_pc = 1; 693 xe->info.skip_pcode = 1; 694 } 695 } 696 697 static int xe_device_vram_alloc(struct xe_device *xe) 698 { 699 struct xe_vram_region *vram; 700 701 if (!IS_DGFX(xe)) 702 return 0; 703 704 vram = drmm_kzalloc(&xe->drm, sizeof(*vram), GFP_KERNEL); 705 if (!vram) 706 return -ENOMEM; 707 708 xe->mem.vram = vram; 709 return 0; 710 } 711 712 /** 713 * xe_device_probe_early: Device early probe 714 * @xe: xe device instance 715 * 716 * Initialize MMIO resources that don't require any 717 * knowledge about tile count. Also initialize pcode and 718 * check vram initialization on root tile. 719 * 720 * Return: 0 on success, error code on failure 721 */ 722 int xe_device_probe_early(struct xe_device *xe) 723 { 724 int err; 725 726 xe_wa_device_init(xe); 727 xe_wa_process_device_oob(xe); 728 729 err = xe_mmio_probe_early(xe); 730 if (err) 731 return err; 732 733 xe_sriov_probe_early(xe); 734 735 sriov_update_device_info(xe); 736 737 err = xe_pcode_probe_early(xe); 738 if (err || xe_survivability_mode_is_requested(xe)) { 739 int save_err = err; 740 741 /* 742 * Try to leave device in survivability mode if device is 743 * possible, but still return the previous error for error 744 * propagation 745 */ 746 err = xe_survivability_mode_boot_enable(xe); 747 if (err) 748 return err; 749 750 return save_err; 751 } 752 753 err = wait_for_lmem_ready(xe); 754 if (err) 755 return err; 756 757 xe->wedged.mode = xe_modparam.wedged_mode; 758 759 err = xe_device_vram_alloc(xe); 760 if (err) 761 return err; 762 763 return 0; 764 } 765 ALLOW_ERROR_INJECTION(xe_device_probe_early, ERRNO); /* See xe_pci_probe() */ 766 767 static int probe_has_flat_ccs(struct xe_device *xe) 768 { 769 struct xe_gt *gt; 770 unsigned int fw_ref; 771 u32 reg; 772 773 /* Always enabled/disabled, no runtime check to do */ 774 if (GRAPHICS_VER(xe) < 20 || !xe->info.has_flat_ccs || IS_SRIOV_VF(xe)) 775 return 0; 776 777 gt = xe_root_mmio_gt(xe); 778 779 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 780 if (!fw_ref) 781 return -ETIMEDOUT; 782 783 reg = xe_gt_mcr_unicast_read_any(gt, XE2_FLAT_CCS_BASE_RANGE_LOWER); 784 xe->info.has_flat_ccs = (reg & XE2_FLAT_CCS_ENABLE); 785 786 if (!xe->info.has_flat_ccs) 787 drm_dbg(&xe->drm, 788 "Flat CCS has been disabled in bios, May lead to performance impact"); 789 790 xe_force_wake_put(gt_to_fw(gt), fw_ref); 791 792 return 0; 793 } 794 795 int xe_device_probe(struct xe_device *xe) 796 { 797 struct xe_tile *tile; 798 struct xe_gt *gt; 799 int err; 800 u8 id; 801 802 xe_pat_init_early(xe); 803 804 err = xe_sriov_init(xe); 805 if (err) 806 return err; 807 808 xe->info.mem_region_mask = 1; 809 810 err = xe_set_dma_info(xe); 811 if (err) 812 return err; 813 814 err = xe_mmio_probe_tiles(xe); 815 if (err) 816 return err; 817 818 for_each_gt(gt, xe, id) { 819 err = xe_gt_init_early(gt); 820 if (err) 821 return err; 822 } 823 824 for_each_tile(tile, xe, id) { 825 err = xe_ggtt_init_early(tile->mem.ggtt); 826 if (err) 827 return err; 828 } 829 830 /* 831 * From here on, if a step fails, make sure a Driver-FLR is triggereed 832 */ 833 err = devm_add_action_or_reset(xe->drm.dev, xe_driver_flr_fini, xe); 834 if (err) 835 return err; 836 837 err = probe_has_flat_ccs(xe); 838 if (err) 839 return err; 840 841 err = xe_vram_probe(xe); 842 if (err) 843 return err; 844 845 for_each_tile(tile, xe, id) { 846 err = xe_tile_init_noalloc(tile); 847 if (err) 848 return err; 849 } 850 851 /* 852 * Allow allocations only now to ensure xe_display_init_early() 853 * is the first to allocate, always. 854 */ 855 err = xe_ttm_sys_mgr_init(xe); 856 if (err) 857 return err; 858 859 /* Allocate and map stolen after potential VRAM resize */ 860 err = xe_ttm_stolen_mgr_init(xe); 861 if (err) 862 return err; 863 864 /* 865 * Now that GT is initialized (TTM in particular), 866 * we can try to init display, and inherit the initial fb. 867 * This is the reason the first allocation needs to be done 868 * inside display. 869 */ 870 err = xe_display_init_early(xe); 871 if (err) 872 return err; 873 874 for_each_tile(tile, xe, id) { 875 err = xe_tile_init(tile); 876 if (err) 877 return err; 878 } 879 880 err = xe_irq_install(xe); 881 if (err) 882 return err; 883 884 for_each_gt(gt, xe, id) { 885 err = xe_gt_init(gt); 886 if (err) 887 return err; 888 } 889 890 if (xe->tiles->media_gt && 891 XE_GT_WA(xe->tiles->media_gt, 15015404425_disable)) 892 XE_DEVICE_WA_DISABLE(xe, 15015404425); 893 894 err = xe_devcoredump_init(xe); 895 if (err) 896 return err; 897 898 xe_nvm_init(xe); 899 900 err = xe_heci_gsc_init(xe); 901 if (err) 902 return err; 903 904 err = xe_oa_init(xe); 905 if (err) 906 return err; 907 908 err = xe_display_init(xe); 909 if (err) 910 return err; 911 912 err = xe_pxp_init(xe); 913 if (err) 914 return err; 915 916 err = xe_psmi_init(xe); 917 if (err) 918 return err; 919 920 err = drm_dev_register(&xe->drm, 0); 921 if (err) 922 return err; 923 924 xe_display_register(xe); 925 926 err = xe_oa_register(xe); 927 if (err) 928 goto err_unregister_display; 929 930 err = xe_pmu_register(&xe->pmu); 931 if (err) 932 goto err_unregister_display; 933 934 err = xe_device_sysfs_init(xe); 935 if (err) 936 goto err_unregister_display; 937 938 xe_debugfs_register(xe); 939 940 err = xe_hwmon_register(xe); 941 if (err) 942 goto err_unregister_display; 943 944 err = xe_i2c_probe(xe); 945 if (err) 946 goto err_unregister_display; 947 948 for_each_gt(gt, xe, id) 949 xe_gt_sanitize_freq(gt); 950 951 xe_vsec_init(xe); 952 953 err = xe_sriov_late_init(xe); 954 if (err) 955 goto err_unregister_display; 956 957 return devm_add_action_or_reset(xe->drm.dev, xe_device_sanitize, xe); 958 959 err_unregister_display: 960 xe_display_unregister(xe); 961 962 return err; 963 } 964 965 void xe_device_remove(struct xe_device *xe) 966 { 967 xe_display_unregister(xe); 968 969 xe_nvm_fini(xe); 970 971 drm_dev_unplug(&xe->drm); 972 973 xe_bo_pci_dev_remove_all(xe); 974 } 975 976 void xe_device_shutdown(struct xe_device *xe) 977 { 978 struct xe_gt *gt; 979 u8 id; 980 981 drm_dbg(&xe->drm, "Shutting down device\n"); 982 983 if (xe_driver_flr_disabled(xe)) { 984 xe_display_pm_shutdown(xe); 985 986 xe_irq_suspend(xe); 987 988 for_each_gt(gt, xe, id) 989 xe_gt_shutdown(gt); 990 991 xe_display_pm_shutdown_late(xe); 992 } else { 993 /* BOOM! */ 994 __xe_driver_flr(xe); 995 } 996 } 997 998 /** 999 * xe_device_wmb() - Device specific write memory barrier 1000 * @xe: the &xe_device 1001 * 1002 * While wmb() is sufficient for a barrier if we use system memory, on discrete 1003 * platforms with device memory we additionally need to issue a register write. 1004 * Since it doesn't matter which register we write to, use the read-only VF_CAP 1005 * register that is also marked as accessible by the VFs. 1006 */ 1007 void xe_device_wmb(struct xe_device *xe) 1008 { 1009 wmb(); 1010 if (IS_DGFX(xe)) 1011 xe_mmio_write32(xe_root_tile_mmio(xe), VF_CAP_REG, 0); 1012 } 1013 1014 /* 1015 * Issue a TRANSIENT_FLUSH_REQUEST and wait for completion on each gt. 1016 */ 1017 static void tdf_request_sync(struct xe_device *xe) 1018 { 1019 unsigned int fw_ref; 1020 struct xe_gt *gt; 1021 u8 id; 1022 1023 for_each_gt(gt, xe, id) { 1024 if (xe_gt_is_media_type(gt)) 1025 continue; 1026 1027 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1028 if (!fw_ref) 1029 return; 1030 1031 xe_mmio_write32(>->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST); 1032 1033 /* 1034 * FIXME: We can likely do better here with our choice of 1035 * timeout. Currently we just assume the worst case, i.e. 150us, 1036 * which is believed to be sufficient to cover the worst case 1037 * scenario on current platforms if all cache entries are 1038 * transient and need to be flushed.. 1039 */ 1040 if (xe_mmio_wait32(>->mmio, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0, 1041 150, NULL, false)) 1042 xe_gt_err_once(gt, "TD flush timeout\n"); 1043 1044 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1045 } 1046 } 1047 1048 void xe_device_l2_flush(struct xe_device *xe) 1049 { 1050 struct xe_gt *gt; 1051 unsigned int fw_ref; 1052 1053 gt = xe_root_mmio_gt(xe); 1054 1055 if (!XE_GT_WA(gt, 16023588340)) 1056 return; 1057 1058 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1059 if (!fw_ref) 1060 return; 1061 1062 spin_lock(>->global_invl_lock); 1063 1064 xe_mmio_write32(>->mmio, XE2_GLOBAL_INVAL, 0x1); 1065 if (xe_mmio_wait32(>->mmio, XE2_GLOBAL_INVAL, 0x1, 0x0, 500, NULL, true)) 1066 xe_gt_err_once(gt, "Global invalidation timeout\n"); 1067 1068 spin_unlock(>->global_invl_lock); 1069 1070 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1071 } 1072 1073 /** 1074 * xe_device_td_flush() - Flush transient L3 cache entries 1075 * @xe: The device 1076 * 1077 * Display engine has direct access to memory and is never coherent with L3/L4 1078 * caches (or CPU caches), however KMD is responsible for specifically flushing 1079 * transient L3 GPU cache entries prior to the flip sequence to ensure scanout 1080 * can happen from such a surface without seeing corruption. 1081 * 1082 * Display surfaces can be tagged as transient by mapping it using one of the 1083 * various L3:XD PAT index modes on Xe2. 1084 * 1085 * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is flushed 1086 * at the end of each submission via PIPE_CONTROL for compute/render, since SA 1087 * Media is not coherent with L3 and we want to support render-vs-media 1088 * usescases. For other engines like copy/blt the HW internally forces uncached 1089 * behaviour, hence why we can skip the TDF on such platforms. 1090 */ 1091 void xe_device_td_flush(struct xe_device *xe) 1092 { 1093 struct xe_gt *root_gt; 1094 1095 if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20) 1096 return; 1097 1098 root_gt = xe_root_mmio_gt(xe); 1099 if (XE_GT_WA(root_gt, 16023588340)) { 1100 /* A transient flush is not sufficient: flush the L2 */ 1101 xe_device_l2_flush(xe); 1102 } else { 1103 xe_guc_pc_apply_flush_freq_limit(&root_gt->uc.guc.pc); 1104 tdf_request_sync(xe); 1105 xe_guc_pc_remove_flush_freq_limit(&root_gt->uc.guc.pc); 1106 } 1107 } 1108 1109 u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size) 1110 { 1111 return xe_device_has_flat_ccs(xe) ? 1112 DIV_ROUND_UP_ULL(size, NUM_BYTES_PER_CCS_BYTE(xe)) : 0; 1113 } 1114 1115 /** 1116 * xe_device_assert_mem_access - Inspect the current runtime_pm state. 1117 * @xe: xe device instance 1118 * 1119 * To be used before any kind of memory access. It will splat a debug warning 1120 * if the device is currently sleeping. But it doesn't guarantee in any way 1121 * that the device is going to remain awake. Xe PM runtime get and put 1122 * functions might be added to the outer bound of the memory access, while 1123 * this check is intended for inner usage to splat some warning if the worst 1124 * case has just happened. 1125 */ 1126 void xe_device_assert_mem_access(struct xe_device *xe) 1127 { 1128 xe_assert(xe, !xe_pm_runtime_suspended(xe)); 1129 } 1130 1131 void xe_device_snapshot_print(struct xe_device *xe, struct drm_printer *p) 1132 { 1133 struct xe_gt *gt; 1134 u8 id; 1135 1136 drm_printf(p, "PCI ID: 0x%04x\n", xe->info.devid); 1137 drm_printf(p, "PCI revision: 0x%02x\n", xe->info.revid); 1138 1139 for_each_gt(gt, xe, id) { 1140 drm_printf(p, "GT id: %u\n", id); 1141 drm_printf(p, "\tTile: %u\n", gt->tile->id); 1142 drm_printf(p, "\tType: %s\n", 1143 gt->info.type == XE_GT_TYPE_MAIN ? "main" : "media"); 1144 drm_printf(p, "\tIP ver: %u.%u.%u\n", 1145 REG_FIELD_GET(GMD_ID_ARCH_MASK, gt->info.gmdid), 1146 REG_FIELD_GET(GMD_ID_RELEASE_MASK, gt->info.gmdid), 1147 REG_FIELD_GET(GMD_ID_REVID, gt->info.gmdid)); 1148 drm_printf(p, "\tCS reference clock: %u\n", gt->info.reference_clock); 1149 } 1150 } 1151 1152 u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address) 1153 { 1154 return sign_extend64(address, xe->info.va_bits - 1); 1155 } 1156 1157 u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address) 1158 { 1159 return address & GENMASK_ULL(xe->info.va_bits - 1, 0); 1160 } 1161 1162 static void xe_device_wedged_fini(struct drm_device *drm, void *arg) 1163 { 1164 struct xe_device *xe = arg; 1165 1166 xe_pm_runtime_put(xe); 1167 } 1168 1169 /** 1170 * DOC: Xe Device Wedging 1171 * 1172 * Xe driver uses drm device wedged uevent as documented in Documentation/gpu/drm-uapi.rst. 1173 * When device is in wedged state, every IOCTL will be blocked and GT cannot be 1174 * used. Certain critical errors like gt reset failure, firmware failures can cause 1175 * the device to be wedged. The default recovery method for a wedged state 1176 * is rebind/bus-reset. 1177 * 1178 * Another recovery method is vendor-specific. Below are the cases that send 1179 * ``WEDGED=vendor-specific`` recovery method in drm device wedged uevent. 1180 * 1181 * Case: Firmware Flash 1182 * -------------------- 1183 * 1184 * Identification Hint 1185 * +++++++++++++++++++ 1186 * 1187 * ``WEDGED=vendor-specific`` drm device wedged uevent with 1188 * :ref:`Runtime Survivability mode <xe-survivability-mode>` is used to notify 1189 * admin/userspace consumer about the need for a firmware flash. 1190 * 1191 * Recovery Procedure 1192 * ++++++++++++++++++ 1193 * 1194 * Once ``WEDGED=vendor-specific`` drm device wedged uevent is received, follow 1195 * the below steps 1196 * 1197 * - Check Runtime Survivability mode sysfs. 1198 * If enabled, firmware flash is required to recover the device. 1199 * 1200 * /sys/bus/pci/devices/<device>/survivability_mode 1201 * 1202 * - Admin/userpsace consumer can use firmware flashing tools like fwupd to flash 1203 * firmware and restore device to normal operation. 1204 */ 1205 1206 /** 1207 * xe_device_set_wedged_method - Set wedged recovery method 1208 * @xe: xe device instance 1209 * @method: recovery method to set 1210 * 1211 * Set wedged recovery method to be sent in drm wedged uevent. 1212 */ 1213 void xe_device_set_wedged_method(struct xe_device *xe, unsigned long method) 1214 { 1215 xe->wedged.method = method; 1216 } 1217 1218 /** 1219 * xe_device_declare_wedged - Declare device wedged 1220 * @xe: xe device instance 1221 * 1222 * This is a final state that can only be cleared with the recovery method 1223 * specified in the drm wedged uevent. The method can be set using 1224 * xe_device_set_wedged_method before declaring the device as wedged. If no method 1225 * is set, reprobe (unbind/re-bind) will be sent by default. 1226 * 1227 * In this state every IOCTL will be blocked so the GT cannot be used. 1228 * In general it will be called upon any critical error such as gt reset 1229 * failure or guc loading failure. Userspace will be notified of this state 1230 * through device wedged uevent. 1231 * If xe.wedged module parameter is set to 2, this function will be called 1232 * on every single execution timeout (a.k.a. GPU hang) right after devcoredump 1233 * snapshot capture. In this mode, GT reset won't be attempted so the state of 1234 * the issue is preserved for further debugging. 1235 */ 1236 void xe_device_declare_wedged(struct xe_device *xe) 1237 { 1238 struct xe_gt *gt; 1239 u8 id; 1240 1241 if (xe->wedged.mode == 0) { 1242 drm_dbg(&xe->drm, "Wedged mode is forcibly disabled\n"); 1243 return; 1244 } 1245 1246 xe_pm_runtime_get_noresume(xe); 1247 1248 if (drmm_add_action_or_reset(&xe->drm, xe_device_wedged_fini, xe)) { 1249 drm_err(&xe->drm, "Failed to register xe_device_wedged_fini clean-up. Although device is wedged.\n"); 1250 return; 1251 } 1252 1253 if (!atomic_xchg(&xe->wedged.flag, 1)) { 1254 xe->needs_flr_on_fini = true; 1255 drm_err(&xe->drm, 1256 "CRITICAL: Xe has declared device %s as wedged.\n" 1257 "IOCTLs and executions are blocked. Only a rebind may clear the failure\n" 1258 "Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/xe/kernel/issues/new\n", 1259 dev_name(xe->drm.dev)); 1260 } 1261 1262 for_each_gt(gt, xe, id) 1263 xe_gt_declare_wedged(gt); 1264 1265 if (xe_device_wedged(xe)) { 1266 /* If no wedge recovery method is set, use default */ 1267 if (!xe->wedged.method) 1268 xe_device_set_wedged_method(xe, DRM_WEDGE_RECOVERY_REBIND | 1269 DRM_WEDGE_RECOVERY_BUS_RESET); 1270 1271 /* Notify userspace of wedged device */ 1272 drm_dev_wedged_event(&xe->drm, xe->wedged.method, NULL); 1273 } 1274 } 1275