1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2026 Intel Corporation 4 */ 5 6 #ifndef _XE_SYSCTRL_REGS_H_ 7 #define _XE_SYSCTRL_REGS_H_ 8 9 #include "xe_regs.h" 10 11 #define SYSCTRL_BASE_OFFSET 0xdb000 12 #define SYSCTRL_BASE (SOC_BASE + SYSCTRL_BASE_OFFSET) 13 #define SYSCTRL_MAILBOX_INDEX 0x03 14 #define SYSCTRL_BAR_LENGTH 0x1000 15 16 #define SYSCTRL_MB_CTRL XE_REG(0x10) 17 #define SYSCTRL_MB_CTRL_RUN_BUSY REG_BIT(31) 18 #define SYSCTRL_MB_CTRL_IRQ REG_BIT(30) 19 #define SYSCTRL_MB_CTRL_RUN_BUSY_OUT REG_BIT(29) 20 #define SYSCTRL_MB_CTRL_PARAM3_MASK REG_GENMASK(28, 24) 21 #define SYSCTRL_MB_CTRL_PARAM2_MASK REG_GENMASK(23, 16) 22 #define SYSCTRL_MB_CTRL_PARAM1_MASK REG_GENMASK(15, 8) 23 #define SYSCTRL_MB_CTRL_COMMAND_MASK REG_GENMASK(7, 0) 24 #define SYSCTRL_MB_CTRL_CMD REG_FIELD_PREP(SYSCTRL_MB_CTRL_COMMAND_MASK, 5) 25 26 #define SYSCTRL_MB_DATA0 XE_REG(0x14) 27 #define SYSCTRL_MB_DATA1 XE_REG(0x18) 28 #define SYSCTRL_MB_DATA2 XE_REG(0x1c) 29 #define SYSCTRL_MB_DATA3 XE_REG(0x20) 30 31 #define SYSCTRL_FRAME_PHASE REG_BIT(24) 32 #define SYSCTRL_FRAME_CURRENT_MASK REG_GENMASK(21, 16) 33 #define SYSCTRL_FRAME_TOTAL_MASK REG_GENMASK(13, 8) 34 #define SYSCTRL_FRAME_COMMAND_MASK REG_GENMASK(7, 0) 35 36 #endif 37