1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 #ifndef _XE_REGS_H_ 6 #define _XE_REGS_H_ 7 8 #include "regs/xe_reg_defs.h" 9 10 #define TIMESTAMP_OVERRIDE XE_REG(0x44074) 11 #define TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK REG_GENMASK(15, 12) 12 #define TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK REG_GENMASK(9, 0) 13 14 #define PCU_IRQ_OFFSET 0x444e0 15 #define GU_MISC_IRQ_OFFSET 0x444f0 16 #define GU_MISC_GSE REG_BIT(27) 17 18 #define SOFTWARE_FLAGS_SPR33 XE_REG(0x4f084) 19 20 #define GU_CNTL_PROTECTED XE_REG(0x10100C) 21 #define DRIVERINT_FLR_DIS REG_BIT(31) 22 23 #define GU_CNTL XE_REG(0x101010) 24 #define LMEM_INIT REG_BIT(7) 25 #define DRIVERFLR REG_BIT(31) 26 27 #define GU_DEBUG XE_REG(0x101018) 28 #define DRIVERFLR_STATUS REG_BIT(31) 29 30 #define XEHP_CLOCK_GATE_DIS XE_REG(0x101014) 31 #define SGSI_SIDECLK_DIS REG_BIT(17) 32 33 #define XEHP_MTCFG_ADDR XE_REG(0x101800) 34 #define TILE_COUNT REG_GENMASK(15, 8) 35 36 #define GGC XE_REG(0x108040) 37 #define GMS_MASK REG_GENMASK(15, 8) 38 #define GGMS_MASK REG_GENMASK(7, 6) 39 40 #define DSMBASE XE_REG(0x1080C0) 41 #define BDSM_MASK REG_GENMASK64(63, 20) 42 43 #define GSMBASE XE_REG(0x108100) 44 45 #define STOLEN_RESERVED XE_REG(0x1082c0) 46 #define WOPCM_SIZE_MASK REG_GENMASK64(9, 7) 47 48 #define MTL_RP_STATE_CAP XE_REG(0x138000) 49 50 #define MTL_GT_RPE_FREQUENCY XE_REG(0x13800c) 51 52 #define MTL_MEDIAP_STATE_CAP XE_REG(0x138020) 53 #define MTL_RPN_CAP_MASK REG_GENMASK(24, 16) 54 #define MTL_RP0_CAP_MASK REG_GENMASK(8, 0) 55 56 #define MTL_MPE_FREQUENCY XE_REG(0x13802c) 57 #define MTL_RPE_MASK REG_GENMASK(8, 0) 58 59 #define DG1_MSTR_TILE_INTR XE_REG(0x190008) 60 #define DG1_MSTR_IRQ REG_BIT(31) 61 #define DG1_MSTR_TILE(t) REG_BIT(t) 62 63 #define GFX_MSTR_IRQ XE_REG(0x190010, XE_REG_OPTION_VF) 64 #define MASTER_IRQ REG_BIT(31) 65 #define GU_MISC_IRQ REG_BIT(29) 66 #define DISPLAY_IRQ REG_BIT(16) 67 #define GT_DW_IRQ(x) REG_BIT(x) 68 69 #define PVC_RP_STATE_CAP XE_REG(0x281014) 70 71 #endif 72