xref: /linux/drivers/gpu/drm/xe/regs/xe_reg_defs.h (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #ifndef _XE_REG_DEFS_H_
7 #define _XE_REG_DEFS_H_
8 
9 #include <drm/intel/pick.h>
10 #include <drm/intel/reg_bits.h>
11 
12 #include <linux/build_bug.h>
13 #include <linux/log2.h>
14 #include <linux/sizes.h>
15 
16 /**
17  * XE_REG_ADDR_MAX - The upper limit on MMIO register address
18  *
19  * This macro specifies the upper limit (not inclusive) on MMIO register offset
20  * supported by struct xe_reg and functions based on struct xe_mmio.
21  *
22  * Currently this is defined as 4 MiB.
23  */
24 #define XE_REG_ADDR_MAX	SZ_4M
25 
26 /**
27  * struct xe_reg - Register definition
28  *
29  * Register definition to be used by the individual register. Although the same
30  * definition is used for xe_reg and xe_reg_mcr, they use different internal
31  * APIs for accesses.
32  */
33 struct xe_reg {
34 	union {
35 		struct {
36 			/** @addr: address */
37 			u32 addr:const_ilog2(XE_REG_ADDR_MAX);
38 			/**
39 			 * @masked: register is "masked", with upper 16bits used
40 			 * to identify the bits that are updated on the lower
41 			 * bits
42 			 */
43 			u32 masked:1;
44 			/**
45 			 * @mcr: register is multicast/replicated in the
46 			 * hardware and needs special handling. Any register
47 			 * with this set should also use a type of xe_reg_mcr_t.
48 			 * It's only here so the few places that deal with MCR
49 			 * registers specially (xe_sr.c) and tests using the raw
50 			 * value can inspect it.
51 			 */
52 			u32 mcr:1;
53 			/**
54 			 * @vf: register is accessible from the Virtual Function.
55 			 */
56 			u32 vf:1;
57 		};
58 		/** @raw: Raw value with both address and options */
59 		u32 raw;
60 	};
61 };
62 static_assert(sizeof(struct xe_reg) == sizeof(u32));
63 
64 /**
65  * struct xe_reg_mcr - MCR register definition
66  *
67  * MCR register is the same as a regular register, but uses another type since
68  * the internal API used for accessing them is different: it's never correct to
69  * use regular MMIO access.
70  */
71 struct xe_reg_mcr {
72 	/** @__reg: The register */
73 	struct xe_reg __reg;
74 };
75 
76 
77 /**
78  * XE_REG_OPTION_MASKED - Register is "masked", with upper 16 bits marking the
79  * written bits on the lower 16 bits.
80  *
81  * It only applies to registers explicitly marked in bspec with
82  * "Access: Masked". Registers with this option can have write operations to
83  * specific lower bits by setting the corresponding upper bits. Other bits will
84  * not be affected. This allows register writes without needing a RMW cycle and
85  * without caching in software the register value.
86  *
87  * Example: a write with value 0x00010001 will set bit 0 and all other bits
88  * retain their previous values.
89  *
90  * To be used with XE_REG(). XE_REG_MCR() and XE_REG_INITIALIZER()
91  */
92 #define XE_REG_OPTION_MASKED		.masked = 1
93 
94 /**
95  * XE_REG_OPTION_VF - Register is "VF" accessible.
96  *
97  * To be used with XE_REG() and XE_REG_INITIALIZER().
98  */
99 #define XE_REG_OPTION_VF		.vf = 1
100 
101 /**
102  * XE_REG_INITIALIZER - Initializer for xe_reg_t.
103  * @r_: Register offset
104  * @...: Additional options like access mode. See struct xe_reg for available
105  *       options.
106  *
107  * Register field is mandatory, and additional options may be passed as
108  * arguments. Usually ``XE_REG()`` should be preferred since it creates an
109  * object of the right type. However when initializing static const storage,
110  * where a compound statement is not allowed, this can be used instead.
111  */
112 #define XE_REG_INITIALIZER(r_, ...)    { .addr = r_, __VA_ARGS__ }
113 
114 
115 /**
116  * XE_REG - Create a struct xe_reg from offset and additional flags
117  * @r_: Register offset
118  * @...: Additional options like access mode. See struct xe_reg for available
119  *       options.
120  */
121 #define XE_REG(r_, ...)		((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__))
122 
123 /**
124  * XE_REG_MCR - Create a struct xe_reg_mcr from offset and additional flags
125  * @r_: Register offset
126  * @...: Additional options like access mode. See struct xe_reg for available
127  *       options.
128  */
129 #define XE_REG_MCR(r_, ...)	((const struct xe_reg_mcr){					\
130 				 .__reg = XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .mcr = 1)	\
131 				 })
132 
133 static inline bool xe_reg_is_valid(struct xe_reg r)
134 {
135 	return r.addr;
136 }
137 
138 #endif
139