1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __XE_OA_REGS__ 7 #define __XE_OA_REGS__ 8 9 #define RPM_CONFIG1 XE_REG(0xd04) 10 #define GT_NOA_ENABLE REG_BIT(9) 11 12 #define EU_PERF_CNTL0 XE_REG(0xe458) 13 #define EU_PERF_CNTL4 XE_REG(0xe45c) 14 #define EU_PERF_CNTL1 XE_REG(0xe558) 15 #define EU_PERF_CNTL5 XE_REG(0xe55c) 16 #define EU_PERF_CNTL2 XE_REG(0xe658) 17 #define EU_PERF_CNTL6 XE_REG(0xe65c) 18 #define EU_PERF_CNTL3 XE_REG(0xe758) 19 20 #define OA_TLB_INV_CR XE_REG(0xceec) 21 22 /* OAR unit */ 23 #define OAR_OACONTROL XE_REG(0x2960) 24 #define OAR_OACONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1) 25 #define OAR_OACONTROL_COUNTER_ENABLE REG_BIT(0) 26 27 #define OACTXCONTROL(base) XE_REG((base) + 0x360) 28 #define OAR_OASTATUS XE_REG(0x2968) 29 #define OA_COUNTER_RESUME REG_BIT(0) 30 31 /* OAG unit */ 32 #define OAG_OAGLBCTXCTRL XE_REG(0x2b28) 33 #define OAG_OAGLBCTXCTRL_TIMER_PERIOD_MASK REG_GENMASK(7, 2) 34 #define OAG_OAGLBCTXCTRL_TIMER_ENABLE REG_BIT(1) 35 #define OAG_OAGLBCTXCTRL_COUNTER_RESUME REG_BIT(0) 36 37 #define OAG_OAHEADPTR XE_REG(0xdb00) 38 #define OAG_OAHEADPTR_MASK REG_GENMASK(31, 6) 39 #define OAG_OATAILPTR XE_REG(0xdb04) 40 #define OAG_OATAILPTR_MASK REG_GENMASK(31, 6) 41 42 #define OAG_OABUFFER XE_REG(0xdb08) 43 #define OABUFFER_SIZE_MASK REG_GENMASK(5, 3) 44 #define OABUFFER_SIZE_128K REG_FIELD_PREP(OABUFFER_SIZE_MASK, 0) 45 #define OABUFFER_SIZE_256K REG_FIELD_PREP(OABUFFER_SIZE_MASK, 1) 46 #define OABUFFER_SIZE_512K REG_FIELD_PREP(OABUFFER_SIZE_MASK, 2) 47 #define OABUFFER_SIZE_1M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 3) 48 #define OABUFFER_SIZE_2M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 4) 49 #define OABUFFER_SIZE_4M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 5) 50 #define OABUFFER_SIZE_8M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 6) 51 #define OABUFFER_SIZE_16M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 7) 52 #define OAG_OABUFFER_MEMORY_SELECT REG_BIT(0) /* 0: PPGTT, 1: GGTT */ 53 54 #define OAG_OACONTROL XE_REG(0xdaf4) 55 #define OAG_OACONTROL_OA_CCS_SELECT_MASK REG_GENMASK(18, 16) 56 #define OAG_OACONTROL_OA_COUNTER_SEL_MASK REG_GENMASK(4, 2) 57 #define OAG_OACONTROL_OA_COUNTER_ENABLE REG_BIT(0) 58 /* Common to all OA units */ 59 #define OA_OACONTROL_REPORT_BC_MASK REG_GENMASK(9, 9) 60 #define OA_OACONTROL_COUNTER_SIZE_MASK REG_GENMASK(8, 8) 61 62 #define OAG_OA_DEBUG XE_REG(0xdaf8, XE_REG_OPTION_MASKED) 63 #define OAG_OA_DEBUG_DISABLE_MMIO_TRG REG_BIT(14) 64 #define OAG_OA_DEBUG_START_TRIGGER_SCOPE_CONTROL REG_BIT(13) 65 #define OAG_OA_DEBUG_DISABLE_START_TRG_2_COUNT_QUAL REG_BIT(8) 66 #define OAG_OA_DEBUG_DISABLE_START_TRG_1_COUNT_QUAL REG_BIT(7) 67 #define OAG_OA_DEBUG_INCLUDE_CLK_RATIO REG_BIT(6) 68 #define OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS REG_BIT(5) 69 #define OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS REG_BIT(1) 70 71 #define OAG_OASTATUS XE_REG(0xdafc) 72 #define OASTATUS_MMIO_TRG_Q_FULL REG_BIT(6) 73 #define OASTATUS_COUNTER_OVERFLOW REG_BIT(2) 74 #define OASTATUS_BUFFER_OVERFLOW REG_BIT(1) 75 #define OASTATUS_REPORT_LOST REG_BIT(0) 76 #define OAG_MMIOTRIGGER XE_REG(0xdb1c) 77 /* OAC unit */ 78 #define OAC_OACONTROL XE_REG(0x15114) 79 80 /* OAM unit */ 81 #define OAM_HEAD_POINTER_OFFSET (0x1a0) 82 #define OAM_TAIL_POINTER_OFFSET (0x1a4) 83 #define OAM_BUFFER_OFFSET (0x1a8) 84 #define OAM_CONTEXT_CONTROL_OFFSET (0x1bc) 85 #define OAM_CONTROL_OFFSET (0x194) 86 #define OAM_CONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1) 87 #define OAM_DEBUG_OFFSET (0x198) 88 #define OAM_STATUS_OFFSET (0x19c) 89 #define OAM_MMIO_TRG_OFFSET (0x1d0) 90 91 #define OAM_HEAD_POINTER(base) XE_REG((base) + OAM_HEAD_POINTER_OFFSET) 92 #define OAM_TAIL_POINTER(base) XE_REG((base) + OAM_TAIL_POINTER_OFFSET) 93 #define OAM_BUFFER(base) XE_REG((base) + OAM_BUFFER_OFFSET) 94 #define OAM_CONTEXT_CONTROL(base) XE_REG((base) + OAM_CONTEXT_CONTROL_OFFSET) 95 #define OAM_CONTROL(base) XE_REG((base) + OAM_CONTROL_OFFSET) 96 #define OAM_DEBUG(base) XE_REG((base) + OAM_DEBUG_OFFSET) 97 #define OAM_STATUS(base) XE_REG((base) + OAM_STATUS_OFFSET) 98 #define OAM_MMIO_TRG(base) XE_REG((base) + OAM_MMIO_TRG_OFFSET) 99 100 #endif 101