1a9f905aeSAshutosh Dixit /* SPDX-License-Identifier: MIT */ 2a9f905aeSAshutosh Dixit /* 3a9f905aeSAshutosh Dixit * Copyright © 2023 Intel Corporation 4a9f905aeSAshutosh Dixit */ 5a9f905aeSAshutosh Dixit 6a9f905aeSAshutosh Dixit #ifndef __XE_OA_REGS__ 7a9f905aeSAshutosh Dixit #define __XE_OA_REGS__ 8a9f905aeSAshutosh Dixit 9a9f905aeSAshutosh Dixit #define RPM_CONFIG1 XE_REG(0xd04) 10a9f905aeSAshutosh Dixit #define GT_NOA_ENABLE REG_BIT(9) 11a9f905aeSAshutosh Dixit 12a9f905aeSAshutosh Dixit #define EU_PERF_CNTL0 XE_REG(0xe458) 13a9f905aeSAshutosh Dixit #define EU_PERF_CNTL4 XE_REG(0xe45c) 14a9f905aeSAshutosh Dixit #define EU_PERF_CNTL1 XE_REG(0xe558) 15a9f905aeSAshutosh Dixit #define EU_PERF_CNTL5 XE_REG(0xe55c) 16a9f905aeSAshutosh Dixit #define EU_PERF_CNTL2 XE_REG(0xe658) 17a9f905aeSAshutosh Dixit #define EU_PERF_CNTL6 XE_REG(0xe65c) 18a9f905aeSAshutosh Dixit #define EU_PERF_CNTL3 XE_REG(0xe758) 19a9f905aeSAshutosh Dixit 20a9f905aeSAshutosh Dixit #define OA_TLB_INV_CR XE_REG(0xceec) 21a9f905aeSAshutosh Dixit 22a9f905aeSAshutosh Dixit /* OAR unit */ 23a9f905aeSAshutosh Dixit #define OAR_OACONTROL XE_REG(0x2960) 24a9f905aeSAshutosh Dixit #define OAR_OACONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1) 25a9f905aeSAshutosh Dixit #define OAR_OACONTROL_COUNTER_ENABLE REG_BIT(0) 26a9f905aeSAshutosh Dixit 27a9f905aeSAshutosh Dixit #define OACTXCONTROL(base) XE_REG((base) + 0x360) 28a9f905aeSAshutosh Dixit #define OAR_OASTATUS XE_REG(0x2968) 29a9f905aeSAshutosh Dixit #define OA_COUNTER_RESUME REG_BIT(0) 30a9f905aeSAshutosh Dixit 31a9f905aeSAshutosh Dixit /* OAG unit */ 32a9f905aeSAshutosh Dixit #define OAG_OAGLBCTXCTRL XE_REG(0x2b28) 33a9f905aeSAshutosh Dixit #define OAG_OAGLBCTXCTRL_TIMER_PERIOD_MASK REG_GENMASK(7, 2) 34a9f905aeSAshutosh Dixit #define OAG_OAGLBCTXCTRL_TIMER_ENABLE REG_BIT(1) 35a9f905aeSAshutosh Dixit #define OAG_OAGLBCTXCTRL_COUNTER_RESUME REG_BIT(0) 36a9f905aeSAshutosh Dixit 37a9f905aeSAshutosh Dixit #define OAG_OAHEADPTR XE_REG(0xdb00) 38a9f905aeSAshutosh Dixit #define OAG_OAHEADPTR_MASK REG_GENMASK(31, 6) 39a9f905aeSAshutosh Dixit #define OAG_OATAILPTR XE_REG(0xdb04) 40a9f905aeSAshutosh Dixit #define OAG_OATAILPTR_MASK REG_GENMASK(31, 6) 41a9f905aeSAshutosh Dixit 42a9f905aeSAshutosh Dixit #define OAG_OABUFFER XE_REG(0xdb08) 43a9f905aeSAshutosh Dixit #define OABUFFER_SIZE_MASK REG_GENMASK(5, 3) 44a9f905aeSAshutosh Dixit #define OABUFFER_SIZE_128K REG_FIELD_PREP(OABUFFER_SIZE_MASK, 0) 45a9f905aeSAshutosh Dixit #define OABUFFER_SIZE_256K REG_FIELD_PREP(OABUFFER_SIZE_MASK, 1) 46a9f905aeSAshutosh Dixit #define OABUFFER_SIZE_512K REG_FIELD_PREP(OABUFFER_SIZE_MASK, 2) 47a9f905aeSAshutosh Dixit #define OABUFFER_SIZE_1M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 3) 48a9f905aeSAshutosh Dixit #define OABUFFER_SIZE_2M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 4) 49a9f905aeSAshutosh Dixit #define OABUFFER_SIZE_4M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 5) 50a9f905aeSAshutosh Dixit #define OABUFFER_SIZE_8M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 6) 51a9f905aeSAshutosh Dixit #define OABUFFER_SIZE_16M REG_FIELD_PREP(OABUFFER_SIZE_MASK, 7) 52a9f905aeSAshutosh Dixit #define OAG_OABUFFER_MEMORY_SELECT REG_BIT(0) /* 0: PPGTT, 1: GGTT */ 53a9f905aeSAshutosh Dixit 54a9f905aeSAshutosh Dixit #define OAG_OACONTROL XE_REG(0xdaf4) 55*a262cc8dSAshutosh Dixit #define OAG_OACONTROL_OA_PES_DISAG_EN REG_GENMASK(27, 22) 56a9f905aeSAshutosh Dixit #define OAG_OACONTROL_OA_CCS_SELECT_MASK REG_GENMASK(18, 16) 57a9f905aeSAshutosh Dixit #define OAG_OACONTROL_OA_COUNTER_SEL_MASK REG_GENMASK(4, 2) 58a9f905aeSAshutosh Dixit #define OAG_OACONTROL_OA_COUNTER_ENABLE REG_BIT(0) 59a9f905aeSAshutosh Dixit /* Common to all OA units */ 60a9f905aeSAshutosh Dixit #define OA_OACONTROL_REPORT_BC_MASK REG_GENMASK(9, 9) 61a9f905aeSAshutosh Dixit #define OA_OACONTROL_COUNTER_SIZE_MASK REG_GENMASK(8, 8) 62a9f905aeSAshutosh Dixit 63a9f905aeSAshutosh Dixit #define OAG_OA_DEBUG XE_REG(0xdaf8, XE_REG_OPTION_MASKED) 64828a8eafSAshutosh Dixit #define OAG_OA_DEBUG_DISABLE_MMIO_TRG REG_BIT(14) 65828a8eafSAshutosh Dixit #define OAG_OA_DEBUG_START_TRIGGER_SCOPE_CONTROL REG_BIT(13) 66828a8eafSAshutosh Dixit #define OAG_OA_DEBUG_DISABLE_START_TRG_2_COUNT_QUAL REG_BIT(8) 67828a8eafSAshutosh Dixit #define OAG_OA_DEBUG_DISABLE_START_TRG_1_COUNT_QUAL REG_BIT(7) 68a9f905aeSAshutosh Dixit #define OAG_OA_DEBUG_INCLUDE_CLK_RATIO REG_BIT(6) 69a9f905aeSAshutosh Dixit #define OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS REG_BIT(5) 70a9f905aeSAshutosh Dixit #define OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS REG_BIT(1) 71a9f905aeSAshutosh Dixit 72a9f905aeSAshutosh Dixit #define OAG_OASTATUS XE_REG(0xdafc) 73a9f905aeSAshutosh Dixit #define OASTATUS_MMIO_TRG_Q_FULL REG_BIT(6) 74a9f905aeSAshutosh Dixit #define OASTATUS_COUNTER_OVERFLOW REG_BIT(2) 75a9f905aeSAshutosh Dixit #define OASTATUS_BUFFER_OVERFLOW REG_BIT(1) 76a9f905aeSAshutosh Dixit #define OASTATUS_REPORT_LOST REG_BIT(0) 77828a8eafSAshutosh Dixit #define OAG_MMIOTRIGGER XE_REG(0xdb1c) 7814e077f8SAshutosh Dixit /* OAC unit */ 7914e077f8SAshutosh Dixit #define OAC_OACONTROL XE_REG(0x15114) 8014e077f8SAshutosh Dixit 81a9f905aeSAshutosh Dixit /* OAM unit */ 82a9f905aeSAshutosh Dixit #define OAM_HEAD_POINTER_OFFSET (0x1a0) 83a9f905aeSAshutosh Dixit #define OAM_TAIL_POINTER_OFFSET (0x1a4) 84a9f905aeSAshutosh Dixit #define OAM_BUFFER_OFFSET (0x1a8) 85a9f905aeSAshutosh Dixit #define OAM_CONTEXT_CONTROL_OFFSET (0x1bc) 86a9f905aeSAshutosh Dixit #define OAM_CONTROL_OFFSET (0x194) 87a9f905aeSAshutosh Dixit #define OAM_CONTROL_COUNTER_SEL_MASK REG_GENMASK(3, 1) 88a9f905aeSAshutosh Dixit #define OAM_DEBUG_OFFSET (0x198) 89a9f905aeSAshutosh Dixit #define OAM_STATUS_OFFSET (0x19c) 90a9f905aeSAshutosh Dixit #define OAM_MMIO_TRG_OFFSET (0x1d0) 91a9f905aeSAshutosh Dixit 92a9f905aeSAshutosh Dixit #define OAM_HEAD_POINTER(base) XE_REG((base) + OAM_HEAD_POINTER_OFFSET) 93a9f905aeSAshutosh Dixit #define OAM_TAIL_POINTER(base) XE_REG((base) + OAM_TAIL_POINTER_OFFSET) 94a9f905aeSAshutosh Dixit #define OAM_BUFFER(base) XE_REG((base) + OAM_BUFFER_OFFSET) 95a9f905aeSAshutosh Dixit #define OAM_CONTEXT_CONTROL(base) XE_REG((base) + OAM_CONTEXT_CONTROL_OFFSET) 96a9f905aeSAshutosh Dixit #define OAM_CONTROL(base) XE_REG((base) + OAM_CONTROL_OFFSET) 97a9f905aeSAshutosh Dixit #define OAM_DEBUG(base) XE_REG((base) + OAM_DEBUG_OFFSET) 98a9f905aeSAshutosh Dixit #define OAM_STATUS(base) XE_REG((base) + OAM_STATUS_OFFSET) 99a9f905aeSAshutosh Dixit #define OAM_MMIO_TRG(base) XE_REG((base) + OAM_MMIO_TRG_OFFSET) 100a9f905aeSAshutosh Dixit 101a9f905aeSAshutosh Dixit #endif 102