1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2024 Intel Corporation 4 */ 5 #ifndef _XE_IRQ_REGS_H_ 6 #define _XE_IRQ_REGS_H_ 7 8 #include "regs/xe_reg_defs.h" 9 10 #define PCU_IRQ_OFFSET 0x444e0 11 #define GU_MISC_IRQ_OFFSET 0x444f0 12 #define GU_MISC_GSE REG_BIT(27) 13 14 #define DG1_MSTR_TILE_INTR XE_REG(0x190008) 15 #define DG1_MSTR_IRQ REG_BIT(31) 16 #define DG1_MSTR_TILE(t) REG_BIT(t) 17 18 #define GFX_MSTR_IRQ XE_REG(0x190010, XE_REG_OPTION_VF) 19 #define MASTER_IRQ REG_BIT(31) 20 #define GU_MISC_IRQ REG_BIT(29) 21 #define ERROR_IRQ(x) REG_BIT(26 + (x)) 22 #define DISPLAY_IRQ REG_BIT(16) 23 #define I2C_IRQ REG_BIT(12) 24 #define GT_DW_IRQ(x) REG_BIT(x) 25 26 /* 27 * Note: Interrupt registers 1900xx are VF accessible only until version 12.50. 28 * On newer platforms, VFs are using memory-based interrupts instead. 29 * However, for simplicity we keep this XE_REG_OPTION_VF tag intact. 30 */ 31 32 #define GT_INTR_DW(x) XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF) 33 #define INTR_GSC REG_BIT(31) 34 #define INTR_GUC REG_BIT(25) 35 #define INTR_MGUC REG_BIT(24) 36 #define INTR_BCS8 REG_BIT(23) 37 #define INTR_BCS(x) REG_BIT(15 - (x)) 38 #define INTR_CCS(x) REG_BIT(4 + (x)) 39 #define INTR_RCS0 REG_BIT(0) 40 #define INTR_VECS(x) REG_BIT(31 - (x)) 41 #define INTR_VCS(x) REG_BIT(x) 42 43 #define RENDER_COPY_INTR_ENABLE XE_REG(0x190030, XE_REG_OPTION_VF) 44 #define VCS_VECS_INTR_ENABLE XE_REG(0x190034, XE_REG_OPTION_VF) 45 #define GUC_SG_INTR_ENABLE XE_REG(0x190038, XE_REG_OPTION_VF) 46 #define ENGINE1_MASK REG_GENMASK(31, 16) 47 #define ENGINE0_MASK REG_GENMASK(15, 0) 48 #define GPM_WGBOXPERF_INTR_ENABLE XE_REG(0x19003c, XE_REG_OPTION_VF) 49 #define CRYPTO_RSVD_INTR_ENABLE XE_REG(0x190040) 50 #define GUNIT_GSC_INTR_ENABLE XE_REG(0x190044, XE_REG_OPTION_VF) 51 #define CCS_RSVD_INTR_ENABLE XE_REG(0x190048, XE_REG_OPTION_VF) 52 53 #define INTR_IDENTITY_REG(x) XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF) 54 #define INTR_DATA_VALID REG_BIT(31) 55 #define INTR_ENGINE_INSTANCE(x) REG_FIELD_GET(GENMASK(25, 20), x) 56 #define INTR_ENGINE_CLASS(x) REG_FIELD_GET(GENMASK(18, 16), x) 57 #define INTR_ENGINE_INTR(x) REG_FIELD_GET(GENMASK(15, 0), x) 58 #define OTHER_GUC_INSTANCE 0 59 #define OTHER_GSC_HECI2_INSTANCE 3 60 #define OTHER_KCR_INSTANCE 4 61 #define OTHER_GSC_INSTANCE 6 62 63 #define IIR_REG_SELECTOR(x) XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF) 64 #define RCS0_RSVD_INTR_MASK XE_REG(0x190090, XE_REG_OPTION_VF) 65 #define BCS_RSVD_INTR_MASK XE_REG(0x1900a0, XE_REG_OPTION_VF) 66 #define VCS0_VCS1_INTR_MASK XE_REG(0x1900a8, XE_REG_OPTION_VF) 67 #define VCS2_VCS3_INTR_MASK XE_REG(0x1900ac, XE_REG_OPTION_VF) 68 #define VECS0_VECS1_INTR_MASK XE_REG(0x1900d0, XE_REG_OPTION_VF) 69 #define HECI2_RSVD_INTR_MASK XE_REG(0x1900e4) 70 #define GUC_SG_INTR_MASK XE_REG(0x1900e8, XE_REG_OPTION_VF) 71 #define GPM_WGBOXPERF_INTR_MASK XE_REG(0x1900ec, XE_REG_OPTION_VF) 72 #define CRYPTO_RSVD_INTR_MASK XE_REG(0x1900f0) 73 #define GUNIT_GSC_INTR_MASK XE_REG(0x1900f4, XE_REG_OPTION_VF) 74 #define CCS0_CCS1_INTR_MASK XE_REG(0x190100) 75 #define CCS2_CCS3_INTR_MASK XE_REG(0x190104) 76 #define XEHPC_BCS1_BCS2_INTR_MASK XE_REG(0x190110) 77 #define XEHPC_BCS3_BCS4_INTR_MASK XE_REG(0x190114) 78 #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118) 79 #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c) 80 #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) 81 #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) 82 #define GSC_ER_COMPLETE REG_BIT(5) 83 #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4) 84 #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 85 #define GT_RENDER_USER_INTERRUPT REG_BIT(0) 86 87 /* irqs for OTHER_KCR_INSTANCE */ 88 #define KCR_PXP_STATE_TERMINATED_INTERRUPT REG_BIT(1) 89 #define KCR_APP_TERMINATED_PER_FW_REQ_INTERRUPT REG_BIT(2) 90 #define KCR_PXP_STATE_RESET_COMPLETE_INTERRUPT REG_BIT(3) 91 92 #endif 93