xref: /linux/drivers/gpu/drm/xe/regs/xe_guc_regs.h (revision a3a02a52bcfcbcc4a637d4b68bf1bc391c9fad02) 
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2022 Intel Corporation
4  */
5 
6 #ifndef _XE_GUC_REGS_H_
7 #define _XE_GUC_REGS_H_
8 
9 #include <linux/compiler.h>
10 #include <linux/types.h>
11 
12 #include "regs/xe_reg_defs.h"
13 
14 /* Definitions of GuC H/W registers, bits, etc */
15 
16 #define DIST_DBS_POPULATED			XE_REG(0xd08)
17 #define   DOORBELLS_PER_SQIDI_MASK		REG_GENMASK(23, 16)
18 #define   SQIDIS_DOORBELL_EXIST_MASK		REG_GENMASK(15, 0)
19 
20 #define DRBREGL(x)				XE_REG(0x1000 + (x) * 8)
21 #define   DRB_VALID				REG_BIT(0)
22 #define DRBREGU(x)				XE_REG(0x1000 + (x) * 8 + 4)
23 
24 #define GTCR					XE_REG(0x4274)
25 #define   GTCR_INVALIDATE			REG_BIT(0)
26 
27 #define GUC_ARAT_C6DIS				XE_REG(0xa178)
28 
29 #define GUC_STATUS				XE_REG(0xc000)
30 #define   GS_AUTH_STATUS_MASK			REG_GENMASK(31, 30)
31 #define   GS_AUTH_STATUS_BAD			REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x1)
32 #define   GS_AUTH_STATUS_GOOD			REG_FIELD_PREP(GS_AUTH_STATUS_MASK, 0x2)
33 #define   GS_MIA_MASK				REG_GENMASK(18, 16)
34 #define   GS_MIA_CORE_STATE			REG_FIELD_PREP(GS_MIA_MASK, 0x1)
35 #define   GS_MIA_HALT_REQUESTED			REG_FIELD_PREP(GS_MIA_MASK, 0x2)
36 #define   GS_MIA_ISR_ENTRY			REG_FIELD_PREP(GS_MIA_MASK, 0x4)
37 #define   GS_UKERNEL_MASK			REG_GENMASK(15, 8)
38 #define   GS_BOOTROM_MASK			REG_GENMASK(7, 1)
39 #define   GS_BOOTROM_RSA_FAILED			REG_FIELD_PREP(GS_BOOTROM_MASK, 0x50)
40 #define   GS_BOOTROM_JUMP_PASSED		REG_FIELD_PREP(GS_BOOTROM_MASK, 0x76)
41 #define   GS_MIA_IN_RESET			REG_BIT(0)
42 
43 #define GUC_HEADER_INFO				XE_REG(0xc014)
44 
45 #define GUC_WOPCM_SIZE				XE_REG(0xc050)
46 #define   GUC_WOPCM_SIZE_MASK			REG_GENMASK(31, 12)
47 #define   GUC_WOPCM_SIZE_LOCKED			REG_BIT(0)
48 
49 #define GUC_SHIM_CONTROL			XE_REG(0xc064)
50 #define   GUC_MOCS_INDEX_MASK			REG_GENMASK(27, 24)
51 #define   GUC_SHIM_WC_ENABLE			REG_BIT(21)
52 #define   GUC_ENABLE_MIA_CLOCK_GATING		REG_BIT(15)
53 #define   GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	REG_BIT(10)
54 #define   GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	REG_BIT(9)
55 #define   GUC_MSGCH_ENABLE			REG_BIT(4)
56 #define   GUC_ENABLE_MIA_CACHING		REG_BIT(2)
57 #define   GUC_ENABLE_READ_CACHE_LOGIC		REG_BIT(1)
58 #define   GUC_DISABLE_SRAM_INIT_TO_ZEROES	REG_BIT(0)
59 
60 #define SOFT_SCRATCH(n)				XE_REG(0xc180 + (n) * 4)
61 #define SOFT_SCRATCH_COUNT			16
62 
63 #define HUC_KERNEL_LOAD_INFO			XE_REG(0xc1dc)
64 #define   HUC_LOAD_SUCCESSFUL			REG_BIT(0)
65 
66 #define UOS_RSA_SCRATCH(i)			XE_REG(0xc200 + (i) * 4)
67 #define UOS_RSA_SCRATCH_COUNT			64
68 
69 #define DMA_ADDR_0_LOW				XE_REG(0xc300)
70 #define DMA_ADDR_0_HIGH				XE_REG(0xc304)
71 #define DMA_ADDR_1_LOW				XE_REG(0xc308)
72 #define DMA_ADDR_1_HIGH				XE_REG(0xc30c)
73 #define   DMA_ADDR_SPACE_MASK			REG_GENMASK(20, 16)
74 #define   DMA_ADDRESS_SPACE_WOPCM		REG_FIELD_PREP(DMA_ADDR_SPACE_MASK, 7)
75 #define   DMA_ADDRESS_SPACE_GGTT		REG_FIELD_PREP(DMA_ADDR_SPACE_MASK, 8)
76 #define DMA_COPY_SIZE				XE_REG(0xc310)
77 #define DMA_CTRL				XE_REG(0xc314)
78 #define   HUC_UKERNEL				REG_BIT(9)
79 #define   UOS_MOVE				REG_BIT(4)
80 #define   START_DMA				REG_BIT(0)
81 #define DMA_GUC_WOPCM_OFFSET			XE_REG(0xc340)
82 #define   GUC_WOPCM_OFFSET_SHIFT		14
83 #define   GUC_WOPCM_OFFSET_MASK			REG_GENMASK(31, GUC_WOPCM_OFFSET_SHIFT)
84 #define   HUC_LOADING_AGENT_GUC			REG_BIT(1)
85 #define   GUC_WOPCM_OFFSET_VALID		REG_BIT(0)
86 #define GUC_MAX_IDLE_COUNT			XE_REG(0xc3e4)
87 
88 #define GUC_SEND_INTERRUPT			XE_REG(0xc4c8)
89 #define   GUC_SEND_TRIGGER			REG_BIT(0)
90 
91 #define GUC_BCS_RCS_IER				XE_REG(0xc550)
92 #define GUC_VCS2_VCS1_IER			XE_REG(0xc554)
93 #define GUC_WD_VECS_IER				XE_REG(0xc558)
94 #define GUC_PM_P24C_IER				XE_REG(0xc55c)
95 
96 #define GUC_TLB_INV_CR				XE_REG(0xcee8)
97 #define   GUC_TLB_INV_CR_INVALIDATE		REG_BIT(0)
98 
99 #define HUC_STATUS2				XE_REG(0xd3b0)
100 #define   HUC_FW_VERIFIED			REG_BIT(7)
101 
102 #define GT_PM_CONFIG				XE_REG(0x13816c)
103 #define   GT_DOORBELL_ENABLE			REG_BIT(0)
104 
105 #define GUC_HOST_INTERRUPT			XE_REG(0x1901f0, XE_REG_OPTION_VF)
106 
107 #define VF_SW_FLAG(n)				XE_REG(0x190240 + (n) * 4, XE_REG_OPTION_VF)
108 #define VF_SW_FLAG_COUNT			4
109 
110 #define MED_GUC_HOST_INTERRUPT			XE_REG(0x190304, XE_REG_OPTION_VF)
111 
112 #define MED_VF_SW_FLAG(n)			XE_REG(0x190310 + (n) * 4, XE_REG_OPTION_VF)
113 #define MED_VF_SW_FLAG_COUNT			4
114 
115 #define GUC_TLB_INV_CR				XE_REG(0xcee8)
116 #define   GUC_TLB_INV_CR_INVALIDATE		REG_BIT(0)
117 #define PVC_GUC_TLB_INV_DESC0			XE_REG(0xcf7c)
118 #define   PVC_GUC_TLB_INV_DESC0_VALID		REG_BIT(0)
119 #define PVC_GUC_TLB_INV_DESC1			XE_REG(0xcf80)
120 #define   PVC_GUC_TLB_INV_DESC1_INVALIDATE	REG_BIT(6)
121 
122 /* GuC Interrupt Vector */
123 #define GUC_INTR_GUC2HOST			REG_BIT(15)
124 #define GUC_INTR_EXEC_ERROR			REG_BIT(14)
125 #define GUC_INTR_DISPLAY_EVENT			REG_BIT(13)
126 #define GUC_INTR_SEM_SIG			REG_BIT(12)
127 #define GUC_INTR_IOMMU2GUC			REG_BIT(11)
128 #define GUC_INTR_DOORBELL_RANG			REG_BIT(10)
129 #define GUC_INTR_DMA_DONE			REG_BIT(9)
130 #define GUC_INTR_FATAL_ERROR			REG_BIT(8)
131 #define GUC_INTR_NOTIF_ERROR			REG_BIT(7)
132 #define GUC_INTR_SW_INT_6			REG_BIT(6)
133 #define GUC_INTR_SW_INT_5			REG_BIT(5)
134 #define GUC_INTR_SW_INT_4			REG_BIT(4)
135 #define GUC_INTR_SW_INT_3			REG_BIT(3)
136 #define GUC_INTR_SW_INT_2			REG_BIT(2)
137 #define GUC_INTR_SW_INT_1			REG_BIT(1)
138 #define GUC_INTR_SW_INT_0			REG_BIT(0)
139 
140 #define GUC_NUM_DOORBELLS			256
141 
142 /* format of the HW-monitored doorbell cacheline */
143 struct guc_doorbell_info {
144 	u32 db_status;
145 #define GUC_DOORBELL_DISABLED			0
146 #define GUC_DOORBELL_ENABLED			1
147 
148 	u32 cookie;
149 	u32 reserved[14];
150 } __packed;
151 
152 #endif
153