xref: /linux/drivers/gpu/drm/xe/regs/xe_gt_regs.h (revision 62597edf6340191511bdf9a7f64fa315ddc58805)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #ifndef _XE_GT_REGS_H_
7 #define _XE_GT_REGS_H_
8 
9 #include "regs/xe_reg_defs.h"
10 
11 /*
12  * The GSI register range [0x0 - 0x40000) is replicated at a higher offset
13  * for the media GT.  xe_mmio and xe_gt_mcr functions will automatically
14  * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT.
15  */
16 #define MEDIA_GT_GSI_OFFSET				0x380000
17 #define MEDIA_GT_GSI_LENGTH				0x40000
18 
19 /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */
20 #define MTL_MIRROR_TARGET_WP1				XE_REG(0xc60)
21 #define   MTL_CAGF_MASK					REG_GENMASK(8, 0)
22 #define   MTL_CC_MASK					REG_GENMASK(12, 9)
23 
24 /* RPM unit config (Gen8+) */
25 #define RPM_CONFIG0					XE_REG(0xd00)
26 #define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK		REG_GENMASK(5, 3)
27 #define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ		0
28 #define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
29 #define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
30 #define   RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ		3
31 #define   RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
32 
33 #define FORCEWAKE_ACK_MEDIA_VDBOX(n)		XE_REG(0xd50 + (n) * 4)
34 #define FORCEWAKE_ACK_MEDIA_VEBOX(n)		XE_REG(0xd70 + (n) * 4)
35 #define FORCEWAKE_ACK_RENDER			XE_REG(0xd84)
36 
37 #define GMD_ID					XE_REG(0xd8c)
38 #define   GMD_ID_ARCH_MASK			REG_GENMASK(31, 22)
39 #define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)
40 #define   GMD_ID_REVID				REG_GENMASK(5, 0)
41 
42 #define FORCEWAKE_ACK_GSC			XE_REG(0xdf8)
43 #define FORCEWAKE_ACK_GT_MTL			XE_REG(0xdfc)
44 
45 #define MCFG_MCR_SELECTOR			XE_REG(0xfd0)
46 #define MTL_MCR_SELECTOR			XE_REG(0xfd4)
47 #define SF_MCR_SELECTOR				XE_REG(0xfd8)
48 #define MCR_SELECTOR				XE_REG(0xfdc)
49 #define GAM_MCR_SELECTOR			XE_REG(0xfe0)
50 #define   MCR_MULTICAST				REG_BIT(31)
51 #define   MCR_SLICE_MASK			REG_GENMASK(30, 27)
52 #define   MCR_SLICE(slice)			REG_FIELD_PREP(MCR_SLICE_MASK, slice)
53 #define   MCR_SUBSLICE_MASK			REG_GENMASK(26, 24)
54 #define   MCR_SUBSLICE(subslice)		REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice)
55 #define   MTL_MCR_GROUPID			REG_GENMASK(11, 8)
56 #define   MTL_MCR_INSTANCEID			REG_GENMASK(3, 0)
57 
58 #define PS_INVOCATION_COUNT			XE_REG(0x2348)
59 
60 #define XELP_GLOBAL_MOCS(i)			XE_REG(0x4000 + (i) * 4)
61 #define XEHP_GLOBAL_MOCS(i)			XE_REG_MCR(0x4000 + (i) * 4)
62 #define   LE_SSE_MASK				REG_GENMASK(18, 17)
63 #define   LE_SSE(value)				REG_FIELD_PREP(LE_SSE_MASK, value)
64 #define   LE_COS_MASK				REG_GENMASK(16, 15)
65 #define   LE_COS(value)				REG_FIELD_PREP(LE_COS_MASK)
66 #define   LE_SCF_MASK				REG_BIT(14)
67 #define   LE_SCF(value)				REG_FIELD_PREP(LE_SCF_MASK, value)
68 #define   LE_PFM_MASK				REG_GENMASK(13, 11)
69 #define   LE_PFM(value)				REG_FIELD_PREP(LE_PFM_MASK, value)
70 #define   LE_SCC_MASK				REG_GENMASK(10, 8)
71 #define   LE_SCC(value)				REG_FIELD_PREP(LE_SCC_MASK, value)
72 #define   LE_RSC_MASK				REG_BIT(7)
73 #define   LE_RSC(value)				REG_FIELD_PREP(LE_RSC_MASK, value)
74 #define   LE_AOM_MASK				REG_BIT(6)
75 #define   LE_AOM(value)				REG_FIELD_PREP(LE_AOM_MASK, value)
76 #define   LE_LRUM_MASK				REG_GENMASK(5, 4)
77 #define   LE_LRUM(value)			REG_FIELD_PREP(LE_LRUM_MASK, value)
78 #define   LE_TGT_CACHE_MASK			REG_GENMASK(3, 2)
79 #define   LE_TGT_CACHE(value)			REG_FIELD_PREP(LE_TGT_CACHE_MASK, value)
80 #define   LE_CACHEABILITY_MASK			REG_GENMASK(1, 0)
81 #define   LE_CACHEABILITY(value)		REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)
82 
83 #define XE2_GAMREQSTRM_CTRL			XE_REG(0x4194)
84 #define   CG_DIS_CNTLBUS			REG_BIT(6)
85 
86 #define CCS_AUX_INV				XE_REG(0x4208)
87 
88 #define VD0_AUX_INV				XE_REG(0x4218)
89 #define VE0_AUX_INV				XE_REG(0x4238)
90 
91 #define VE1_AUX_INV				XE_REG(0x42b8)
92 #define   AUX_INV				REG_BIT(0)
93 
94 #define XEHP_TILE_ADDR_RANGE(_idx)		XE_REG_MCR(0x4900 + (_idx) * 4)
95 #define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)
96 #define XEHP_FLAT_CCS_PTR			REG_GENMASK(31, 8)
97 
98 #define WM_CHICKEN3				XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
99 #define   HIZ_PLANE_COMPRESSION_DIS		REG_BIT(10)
100 
101 #define CHICKEN_RASTER_1			XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED)
102 #define   DIS_SF_ROUND_NEAREST_EVEN		REG_BIT(8)
103 
104 #define CHICKEN_RASTER_2			XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
105 #define   TBIMR_FAST_CLIP			REG_BIT(5)
106 
107 #define FF_MODE					XE_REG_MCR(0x6210)
108 #define   DIS_TE_AUTOSTRIP			REG_BIT(31)
109 #define   DIS_MESH_PARTIAL_AUTOSTRIP		REG_BIT(16)
110 #define   DIS_MESH_AUTOSTRIP			REG_BIT(15)
111 
112 #define VFLSKPD					XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED)
113 #define   DIS_PARTIAL_AUTOSTRIP			REG_BIT(9)
114 #define   DIS_AUTOSTRIP				REG_BIT(6)
115 #define   DIS_OVER_FETCH_CACHE			REG_BIT(1)
116 #define   DIS_MULT_MISS_RD_SQUASH		REG_BIT(0)
117 
118 #define FF_MODE2				XE_REG(0x6604)
119 #define XEHP_FF_MODE2				XE_REG_MCR(0x6604)
120 #define   FF_MODE2_GS_TIMER_MASK		REG_GENMASK(31, 24)
121 #define   FF_MODE2_GS_TIMER_224			REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
122 #define   FF_MODE2_TDS_TIMER_MASK		REG_GENMASK(23, 16)
123 #define   FF_MODE2_TDS_TIMER_128		REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
124 
125 #define XEHPG_INSTDONE_GEOM_SVGUNIT		XE_REG_MCR(0x666c)
126 
127 #define CACHE_MODE_1				XE_REG(0x7004, XE_REG_OPTION_MASKED)
128 #define   MSAA_OPTIMIZATION_REDUC_DISABLE	REG_BIT(11)
129 
130 #define COMMON_SLICE_CHICKEN1			XE_REG(0x7010, XE_REG_OPTION_MASKED)
131 #define   DISABLE_BOTTOM_CLIP_RECTANGLE_TEST	REG_BIT(14)
132 
133 #define HIZ_CHICKEN					XE_REG(0x7018, XE_REG_OPTION_MASKED)
134 #define   DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE	REG_BIT(14)
135 #define   HZ_DEPTH_TEST_LE_GE_OPT_DISABLE		REG_BIT(13)
136 
137 #define XEHP_PSS_MODE2				XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED)
138 #define   SCOREBOARD_STALL_FLUSH_CONTROL	REG_BIT(5)
139 
140 #define XEHP_PSS_CHICKEN			XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED)
141 #define   FLSH_IGNORES_PSD			REG_BIT(10)
142 #define   FD_END_COLLECT			REG_BIT(5)
143 
144 #define SC_INSTDONE				XE_REG(0x7100)
145 #define SC_INSTDONE_EXTRA			XE_REG(0x7104)
146 #define SC_INSTDONE_EXTRA2			XE_REG(0x7108)
147 
148 #define XEHPG_SC_INSTDONE			XE_REG_MCR(0x7100)
149 #define XEHPG_SC_INSTDONE_EXTRA			XE_REG_MCR(0x7104)
150 #define XEHPG_SC_INSTDONE_EXTRA2		XE_REG_MCR(0x7108)
151 
152 #define COMMON_SLICE_CHICKEN4			XE_REG(0x7300, XE_REG_OPTION_MASKED)
153 #define   DISABLE_TDC_LOAD_BALANCING_CALC	REG_BIT(6)
154 
155 #define COMMON_SLICE_CHICKEN3				XE_REG(0x7304, XE_REG_OPTION_MASKED)
156 #define XEHP_COMMON_SLICE_CHICKEN3			XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED)
157 #define   DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN	REG_BIT(12)
158 #define   XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE		REG_BIT(12)
159 #define   BLEND_EMB_FIX_DISABLE_IN_RCC			REG_BIT(11)
160 #define   DISABLE_CPS_AWARE_COLOR_PIPE			REG_BIT(9)
161 
162 #define XEHP_SLICE_COMMON_ECO_CHICKEN1		XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)
163 #define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE	REG_BIT(14)
164 
165 #define VF_PREEMPTION				XE_REG(0x83a4, XE_REG_OPTION_MASKED)
166 #define   PREEMPTION_VERTEX_COUNT		REG_GENMASK(15, 0)
167 
168 #define VF_SCRATCHPAD				XE_REG(0x83a8, XE_REG_OPTION_MASKED)
169 #define   XE2_VFG_TED_CREDIT_INTERFACE_DISABLE	REG_BIT(13)
170 
171 #define VFG_PREEMPTION_CHICKEN			XE_REG(0x83b4, XE_REG_OPTION_MASKED)
172 #define   POLYGON_TRIFAN_LINELOOP_DISABLE	REG_BIT(4)
173 
174 #define SQCNT1					XE_REG_MCR(0x8718)
175 #define XELPMP_SQCNT1				XE_REG(0x8718)
176 #define   SQCNT1_PMON_ENABLE			REG_BIT(30)
177 #define   SQCNT1_OABPC				REG_BIT(29)
178 #define   ENFORCE_RAR				REG_BIT(23)
179 
180 #define XEHP_SQCM				XE_REG_MCR(0x8724)
181 #define   EN_32B_ACCESS				REG_BIT(30)
182 
183 #define XE2_FLAT_CCS_BASE_RANGE_LOWER		XE_REG_MCR(0x8800)
184 #define   XE2_FLAT_CCS_ENABLE			REG_BIT(0)
185 #define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK	REG_GENMASK(31, 6)
186 
187 #define XE2_FLAT_CCS_BASE_RANGE_UPPER		XE_REG_MCR(0x8804)
188 #define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK	REG_GENMASK(7, 0)
189 
190 #define GSCPSMI_BASE				XE_REG(0x880c)
191 
192 #define CCCHKNREG1				XE_REG_MCR(0x8828)
193 #define   ENCOMPPERFFIX				REG_BIT(18)
194 
195 /* Fuse readout registers for GT */
196 #define XEHP_FUSE4				XE_REG(0x9114)
197 #define   CFEG_WMTP_DISABLE			REG_BIT(20)
198 #define   CCS_EN_MASK				REG_GENMASK(19, 16)
199 #define   GT_L3_EXC_MASK			REG_GENMASK(6, 4)
200 
201 #define	MIRROR_FUSE3				XE_REG(0x9118)
202 #define   XE2_NODE_ENABLE_MASK			REG_GENMASK(31, 16)
203 #define   L3BANK_PAIR_COUNT			4
204 #define   XEHPC_GT_L3_MODE_MASK			REG_GENMASK(7, 4)
205 #define   XE2_GT_L3_MODE_MASK			REG_GENMASK(7, 4)
206 #define   L3BANK_MASK				REG_GENMASK(3, 0)
207 #define   XELP_GT_L3_MODE_MASK			REG_GENMASK(7, 0)
208 /* on Xe_HP the same fuses indicates mslices instead of L3 banks */
209 #define   MAX_MSLICES				4
210 #define   MEML3_EN_MASK				REG_GENMASK(3, 0)
211 
212 #define MIRROR_FUSE1				XE_REG(0x911c)
213 
214 #define XELP_EU_ENABLE				XE_REG(0x9134)	/* "_DISABLE" on Xe_LP */
215 #define   XELP_EU_MASK				REG_GENMASK(7, 0)
216 #define XELP_GT_SLICE_ENABLE			XE_REG(0x9138)
217 #define XELP_GT_GEOMETRY_DSS_ENABLE		XE_REG(0x913c)
218 
219 #define GT_VEBOX_VDBOX_DISABLE			XE_REG(0x9140)
220 #define   GT_VEBOX_DISABLE_MASK			REG_GENMASK(19, 16)
221 #define   GT_VDBOX_DISABLE_MASK			REG_GENMASK(7, 0)
222 
223 #define XEHP_GT_COMPUTE_DSS_ENABLE		XE_REG(0x9144)
224 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT		XE_REG(0x9148)
225 #define XE2_GT_COMPUTE_DSS_2			XE_REG(0x914c)
226 #define XE2_GT_GEOMETRY_DSS_1			XE_REG(0x9150)
227 #define XE2_GT_GEOMETRY_DSS_2			XE_REG(0x9154)
228 
229 #define GDRST					XE_REG(0x941c)
230 #define   GRDOM_GUC				REG_BIT(3)
231 #define   GRDOM_FULL				REG_BIT(0)
232 
233 #define MISCCPCTL				XE_REG(0x9424)
234 #define   DOP_CLOCK_GATE_RENDER_ENABLE		REG_BIT(1)
235 
236 #define UNSLCGCTL9430				XE_REG(0x9430)
237 #define   MSQDUNIT_CLKGATE_DIS			REG_BIT(3)
238 
239 #define UNSLICE_UNIT_LEVEL_CLKGATE		XE_REG(0x9434)
240 #define   VFUNIT_CLKGATE_DIS			REG_BIT(20)
241 #define   TSGUNIT_CLKGATE_DIS			REG_BIT(17) /* XEHPSDV */
242 #define   CG3DDISCFEG_CLKGATE_DIS		REG_BIT(17) /* DG2 */
243 #define   GAMEDIA_CLKGATE_DIS			REG_BIT(11)
244 #define   HSUNIT_CLKGATE_DIS			REG_BIT(8)
245 #define   VSUNIT_CLKGATE_DIS			REG_BIT(3)
246 
247 #define UNSLCGCTL9440				XE_REG(0x9440)
248 #define   GAMTLBOACS_CLKGATE_DIS		REG_BIT(28)
249 #define   GAMTLBVDBOX5_CLKGATE_DIS		REG_BIT(27)
250 #define   GAMTLBVDBOX6_CLKGATE_DIS		REG_BIT(26)
251 #define   GAMTLBVDBOX3_CLKGATE_DIS		REG_BIT(24)
252 #define   GAMTLBVDBOX4_CLKGATE_DIS		REG_BIT(23)
253 #define   GAMTLBVDBOX7_CLKGATE_DIS		REG_BIT(22)
254 #define   GAMTLBVDBOX2_CLKGATE_DIS		REG_BIT(21)
255 #define   GAMTLBVDBOX0_CLKGATE_DIS		REG_BIT(17)
256 #define   GAMTLBKCR_CLKGATE_DIS			REG_BIT(16)
257 #define   GAMTLBGUC_CLKGATE_DIS			REG_BIT(15)
258 #define   GAMTLBBLT_CLKGATE_DIS			REG_BIT(14)
259 #define   GAMTLBVDBOX1_CLKGATE_DIS		REG_BIT(6)
260 
261 #define UNSLCGCTL9444				XE_REG(0x9444)
262 #define   GAMTLBGFXA0_CLKGATE_DIS		REG_BIT(30)
263 #define   GAMTLBGFXA1_CLKGATE_DIS		REG_BIT(29)
264 #define   GAMTLBCOMPA0_CLKGATE_DIS		REG_BIT(28)
265 #define   GAMTLBCOMPA1_CLKGATE_DIS		REG_BIT(27)
266 #define   GAMTLBCOMPB0_CLKGATE_DIS		REG_BIT(26)
267 #define   GAMTLBCOMPB1_CLKGATE_DIS		REG_BIT(25)
268 #define   GAMTLBCOMPC0_CLKGATE_DIS		REG_BIT(24)
269 #define   GAMTLBCOMPC1_CLKGATE_DIS		REG_BIT(23)
270 #define   GAMTLBCOMPD0_CLKGATE_DIS		REG_BIT(22)
271 #define   GAMTLBCOMPD1_CLKGATE_DIS		REG_BIT(21)
272 #define   GAMTLBMERT_CLKGATE_DIS		REG_BIT(20)
273 #define   GAMTLBVEBOX3_CLKGATE_DIS		REG_BIT(19)
274 #define   GAMTLBVEBOX2_CLKGATE_DIS		REG_BIT(18)
275 #define   GAMTLBVEBOX1_CLKGATE_DIS		REG_BIT(17)
276 #define   GAMTLBVEBOX0_CLKGATE_DIS		REG_BIT(16)
277 #define   LTCDD_CLKGATE_DIS			REG_BIT(10)
278 
279 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x94d4)
280 #define   L3_CR2X_CLKGATE_DIS			REG_BIT(17)
281 #define   L3_CLKGATE_DIS			REG_BIT(16)
282 #define   NODEDSS_CLKGATE_DIS			REG_BIT(12)
283 #define   MSCUNIT_CLKGATE_DIS			REG_BIT(10)
284 #define   RCCUNIT_CLKGATE_DIS			REG_BIT(7)
285 #define   SARBUNIT_CLKGATE_DIS			REG_BIT(5)
286 #define   SBEUNIT_CLKGATE_DIS			REG_BIT(4)
287 
288 #define UNSLICE_UNIT_LEVEL_CLKGATE2		XE_REG(0x94e4)
289 #define   VSUNIT_CLKGATE2_DIS			REG_BIT(19)
290 
291 #define SUBSLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x9524)
292 #define   DSS_ROUTER_CLKGATE_DIS		REG_BIT(28)
293 #define   GWUNIT_CLKGATE_DIS			REG_BIT(16)
294 
295 #define SUBSLICE_UNIT_LEVEL_CLKGATE2		XE_REG_MCR(0x9528)
296 #define   CPSSUNIT_CLKGATE_DIS			REG_BIT(9)
297 
298 #define SSMCGCTL9530				XE_REG_MCR(0x9530)
299 #define   RTFUNIT_CLKGATE_DIS			REG_BIT(18)
300 
301 #define DFR_RATIO_EN_AND_CHICKEN		XE_REG_MCR(0x9550)
302 #define   DFR_DISABLE				REG_BIT(9)
303 
304 #define RPNSWREQ				XE_REG(0xa008)
305 #define   REQ_RATIO_MASK			REG_GENMASK(31, 23)
306 
307 #define RP_CONTROL				XE_REG(0xa024)
308 #define   RPSWCTL_MASK				REG_GENMASK(10, 9)
309 #define   RPSWCTL_ENABLE			REG_FIELD_PREP(RPSWCTL_MASK, 2)
310 #define   RPSWCTL_DISABLE			REG_FIELD_PREP(RPSWCTL_MASK, 0)
311 #define RC_CONTROL				XE_REG(0xa090)
312 #define   RC_CTL_HW_ENABLE			REG_BIT(31)
313 #define   RC_CTL_TO_MODE			REG_BIT(28)
314 #define   RC_CTL_RC6_ENABLE			REG_BIT(18)
315 #define RC_STATE				XE_REG(0xa094)
316 #define RC_IDLE_HYSTERSIS			XE_REG(0xa0ac)
317 #define MEDIA_POWERGATE_IDLE_HYSTERESIS		XE_REG(0xa0c4)
318 #define RENDER_POWERGATE_IDLE_HYSTERESIS	XE_REG(0xa0c8)
319 
320 #define PMINTRMSK				XE_REG(0xa168)
321 #define   PMINTR_DISABLE_REDIRECT_TO_GUC	REG_BIT(31)
322 #define   ARAT_EXPIRED_INTRMSK			REG_BIT(9)
323 
324 #define FORCEWAKE_GT				XE_REG(0xa188)
325 
326 #define POWERGATE_ENABLE			XE_REG(0xa210)
327 #define   RENDER_POWERGATE_ENABLE		REG_BIT(0)
328 #define   MEDIA_POWERGATE_ENABLE		REG_BIT(1)
329 #define   VDN_HCP_POWERGATE_ENABLE(n)		REG_BIT(3 + 2 * (n))
330 #define   VDN_MFXVDENC_POWERGATE_ENABLE(n)	REG_BIT(4 + 2 * (n))
331 
332 #define CTC_MODE				XE_REG(0xa26c)
333 #define   CTC_SHIFT_PARAMETER_MASK		REG_GENMASK(2, 1)
334 #define   CTC_SOURCE_DIVIDE_LOGIC		REG_BIT(0)
335 
336 #define FORCEWAKE_RENDER			XE_REG(0xa278)
337 #define FORCEWAKE_MEDIA_VDBOX(n)		XE_REG(0xa540 + (n) * 4)
338 #define FORCEWAKE_MEDIA_VEBOX(n)		XE_REG(0xa560 + (n) * 4)
339 #define FORCEWAKE_GSC				XE_REG(0xa618)
340 
341 #define XEHPC_LNCFMISCCFGREG0			XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)
342 #define   XEHPC_OVRLSCCC			REG_BIT(0)
343 
344 /* L3 Cache Control */
345 #define LNCFCMOCS_REG_COUNT			32
346 #define XELP_LNCFCMOCS(i)			XE_REG(0xb020 + (i) * 4)
347 #define XEHP_LNCFCMOCS(i)			XE_REG_MCR(0xb020 + (i) * 4)
348 #define   L3_UPPER_LKUP_MASK			REG_BIT(23)
349 #define   L3_UPPER_GLBGO_MASK			REG_BIT(22)
350 #define   L3_UPPER_IDX_CACHEABILITY_MASK	REG_GENMASK(21, 20)
351 #define   L3_UPPER_IDX_SCC_MASK			REG_GENMASK(19, 17)
352 #define   L3_UPPER_IDX_ESC_MASK			REG_BIT(16)
353 #define   L3_LKUP_MASK				REG_BIT(7)
354 #define   L3_LKUP(value)			REG_FIELD_PREP(L3_LKUP_MASK, value)
355 #define   L3_GLBGO_MASK				REG_BIT(6)
356 #define   L3_GLBGO(value)			REG_FIELD_PREP(L3_GLBGO_MASK, value)
357 #define   L3_CACHEABILITY_MASK			REG_GENMASK(5, 4)
358 #define   L3_CACHEABILITY(value)		REG_FIELD_PREP(L3_CACHEABILITY_MASK, value)
359 #define   L3_SCC_MASK				REG_GENMASK(3, 1)
360 #define   L3_SCC(value)				REG_FIELD_PREP(L3_SCC_MASK, value)
361 #define   L3_ESC_MASK				REG_BIT(0)
362 #define   L3_ESC(value)				REG_FIELD_PREP(L3_ESC_MASK, value)
363 
364 #define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
365 #define   XEHP_LNESPARE				REG_BIT(19)
366 
367 #define L3SQCREG3				XE_REG_MCR(0xb108)
368 #define   COMPPWOVERFETCHEN			REG_BIT(28)
369 
370 #define XEHP_L3SQCREG5				XE_REG_MCR(0xb158)
371 #define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)
372 
373 #define XEHP_L3SCQREG7				XE_REG_MCR(0xb188)
374 #define   BLEND_FILL_CACHING_OPT_DIS		REG_BIT(3)
375 
376 #define XEHPC_L3CLOS_MASK(i)			XE_REG_MCR(0xb194 + (i) * 8)
377 
378 #define XE2_GLOBAL_INVAL			XE_REG(0xb404)
379 
380 #define SCRATCH1LPFC				XE_REG(0xb474)
381 #define   EN_L3_RW_CCS_CACHE_FLUSH		REG_BIT(0)
382 
383 #define XE2LPM_L3SQCREG5			XE_REG_MCR(0xb658)
384 
385 #define XE2_TDF_CTRL				XE_REG(0xb418)
386 #define   TRANSIENT_FLUSH_REQUEST		REG_BIT(0)
387 
388 #define XEHP_MERT_MOD_CTRL			XE_REG_MCR(0xcf28)
389 #define RENDER_MOD_CTRL				XE_REG_MCR(0xcf2c)
390 #define COMP_MOD_CTRL				XE_REG_MCR(0xcf30)
391 #define XEHP_VDBX_MOD_CTRL			XE_REG_MCR(0xcf34)
392 #define XELPMP_VDBX_MOD_CTRL			XE_REG(0xcf34)
393 #define XEHP_VEBX_MOD_CTRL			XE_REG_MCR(0xcf38)
394 #define XELPMP_VEBX_MOD_CTRL			XE_REG(0xcf38)
395 #define   FORCE_MISS_FTLB			REG_BIT(3)
396 
397 #define XEHP_GAMSTLB_CTRL			XE_REG_MCR(0xcf4c)
398 #define   CONTROL_BLOCK_CLKGATE_DIS		REG_BIT(12)
399 #define   EGRESS_BLOCK_CLKGATE_DIS		REG_BIT(11)
400 #define   TAG_BLOCK_CLKGATE_DIS			REG_BIT(7)
401 
402 #define XEHP_GAMCNTRL_CTRL			XE_REG_MCR(0xcf54)
403 #define   INVALIDATION_BROADCAST_MODE_DIS	REG_BIT(12)
404 #define   GLOBAL_INVALIDATION_MODE		REG_BIT(2)
405 
406 #define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)
407 #define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)
408 
409 #define SAMPLER_INSTDONE			XE_REG_MCR(0xe160)
410 #define ROW_INSTDONE				XE_REG_MCR(0xe164)
411 
412 #define SAMPLER_MODE				XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
413 #define   ENABLE_SMALLPL			REG_BIT(15)
414 #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
415 #define   SAMPLER_ENABLE_HEADLESS_MSG		REG_BIT(5)
416 #define   INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
417 
418 #define HALF_SLICE_CHICKEN7				XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED)
419 #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
420 #define   CLEAR_OPTIMIZATION_DISABLE			REG_BIT(6)
421 
422 #define CACHE_MODE_SS				XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)
423 #define   DISABLE_ECC				REG_BIT(5)
424 #define   ENABLE_PREFETCH_INTO_IC		REG_BIT(3)
425 
426 #define ROW_CHICKEN4				XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED)
427 #define   DISABLE_GRF_CLEAR			REG_BIT(13)
428 #define   XEHP_DIS_BBL_SYSPIPE			REG_BIT(11)
429 #define   DISABLE_TDL_PUSH			REG_BIT(9)
430 #define   DIS_PICK_2ND_EU			REG_BIT(7)
431 #define   DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX	REG_BIT(4)
432 #define   THREAD_EX_ARB_MODE			REG_GENMASK(3, 2)
433 #define   THREAD_EX_ARB_MODE_RR_AFTER_DEP	REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
434 
435 #define ROW_CHICKEN3				XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED)
436 #define   XE2_EUPEND_CHK_FLUSH_DIS		REG_BIT(14)
437 #define   DIS_FIX_EOT1_FLUSH			REG_BIT(9)
438 
439 #define TDL_TSL_CHICKEN				XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED)
440 #define   STK_ID_RESTRICT			REG_BIT(12)
441 #define   SLM_WMTP_RESTORE			REG_BIT(11)
442 
443 #define ROW_CHICKEN				XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)
444 #define   UGM_BACKUP_MODE			REG_BIT(13)
445 #define   MDQ_ARBITRATION_MODE			REG_BIT(12)
446 #define   STALL_DOP_GATING_DISABLE		REG_BIT(5)
447 #define   EARLY_EOT_DIS				REG_BIT(1)
448 
449 #define ROW_CHICKEN2				XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED)
450 #define   DISABLE_READ_SUPPRESSION		REG_BIT(15)
451 #define   DISABLE_EARLY_READ			REG_BIT(14)
452 #define   ENABLE_LARGE_GRF_MODE			REG_BIT(12)
453 #define   PUSH_CONST_DEREF_HOLD_DIS		REG_BIT(8)
454 #define   DISABLE_TDL_SVHS_GATING		REG_BIT(1)
455 #define   DISABLE_DOP_GATING			REG_BIT(0)
456 
457 #define RT_CTRL					XE_REG_MCR(0xe530)
458 #define   DIS_NULL_QUERY			REG_BIT(10)
459 
460 #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK	XE_REG_MCR(0xe534)
461 #define   EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT	REG_BIT(31)
462 
463 #define XEHP_HDC_CHICKEN0					XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED)
464 #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK	REG_GENMASK(13, 11)
465 #define   DIS_ATOMIC_CHAINING_TYPED_WRITES	REG_BIT(3)
466 
467 #define LSC_CHICKEN_BIT_0			XE_REG_MCR(0xe7c8)
468 #define   DISABLE_D8_D16_COASLESCE		REG_BIT(30)
469 #define   WR_REQ_CHAINING_DIS			REG_BIT(26)
470 #define   TGM_WRITE_EOM_FORCE			REG_BIT(17)
471 #define   FORCE_1_SUB_MESSAGE_PER_FRAGMENT	REG_BIT(15)
472 #define   SEQUENTIAL_ACCESS_UPGRADE_DISABLE	REG_BIT(13)
473 
474 #define LSC_CHICKEN_BIT_0_UDW			XE_REG_MCR(0xe7c8 + 4)
475 #define   UGM_FRAGMENT_THRESHOLD_TO_3		REG_BIT(58 - 32)
476 #define   DIS_CHAIN_2XSIMD8			REG_BIT(55 - 32)
477 #define   XE2_ALLOC_DPA_STARVE_FIX_DIS		REG_BIT(47 - 32)
478 #define   ENABLE_SMP_LD_RENDER_SURFACE_CONTROL	REG_BIT(44 - 32)
479 #define   FORCE_SLM_FENCE_SCOPE_TO_TILE		REG_BIT(42 - 32)
480 #define   FORCE_UGM_FENCE_SCOPE_TO_TILE		REG_BIT(41 - 32)
481 #define   MAXREQS_PER_BANK			REG_GENMASK(39 - 32, 37 - 32)
482 #define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)
483 
484 #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
485 #define   COMP_CKN_IN				REG_GENMASK(30, 29)
486 
487 #define RCU_MODE				XE_REG(0x14800, XE_REG_OPTION_MASKED)
488 #define   RCU_MODE_FIXED_SLICE_CCS_MODE		REG_BIT(1)
489 #define   RCU_MODE_CCS_ENABLE			REG_BIT(0)
490 
491 /*
492  * Total of 4 cslices, where each cslice is in the form:
493  *   [0-3]     CCS ID
494  *   [4-6]     RSVD
495  *   [7]       Disabled
496  */
497 #define CCS_MODE				XE_REG(0x14804)
498 #define   CCS_MODE_CSLICE_0_3_MASK		REG_GENMASK(11, 0) /* 3 bits per cslice */
499 #define   CCS_MODE_CSLICE_MASK			0x7 /* CCS0-3 + rsvd */
500 #define   CCS_MODE_CSLICE_WIDTH			ilog2(CCS_MODE_CSLICE_MASK + 1)
501 #define   CCS_MODE_CSLICE(cslice, ccs) \
502 	((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH))
503 
504 #define FORCEWAKE_ACK_GT			XE_REG(0x130044)
505 
506 /* Applicable for all FORCEWAKE_DOMAIN and FORCEWAKE_ACK_DOMAIN regs */
507 #define   FORCEWAKE_KERNEL			0
508 #define   FORCEWAKE_MT(bit)			BIT(bit)
509 #define   FORCEWAKE_MT_MASK(bit)		BIT((bit) + 16)
510 
511 #define MTL_MEDIA_PERF_LIMIT_REASONS		XE_REG(0x138030)
512 #define MTL_MEDIA_MC6				XE_REG(0x138048)
513 
514 #define GT_CORE_STATUS				XE_REG(0x138060)
515 #define   RCN_MASK				REG_GENMASK(2, 0)
516 #define   GT_C0					0
517 #define   GT_C6					3
518 
519 #define GT_GFX_RC6_LOCKED			XE_REG(0x138104)
520 #define GT_GFX_RC6				XE_REG(0x138108)
521 
522 #define GT0_PERF_LIMIT_REASONS			XE_REG(0x1381a8)
523 #define   GT0_PERF_LIMIT_REASONS_MASK		0xde3
524 #define   PROCHOT_MASK				REG_BIT(0)
525 #define   THERMAL_LIMIT_MASK			REG_BIT(1)
526 #define   RATL_MASK				REG_BIT(5)
527 #define   VR_THERMALERT_MASK			REG_BIT(6)
528 #define   VR_TDC_MASK				REG_BIT(7)
529 #define   POWER_LIMIT_4_MASK			REG_BIT(8)
530 #define   POWER_LIMIT_1_MASK			REG_BIT(10)
531 #define   POWER_LIMIT_2_MASK			REG_BIT(11)
532 
533 #define GT_PERF_STATUS				XE_REG(0x1381b4)
534 #define   VOLTAGE_MASK				REG_GENMASK(10, 0)
535 
536 /*
537  * Note: Interrupt registers 1900xx are VF accessible only until version 12.50.
538  *       On newer platforms, VFs are using memory-based interrupts instead.
539  *       However, for simplicity we keep this XE_REG_OPTION_VF tag intact.
540  */
541 
542 #define GT_INTR_DW(x)				XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF)
543 #define   INTR_GSC				REG_BIT(31)
544 #define   INTR_GUC				REG_BIT(25)
545 #define   INTR_MGUC				REG_BIT(24)
546 #define   INTR_BCS8				REG_BIT(23)
547 #define   INTR_BCS(x)				REG_BIT(15 - (x))
548 #define   INTR_CCS(x)				REG_BIT(4 + (x))
549 #define   INTR_RCS0				REG_BIT(0)
550 #define   INTR_VECS(x)				REG_BIT(31 - (x))
551 #define   INTR_VCS(x)				REG_BIT(x)
552 
553 #define RENDER_COPY_INTR_ENABLE			XE_REG(0x190030, XE_REG_OPTION_VF)
554 #define VCS_VECS_INTR_ENABLE			XE_REG(0x190034, XE_REG_OPTION_VF)
555 #define GUC_SG_INTR_ENABLE			XE_REG(0x190038, XE_REG_OPTION_VF)
556 #define   ENGINE1_MASK				REG_GENMASK(31, 16)
557 #define   ENGINE0_MASK				REG_GENMASK(15, 0)
558 #define GPM_WGBOXPERF_INTR_ENABLE		XE_REG(0x19003c, XE_REG_OPTION_VF)
559 #define GUNIT_GSC_INTR_ENABLE			XE_REG(0x190044, XE_REG_OPTION_VF)
560 #define CCS_RSVD_INTR_ENABLE			XE_REG(0x190048, XE_REG_OPTION_VF)
561 
562 #define INTR_IDENTITY_REG(x)			XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF)
563 #define   INTR_DATA_VALID			REG_BIT(31)
564 #define   INTR_ENGINE_INSTANCE(x)		REG_FIELD_GET(GENMASK(25, 20), x)
565 #define   INTR_ENGINE_CLASS(x)			REG_FIELD_GET(GENMASK(18, 16), x)
566 #define   INTR_ENGINE_INTR(x)			REG_FIELD_GET(GENMASK(15, 0), x)
567 #define   OTHER_GUC_INSTANCE			0
568 #define   OTHER_GSC_HECI2_INSTANCE		3
569 #define   OTHER_GSC_INSTANCE			6
570 
571 #define IIR_REG_SELECTOR(x)			XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF)
572 #define RCS0_RSVD_INTR_MASK			XE_REG(0x190090, XE_REG_OPTION_VF)
573 #define BCS_RSVD_INTR_MASK			XE_REG(0x1900a0, XE_REG_OPTION_VF)
574 #define VCS0_VCS1_INTR_MASK			XE_REG(0x1900a8, XE_REG_OPTION_VF)
575 #define VCS2_VCS3_INTR_MASK			XE_REG(0x1900ac, XE_REG_OPTION_VF)
576 #define VECS0_VECS1_INTR_MASK			XE_REG(0x1900d0, XE_REG_OPTION_VF)
577 #define HECI2_RSVD_INTR_MASK			XE_REG(0x1900e4)
578 #define GUC_SG_INTR_MASK			XE_REG(0x1900e8, XE_REG_OPTION_VF)
579 #define GPM_WGBOXPERF_INTR_MASK			XE_REG(0x1900ec, XE_REG_OPTION_VF)
580 #define GUNIT_GSC_INTR_MASK			XE_REG(0x1900f4, XE_REG_OPTION_VF)
581 #define CCS0_CCS1_INTR_MASK			XE_REG(0x190100)
582 #define CCS2_CCS3_INTR_MASK			XE_REG(0x190104)
583 #define XEHPC_BCS1_BCS2_INTR_MASK		XE_REG(0x190110)
584 #define XEHPC_BCS3_BCS4_INTR_MASK		XE_REG(0x190114)
585 #define XEHPC_BCS5_BCS6_INTR_MASK		XE_REG(0x190118)
586 #define XEHPC_BCS7_BCS8_INTR_MASK		XE_REG(0x19011c)
587 #define   GT_WAIT_SEMAPHORE_INTERRUPT		REG_BIT(11)
588 #define   GT_CONTEXT_SWITCH_INTERRUPT		REG_BIT(8)
589 #define   GSC_ER_COMPLETE			REG_BIT(5)
590 #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT	REG_BIT(4)
591 #define   GT_CS_MASTER_ERROR_INTERRUPT		REG_BIT(3)
592 #define   GT_RENDER_USER_INTERRUPT		REG_BIT(0)
593 
594 #endif
595