1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2025 Intel Corporation 4 */ 5 6 #ifndef _XE_EU_STALL_REGS_H_ 7 #define _XE_EU_STALL_REGS_H_ 8 9 #include "regs/xe_reg_defs.h" 10 11 #define XEHPC_EUSTALL_BASE XE_REG_MCR(0xe520) 12 #define XEHPC_EUSTALL_BASE_BUF_ADDR REG_GENMASK(31, 6) 13 #define XEHPC_EUSTALL_BASE_XECORE_BUF_SZ REG_GENMASK(5, 3) 14 #define XEHPC_EUSTALL_BASE_ENABLE_SAMPLING REG_BIT(1) 15 16 #define XEHPC_EUSTALL_BASE_UPPER XE_REG_MCR(0xe524) 17 18 #define XEHPC_EUSTALL_REPORT XE_REG_MCR(0xe528, XE_REG_OPTION_MASKED) 19 #define XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK REG_GENMASK(15, 2) 20 #define XEHPC_EUSTALL_REPORT_OVERFLOW_DROP REG_BIT(1) 21 22 #define XEHPC_EUSTALL_REPORT1 XE_REG_MCR(0xe52c, XE_REG_OPTION_MASKED) 23 #define XEHPC_EUSTALL_REPORT1_READ_PTR_MASK REG_GENMASK(15, 2) 24 25 #define XEHPC_EUSTALL_CTRL XE_REG_MCR(0xe53c, XE_REG_OPTION_MASKED) 26 #define EUSTALL_MOCS REG_GENMASK(9, 3) 27 #define EUSTALL_SAMPLE_RATE REG_GENMASK(2, 0) 28 29 #endif 30