1*9a0b11d4SHarish Chegondi /* SPDX-License-Identifier: MIT */ 2*9a0b11d4SHarish Chegondi /* 3*9a0b11d4SHarish Chegondi * Copyright © 2025 Intel Corporation 4*9a0b11d4SHarish Chegondi */ 5*9a0b11d4SHarish Chegondi 6*9a0b11d4SHarish Chegondi #ifndef _XE_EU_STALL_REGS_H_ 7*9a0b11d4SHarish Chegondi #define _XE_EU_STALL_REGS_H_ 8*9a0b11d4SHarish Chegondi 9*9a0b11d4SHarish Chegondi #include "regs/xe_reg_defs.h" 10*9a0b11d4SHarish Chegondi 11*9a0b11d4SHarish Chegondi #define XEHPC_EUSTALL_BASE XE_REG_MCR(0xe520) 12*9a0b11d4SHarish Chegondi #define XEHPC_EUSTALL_BASE_BUF_ADDR REG_GENMASK(31, 6) 13*9a0b11d4SHarish Chegondi #define XEHPC_EUSTALL_BASE_XECORE_BUF_SZ REG_GENMASK(5, 3) 14*9a0b11d4SHarish Chegondi #define XEHPC_EUSTALL_BASE_ENABLE_SAMPLING REG_BIT(1) 15*9a0b11d4SHarish Chegondi 16*9a0b11d4SHarish Chegondi #define XEHPC_EUSTALL_BASE_UPPER XE_REG_MCR(0xe524) 17*9a0b11d4SHarish Chegondi 18*9a0b11d4SHarish Chegondi #define XEHPC_EUSTALL_REPORT XE_REG_MCR(0xe528, XE_REG_OPTION_MASKED) 19*9a0b11d4SHarish Chegondi #define XEHPC_EUSTALL_REPORT_WRITE_PTR_MASK REG_GENMASK(15, 2) 20*9a0b11d4SHarish Chegondi #define XEHPC_EUSTALL_REPORT_OVERFLOW_DROP REG_BIT(1) 21*9a0b11d4SHarish Chegondi 22*9a0b11d4SHarish Chegondi #define XEHPC_EUSTALL_REPORT1 XE_REG_MCR(0xe52c, XE_REG_OPTION_MASKED) 23*9a0b11d4SHarish Chegondi #define XEHPC_EUSTALL_REPORT1_READ_PTR_MASK REG_GENMASK(15, 2) 24*9a0b11d4SHarish Chegondi 25*9a0b11d4SHarish Chegondi #define XEHPC_EUSTALL_CTRL XE_REG_MCR(0xe53c, XE_REG_OPTION_MASKED) 26*9a0b11d4SHarish Chegondi #define EUSTALL_MOCS REG_GENMASK(9, 3) 27*9a0b11d4SHarish Chegondi #define EUSTALL_SAMPLE_RATE REG_GENMASK(2, 0) 28*9a0b11d4SHarish Chegondi 29*9a0b11d4SHarish Chegondi #endif 30