1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_ENGINE_REGS_H_ 7 #define _XE_ENGINE_REGS_H_ 8 9 #include <asm/page.h> 10 11 #include "regs/xe_reg_defs.h" 12 13 /* 14 * These *_BASE values represent the MMIO offset where each hardware engine's 15 * registers start. The other definitions in this header are parameterized 16 * macros that will take one of these values as a parameter. 17 */ 18 #define RENDER_RING_BASE 0x02000 19 #define BSD_RING_BASE 0x1c0000 20 #define BSD2_RING_BASE 0x1c4000 21 #define BSD3_RING_BASE 0x1d0000 22 #define BSD4_RING_BASE 0x1d4000 23 #define XEHP_BSD5_RING_BASE 0x1e0000 24 #define XEHP_BSD6_RING_BASE 0x1e4000 25 #define XEHP_BSD7_RING_BASE 0x1f0000 26 #define XEHP_BSD8_RING_BASE 0x1f4000 27 #define VEBOX_RING_BASE 0x1c8000 28 #define VEBOX2_RING_BASE 0x1d8000 29 #define XEHP_VEBOX3_RING_BASE 0x1e8000 30 #define XEHP_VEBOX4_RING_BASE 0x1f8000 31 #define COMPUTE0_RING_BASE 0x1a000 32 #define COMPUTE1_RING_BASE 0x1c000 33 #define COMPUTE2_RING_BASE 0x1e000 34 #define COMPUTE3_RING_BASE 0x26000 35 #define BLT_RING_BASE 0x22000 36 #define XEHPC_BCS1_RING_BASE 0x3e0000 37 #define XEHPC_BCS2_RING_BASE 0x3e2000 38 #define XEHPC_BCS3_RING_BASE 0x3e4000 39 #define XEHPC_BCS4_RING_BASE 0x3e6000 40 #define XEHPC_BCS5_RING_BASE 0x3e8000 41 #define XEHPC_BCS6_RING_BASE 0x3ea000 42 #define XEHPC_BCS7_RING_BASE 0x3ec000 43 #define XEHPC_BCS8_RING_BASE 0x3ee000 44 #define GSCCS_RING_BASE 0x11a000 45 46 #define RING_TAIL(base) XE_REG((base) + 0x30) 47 48 #define RING_HEAD(base) XE_REG((base) + 0x34) 49 #define HEAD_ADDR 0x001FFFFC 50 51 #define RING_START(base) XE_REG((base) + 0x38) 52 53 #define RING_CTL(base) XE_REG((base) + 0x3c) 54 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 55 #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 56 57 #define RING_PSMI_CTL(base) XE_REG((base) + 0x50, XE_REG_OPTION_MASKED) 58 #define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12) 59 #define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7) 60 #define IDLE_MSG_DISABLE REG_BIT(0) 61 62 #define RING_PWRCTX_MAXCNT(base) XE_REG((base) + 0x54) 63 #define IDLE_WAIT_TIME REG_GENMASK(19, 0) 64 65 #define RING_ACTHD_UDW(base) XE_REG((base) + 0x5c) 66 #define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60) 67 #define RING_IPEHR(base) XE_REG((base) + 0x68) 68 #define RING_ACTHD(base) XE_REG((base) + 0x74) 69 #define RING_DMA_FADD(base) XE_REG((base) + 0x78) 70 #define RING_HWS_PGA(base) XE_REG((base) + 0x80) 71 #define RING_HWSTAM(base) XE_REG((base) + 0x98) 72 #define RING_MI_MODE(base) XE_REG((base) + 0x9c) 73 #define RING_NOPID(base) XE_REG((base) + 0x94) 74 75 #define FF_THREAD_MODE(base) XE_REG((base) + 0xa0) 76 #define FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 77 78 #define RING_INT_SRC_RPT_PTR(base) XE_REG((base) + 0xa4) 79 #define RING_IMR(base) XE_REG((base) + 0xa8) 80 #define RING_INT_STATUS_RPT_PTR(base) XE_REG((base) + 0xac) 81 82 #define RING_EIR(base) XE_REG((base) + 0xb0) 83 #define RING_EMR(base) XE_REG((base) + 0xb4) 84 #define RING_ESR(base) XE_REG((base) + 0xb8) 85 86 #define INSTPM(base) XE_REG((base) + 0xc0, XE_REG_OPTION_MASKED) 87 #define ENABLE_SEMAPHORE_POLL_BIT REG_BIT(13) 88 89 #define RING_CMD_CCTL(base) XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED) 90 /* 91 * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. 92 * The lsb of each can be considered a separate enabling bit for encryption. 93 * 6:0 == default MOCS value for reads => 6:1 == table index for reads. 94 * 13:7 == default MOCS value for writes => 13:8 == table index for writes. 95 * 15:14 == Reserved => 31:30 are set to 0. 96 */ 97 #define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 8) 98 #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 1) 99 100 #define CSFE_CHICKEN1(base) XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED) 101 #define GHWSP_CSB_REPORT_DIS REG_BIT(15) 102 #define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14) 103 104 #define FF_SLICE_CS_CHICKEN1(base) XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED) 105 #define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14) 106 107 #define CS_DEBUG_MODE1(base) XE_REG((base) + 0xec, XE_REG_OPTION_MASKED) 108 #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) 109 #define REPLAY_MODE_GRANULARITY REG_BIT(0) 110 111 #define RING_BBADDR(base) XE_REG((base) + 0x140) 112 #define RING_BBADDR_UDW(base) XE_REG((base) + 0x168) 113 114 #define BCS_SWCTRL(base) XE_REG((base) + 0x200, XE_REG_OPTION_MASKED) 115 #define BCS_SWCTRL_DISABLE_256B REG_BIT(2) 116 117 /* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */ 118 #define BLIT_CCTL(base) XE_REG((base) + 0x204) 119 #define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 9) 120 #define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 1) 121 122 #define RING_EXECLIST_STATUS_LO(base) XE_REG((base) + 0x234) 123 #define RING_EXECLIST_STATUS_HI(base) XE_REG((base) + 0x234 + 4) 124 125 #define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244, XE_REG_OPTION_MASKED) 126 #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3) 127 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0) 128 129 #define RING_MODE(base) XE_REG((base) + 0x29c) 130 #define GFX_DISABLE_LEGACY_MODE REG_BIT(3) 131 132 #define RING_TIMESTAMP(base) XE_REG((base) + 0x358) 133 134 #define RING_TIMESTAMP_UDW(base) XE_REG((base) + 0x358 + 4) 135 #define RING_VALID_MASK 0x00000001 136 #define RING_VALID 0x00000001 137 #define STOP_RING REG_BIT(8) 138 #define TAIL_ADDR 0x001FFFF8 139 140 #define RING_CTX_TIMESTAMP(base) XE_REG((base) + 0x3a8) 141 #define CSBE_DEBUG_STATUS(base) XE_REG((base) + 0x3fc) 142 143 #define RING_FORCE_TO_NONPRIV(base, i) XE_REG(((base) + 0x4d0) + (i) * 4) 144 #define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30) 145 #define RING_FORCE_TO_NONPRIV_ACCESS_MASK REG_GENMASK(29, 28) 146 #define RING_FORCE_TO_NONPRIV_ACCESS_RW REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 0) 147 #define RING_FORCE_TO_NONPRIV_ACCESS_RD REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 1) 148 #define RING_FORCE_TO_NONPRIV_ACCESS_WR REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 2) 149 #define RING_FORCE_TO_NONPRIV_ACCESS_INVALID REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 3) 150 #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2) 151 #define RING_FORCE_TO_NONPRIV_RANGE_MASK REG_GENMASK(1, 0) 152 #define RING_FORCE_TO_NONPRIV_RANGE_1 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 0) 153 #define RING_FORCE_TO_NONPRIV_RANGE_4 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 1) 154 #define RING_FORCE_TO_NONPRIV_RANGE_16 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 2) 155 #define RING_FORCE_TO_NONPRIV_RANGE_64 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 3) 156 #define RING_FORCE_TO_NONPRIV_MASK_VALID (RING_FORCE_TO_NONPRIV_RANGE_MASK | \ 157 RING_FORCE_TO_NONPRIV_ACCESS_MASK | \ 158 RING_FORCE_TO_NONPRIV_DENY) 159 #define RING_MAX_NONPRIV_SLOTS 12 160 161 #define RING_EXECLIST_SQ_CONTENTS_LO(base) XE_REG((base) + 0x510) 162 #define RING_EXECLIST_SQ_CONTENTS_HI(base) XE_REG((base) + 0x510 + 4) 163 164 #define RING_EXECLIST_CONTROL(base) XE_REG((base) + 0x550) 165 #define EL_CTRL_LOAD REG_BIT(0) 166 167 #define CS_CHICKEN1(base) XE_REG((base) + 0x580, XE_REG_OPTION_MASKED) 168 #define PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) 169 #define PREEMPT_GPGPU_MID_THREAD_LEVEL PREEMPT_GPGPU_LEVEL(0, 0) 170 #define PREEMPT_GPGPU_THREAD_GROUP_LEVEL PREEMPT_GPGPU_LEVEL(0, 1) 171 #define PREEMPT_GPGPU_COMMAND_LEVEL PREEMPT_GPGPU_LEVEL(1, 0) 172 #define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1) 173 #define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0) 174 175 #define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08) 176 #define CG3DDISHRS_CLKGATE_DIS REG_BIT(5) 177 178 #define VDBOX_CGCTL3F10(base) XE_REG((base) + 0x3f10) 179 #define IECPUNIT_CLKGATE_DIS REG_BIT(22) 180 181 #define VDBOX_CGCTL3F18(base) XE_REG((base) + 0x3f18) 182 #define ALNUNIT_CLKGATE_DIS REG_BIT(13) 183 184 #define VDBOX_CGCTL3F1C(base) XE_REG((base) + 0x3f1c) 185 #define MFXPIPE_CLKGATE_DIS REG_BIT(3) 186 187 #endif 188