1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef _XE_GPU_COMMANDS_H_ 7 #define _XE_GPU_COMMANDS_H_ 8 9 #include "regs/xe_reg_defs.h" 10 11 #define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3) 12 #define SRC_ACCESS_TYPE_SHIFT 21 13 #define DST_ACCESS_TYPE_SHIFT 20 14 #define CCS_SIZE_MASK GENMASK(17, 8) 15 #define XE2_CCS_SIZE_MASK GENMASK(18, 9) 16 #define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 26) 17 #define XE2_XY_CTRL_SURF_MOCS_INDEX_MASK GENMASK(31, 28) 18 #define NUM_CCS_BYTES_PER_BLOCK 256 19 #define NUM_BYTES_PER_CCS_BYTE(_xe) (GRAPHICS_VER(_xe) >= 20 ? 512 : 256) 20 21 #define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22) 22 #define XY_FAST_COLOR_BLT_DEPTH_32 (2 << 19) 23 #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 22) 24 #define XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_MASK GENMASK(27, 24) 25 #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31 26 27 #define XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22) 28 #define XY_FAST_COPY_BLT_DEPTH_32 (3<<24) 29 #define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31) 30 #define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30) 31 #define XE2_XY_FAST_COPY_BLT_MOCS_INDEX_MASK GENMASK(23, 20) 32 33 #define MEM_COPY_CMD (2 << 29 | 0x5a << 22) 34 #define MEM_COPY_PAGE_COPY_MODE REG_BIT(19) 35 #define MEM_COPY_MATRIX_COPY REG_BIT(17) 36 #define MEM_COPY_SRC_MOCS_INDEX_MASK GENMASK(31, 28) 37 #define MEM_COPY_DST_MOCS_INDEX_MASK GENMASK(6, 3) 38 39 #define PVC_MEM_SET_CMD (2 << 29 | 0x5b << 22) 40 #define PVC_MEM_SET_MATRIX REG_BIT(17) 41 #define PVC_MEM_SET_DATA_FIELD GENMASK(31, 24) 42 /* Bspec lists field as [6:0], but index alone is from [6:1] */ 43 #define PVC_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 1) 44 #define XE2_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 3) 45 46 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) 47 48 #define PIPE_CONTROL0_QUEUE_DRAIN_MODE BIT(12) 49 #define PIPE_CONTROL0_L3_READ_ONLY_CACHE_INVALIDATE BIT(10) /* gen12 */ 50 #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */ 51 52 #define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29) 53 #define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28) 54 #define PIPE_CONTROL_AMFS_FLUSH (1<<25) 55 #define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) 56 #define PIPE_CONTROL_LRI_POST_SYNC BIT(23) 57 #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) 58 #define PIPE_CONTROL_CS_STALL (1<<20) 59 #define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19) 60 #define PIPE_CONTROL_TLB_INVALIDATE BIT(18) 61 #define PIPE_CONTROL_PSD_SYNC (1<<17) 62 #define PIPE_CONTROL_QW_WRITE (1<<14) 63 #define PIPE_CONTROL_DEPTH_STALL (1<<13) 64 #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) 65 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) 66 #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) 67 #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9) 68 #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) 69 #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5) 70 #define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4) 71 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) 72 #define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2) 73 #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1) 74 #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0) 75 76 #endif 77