1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 /* for ioread64 */ 7 #include <linux/io-64-nonatomic-lo-hi.h> 8 9 #include "regs/xe_gtt_defs.h" 10 #include "xe_ggtt.h" 11 12 #include "intel_atomic_plane.h" 13 #include "intel_crtc.h" 14 #include "intel_display.h" 15 #include "intel_display_types.h" 16 #include "intel_fb.h" 17 #include "intel_fb_pin.h" 18 #include "intel_frontbuffer.h" 19 #include "intel_plane_initial.h" 20 #include "xe_bo.h" 21 22 static bool 23 intel_reuse_initial_plane_obj(struct intel_crtc *this, 24 const struct intel_initial_plane_config plane_configs[], 25 struct drm_framebuffer **fb) 26 { 27 struct xe_device *xe = to_xe_device(this->base.dev); 28 struct intel_crtc *crtc; 29 30 for_each_intel_crtc(&xe->drm, crtc) { 31 struct intel_plane *plane = 32 to_intel_plane(crtc->base.primary); 33 const struct intel_plane_state *plane_state = 34 to_intel_plane_state(plane->base.state); 35 const struct intel_crtc_state *crtc_state = 36 to_intel_crtc_state(crtc->base.state); 37 38 if (!crtc_state->uapi.active) 39 continue; 40 41 if (!plane_state->ggtt_vma) 42 continue; 43 44 if (plane_configs[this->pipe].base == plane_configs[crtc->pipe].base) { 45 *fb = plane_state->hw.fb; 46 return true; 47 } 48 } 49 50 return false; 51 } 52 53 static struct xe_bo * 54 initial_plane_bo(struct xe_device *xe, 55 struct intel_initial_plane_config *plane_config) 56 { 57 struct xe_tile *tile0 = xe_device_get_root_tile(xe); 58 struct xe_bo *bo; 59 resource_size_t phys_base; 60 u32 base, size, flags; 61 u64 page_size = xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K; 62 63 if (plane_config->size == 0) 64 return NULL; 65 66 flags = XE_BO_FLAG_PINNED | XE_BO_FLAG_SCANOUT | XE_BO_FLAG_GGTT; 67 68 base = round_down(plane_config->base, page_size); 69 if (IS_DGFX(xe)) { 70 u64 __iomem *gte = tile0->mem.ggtt->gsm; 71 u64 pte; 72 73 gte += base / XE_PAGE_SIZE; 74 75 pte = ioread64(gte); 76 if (!(pte & XE_GGTT_PTE_DM)) { 77 drm_err(&xe->drm, 78 "Initial plane programming missing DM bit\n"); 79 return NULL; 80 } 81 82 phys_base = pte & ~(page_size - 1); 83 flags |= XE_BO_FLAG_VRAM0; 84 85 /* 86 * We don't currently expect this to ever be placed in the 87 * stolen portion. 88 */ 89 if (phys_base >= tile0->mem.vram.usable_size) { 90 drm_err(&xe->drm, 91 "Initial plane programming using invalid range, phys_base=%pa\n", 92 &phys_base); 93 return NULL; 94 } 95 96 drm_dbg(&xe->drm, 97 "Using phys_base=%pa, based on initial plane programming\n", 98 &phys_base); 99 } else { 100 struct ttm_resource_manager *stolen = ttm_manager_type(&xe->ttm, XE_PL_STOLEN); 101 102 if (!stolen) 103 return NULL; 104 phys_base = base; 105 flags |= XE_BO_FLAG_STOLEN; 106 107 /* 108 * If the FB is too big, just don't use it since fbdev is not very 109 * important and we should probably use that space with FBC or other 110 * features. 111 */ 112 if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) && 113 plane_config->size * 2 >> PAGE_SHIFT >= stolen->size) 114 return NULL; 115 } 116 117 size = round_up(plane_config->base + plane_config->size, 118 page_size); 119 size -= base; 120 121 bo = xe_bo_create_pin_map_at(xe, tile0, NULL, size, phys_base, 122 ttm_bo_type_kernel, flags); 123 if (IS_ERR(bo)) { 124 drm_dbg(&xe->drm, 125 "Failed to create bo phys_base=%pa size %u with flags %x: %li\n", 126 &phys_base, size, flags, PTR_ERR(bo)); 127 return NULL; 128 } 129 130 return bo; 131 } 132 133 static bool 134 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, 135 struct intel_initial_plane_config *plane_config) 136 { 137 struct xe_device *xe = to_xe_device(crtc->base.dev); 138 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 139 struct drm_framebuffer *fb = &plane_config->fb->base; 140 struct xe_bo *bo; 141 142 switch (fb->modifier) { 143 case DRM_FORMAT_MOD_LINEAR: 144 case I915_FORMAT_MOD_X_TILED: 145 case I915_FORMAT_MOD_Y_TILED: 146 case I915_FORMAT_MOD_4_TILED: 147 break; 148 default: 149 drm_dbg_kms(&xe->drm, 150 "Unsupported modifier for initial FB: 0x%llx\n", 151 fb->modifier); 152 return false; 153 } 154 155 mode_cmd.pixel_format = fb->format->format; 156 mode_cmd.width = fb->width; 157 mode_cmd.height = fb->height; 158 mode_cmd.pitches[0] = fb->pitches[0]; 159 mode_cmd.modifier[0] = fb->modifier; 160 mode_cmd.flags = DRM_MODE_FB_MODIFIERS; 161 162 bo = initial_plane_bo(xe, plane_config); 163 if (!bo) 164 return false; 165 166 if (intel_framebuffer_init(to_intel_framebuffer(fb), 167 bo, &mode_cmd)) { 168 drm_dbg_kms(&xe->drm, "intel fb init failed\n"); 169 goto err_bo; 170 } 171 /* Reference handed over to fb */ 172 xe_bo_put(bo); 173 174 return true; 175 176 err_bo: 177 xe_bo_unpin_map_no_vm(bo); 178 return false; 179 } 180 181 static void 182 intel_find_initial_plane_obj(struct intel_crtc *crtc, 183 struct intel_initial_plane_config plane_configs[]) 184 { 185 struct intel_initial_plane_config *plane_config = 186 &plane_configs[crtc->pipe]; 187 struct intel_plane *plane = 188 to_intel_plane(crtc->base.primary); 189 struct intel_plane_state *plane_state = 190 to_intel_plane_state(plane->base.state); 191 struct intel_crtc_state *crtc_state = 192 to_intel_crtc_state(crtc->base.state); 193 struct drm_framebuffer *fb; 194 struct i915_vma *vma; 195 196 /* 197 * TODO: 198 * Disable planes if get_initial_plane_config() failed. 199 * Make sure things work if the surface base is not page aligned. 200 */ 201 if (!plane_config->fb) 202 return; 203 204 if (intel_alloc_initial_plane_obj(crtc, plane_config)) 205 fb = &plane_config->fb->base; 206 else if (!intel_reuse_initial_plane_obj(crtc, plane_configs, &fb)) 207 goto nofb; 208 209 plane_state->uapi.rotation = plane_config->rotation; 210 intel_fb_fill_view(to_intel_framebuffer(fb), 211 plane_state->uapi.rotation, &plane_state->view); 212 213 vma = intel_fb_pin_to_ggtt(fb, &plane_state->view.gtt, 214 0, 0, false, &plane_state->flags); 215 if (IS_ERR(vma)) 216 goto nofb; 217 218 plane_state->ggtt_vma = vma; 219 plane_state->uapi.src_x = 0; 220 plane_state->uapi.src_y = 0; 221 plane_state->uapi.src_w = fb->width << 16; 222 plane_state->uapi.src_h = fb->height << 16; 223 224 plane_state->uapi.crtc_x = 0; 225 plane_state->uapi.crtc_y = 0; 226 plane_state->uapi.crtc_w = fb->width; 227 plane_state->uapi.crtc_h = fb->height; 228 229 plane_state->uapi.fb = fb; 230 drm_framebuffer_get(fb); 231 232 plane_state->uapi.crtc = &crtc->base; 233 intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc); 234 235 atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits); 236 237 plane_config->vma = vma; 238 239 /* 240 * Flip to the newly created mapping ASAP, so we can re-use the 241 * first part of GGTT for WOPCM, prevent flickering, and prevent 242 * the lookup of sysmem scratch pages. 243 */ 244 plane->check_plane(crtc_state, plane_state); 245 plane->async_flip(plane, crtc_state, plane_state, true); 246 return; 247 248 nofb: 249 /* 250 * We've failed to reconstruct the BIOS FB. Current display state 251 * indicates that the primary plane is visible, but has a NULL FB, 252 * which will lead to problems later if we don't fix it up. The 253 * simplest solution is to just disable the primary plane now and 254 * pretend the BIOS never had it enabled. 255 */ 256 intel_plane_disable_noatomic(crtc, plane); 257 } 258 259 static void plane_config_fini(struct intel_initial_plane_config *plane_config) 260 { 261 if (plane_config->fb) { 262 struct drm_framebuffer *fb = &plane_config->fb->base; 263 264 /* We may only have the stub and not a full framebuffer */ 265 if (drm_framebuffer_read_refcount(fb)) 266 drm_framebuffer_put(fb); 267 else 268 kfree(fb); 269 } 270 } 271 272 void intel_initial_plane_config(struct drm_i915_private *i915) 273 { 274 struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {}; 275 struct intel_crtc *crtc; 276 277 for_each_intel_crtc(&i915->drm, crtc) { 278 struct intel_initial_plane_config *plane_config = 279 &plane_configs[crtc->pipe]; 280 281 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 282 continue; 283 284 /* 285 * Note that reserving the BIOS fb up front prevents us 286 * from stuffing other stolen allocations like the ring 287 * on top. This prevents some ugliness at boot time, and 288 * can even allow for smooth boot transitions if the BIOS 289 * fb is large enough for the active pipe configuration. 290 */ 291 i915->display.funcs.display->get_initial_plane_config(crtc, plane_config); 292 293 /* 294 * If the fb is shared between multiple heads, we'll 295 * just get the first one. 296 */ 297 intel_find_initial_plane_obj(crtc, plane_configs); 298 299 if (i915->display.funcs.display->fixup_initial_plane_config(crtc, plane_config)) 300 intel_crtc_wait_for_next_vblank(crtc); 301 302 plane_config_fini(plane_config); 303 } 304 } 305