1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 /* for ioread64 */ 7 #include <linux/io-64-nonatomic-lo-hi.h> 8 9 #include "regs/xe_gtt_defs.h" 10 #include "xe_ggtt.h" 11 12 #include "i915_drv.h" 13 #include "intel_atomic_plane.h" 14 #include "intel_crtc.h" 15 #include "intel_display.h" 16 #include "intel_display_types.h" 17 #include "intel_fb.h" 18 #include "intel_fb_pin.h" 19 #include "intel_frontbuffer.h" 20 #include "intel_plane_initial.h" 21 22 static bool 23 intel_reuse_initial_plane_obj(struct intel_crtc *this, 24 const struct intel_initial_plane_config plane_configs[], 25 struct drm_framebuffer **fb) 26 { 27 struct drm_i915_private *i915 = to_i915(this->base.dev); 28 struct intel_crtc *crtc; 29 30 for_each_intel_crtc(&i915->drm, crtc) { 31 struct intel_plane *plane = 32 to_intel_plane(crtc->base.primary); 33 const struct intel_plane_state *plane_state = 34 to_intel_plane_state(plane->base.state); 35 const struct intel_crtc_state *crtc_state = 36 to_intel_crtc_state(crtc->base.state); 37 38 if (!crtc_state->uapi.active) 39 continue; 40 41 if (!plane_state->ggtt_vma) 42 continue; 43 44 if (plane_configs[this->pipe].base == plane_configs[crtc->pipe].base) { 45 *fb = plane_state->hw.fb; 46 return true; 47 } 48 } 49 50 return false; 51 } 52 53 static struct xe_bo * 54 initial_plane_bo(struct xe_device *xe, 55 struct intel_initial_plane_config *plane_config) 56 { 57 struct xe_tile *tile0 = xe_device_get_root_tile(xe); 58 struct xe_bo *bo; 59 resource_size_t phys_base; 60 u32 base, size, flags; 61 u64 page_size = xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K; 62 63 if (plane_config->size == 0) 64 return NULL; 65 66 flags = XE_BO_FLAG_PINNED | XE_BO_FLAG_SCANOUT | XE_BO_FLAG_GGTT; 67 68 base = round_down(plane_config->base, page_size); 69 if (IS_DGFX(xe)) { 70 u64 __iomem *gte = tile0->mem.ggtt->gsm; 71 u64 pte; 72 73 gte += base / XE_PAGE_SIZE; 74 75 pte = ioread64(gte); 76 if (!(pte & XE_GGTT_PTE_DM)) { 77 drm_err(&xe->drm, 78 "Initial plane programming missing DM bit\n"); 79 return NULL; 80 } 81 82 phys_base = pte & ~(page_size - 1); 83 flags |= XE_BO_FLAG_VRAM0; 84 85 /* 86 * We don't currently expect this to ever be placed in the 87 * stolen portion. 88 */ 89 if (phys_base >= tile0->mem.vram.usable_size) { 90 drm_err(&xe->drm, 91 "Initial plane programming using invalid range, phys_base=%pa\n", 92 &phys_base); 93 return NULL; 94 } 95 96 drm_dbg(&xe->drm, 97 "Using phys_base=%pa, based on initial plane programming\n", 98 &phys_base); 99 } else { 100 struct ttm_resource_manager *stolen = ttm_manager_type(&xe->ttm, XE_PL_STOLEN); 101 102 if (!stolen) 103 return NULL; 104 phys_base = base; 105 flags |= XE_BO_FLAG_STOLEN; 106 107 /* 108 * If the FB is too big, just don't use it since fbdev is not very 109 * important and we should probably use that space with FBC or other 110 * features. 111 */ 112 if (IS_ENABLED(CONFIG_FRAMEBUFFER_CONSOLE) && 113 plane_config->size * 2 >> PAGE_SHIFT >= stolen->size) 114 return NULL; 115 } 116 117 size = round_up(plane_config->base + plane_config->size, 118 page_size); 119 size -= base; 120 121 bo = xe_bo_create_pin_map_at(xe, tile0, NULL, size, phys_base, 122 ttm_bo_type_kernel, flags); 123 if (IS_ERR(bo)) { 124 drm_dbg(&xe->drm, 125 "Failed to create bo phys_base=%pa size %u with flags %x: %li\n", 126 &phys_base, size, flags, PTR_ERR(bo)); 127 return NULL; 128 } 129 130 return bo; 131 } 132 133 static bool 134 intel_alloc_initial_plane_obj(struct intel_crtc *crtc, 135 struct intel_initial_plane_config *plane_config) 136 { 137 struct drm_device *dev = crtc->base.dev; 138 struct drm_i915_private *dev_priv = to_i915(dev); 139 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 140 struct drm_framebuffer *fb = &plane_config->fb->base; 141 struct xe_bo *bo; 142 143 switch (fb->modifier) { 144 case DRM_FORMAT_MOD_LINEAR: 145 case I915_FORMAT_MOD_X_TILED: 146 case I915_FORMAT_MOD_Y_TILED: 147 case I915_FORMAT_MOD_4_TILED: 148 break; 149 default: 150 drm_dbg(&dev_priv->drm, 151 "Unsupported modifier for initial FB: 0x%llx\n", 152 fb->modifier); 153 return false; 154 } 155 156 mode_cmd.pixel_format = fb->format->format; 157 mode_cmd.width = fb->width; 158 mode_cmd.height = fb->height; 159 mode_cmd.pitches[0] = fb->pitches[0]; 160 mode_cmd.modifier[0] = fb->modifier; 161 mode_cmd.flags = DRM_MODE_FB_MODIFIERS; 162 163 bo = initial_plane_bo(dev_priv, plane_config); 164 if (!bo) 165 return false; 166 167 if (intel_framebuffer_init(to_intel_framebuffer(fb), 168 bo, &mode_cmd)) { 169 drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n"); 170 goto err_bo; 171 } 172 /* Reference handed over to fb */ 173 xe_bo_put(bo); 174 175 return true; 176 177 err_bo: 178 xe_bo_unpin_map_no_vm(bo); 179 return false; 180 } 181 182 static void 183 intel_find_initial_plane_obj(struct intel_crtc *crtc, 184 struct intel_initial_plane_config plane_configs[]) 185 { 186 struct intel_initial_plane_config *plane_config = 187 &plane_configs[crtc->pipe]; 188 struct intel_plane *plane = 189 to_intel_plane(crtc->base.primary); 190 struct intel_plane_state *plane_state = 191 to_intel_plane_state(plane->base.state); 192 struct intel_crtc_state *crtc_state = 193 to_intel_crtc_state(crtc->base.state); 194 struct drm_framebuffer *fb; 195 struct i915_vma *vma; 196 197 /* 198 * TODO: 199 * Disable planes if get_initial_plane_config() failed. 200 * Make sure things work if the surface base is not page aligned. 201 */ 202 if (!plane_config->fb) 203 return; 204 205 if (intel_alloc_initial_plane_obj(crtc, plane_config)) 206 fb = &plane_config->fb->base; 207 else if (!intel_reuse_initial_plane_obj(crtc, plane_configs, &fb)) 208 goto nofb; 209 210 plane_state->uapi.rotation = plane_config->rotation; 211 intel_fb_fill_view(to_intel_framebuffer(fb), 212 plane_state->uapi.rotation, &plane_state->view); 213 214 vma = intel_pin_and_fence_fb_obj(fb, false, &plane_state->view.gtt, 215 false, &plane_state->flags); 216 if (IS_ERR(vma)) 217 goto nofb; 218 219 plane_state->ggtt_vma = vma; 220 plane_state->uapi.src_x = 0; 221 plane_state->uapi.src_y = 0; 222 plane_state->uapi.src_w = fb->width << 16; 223 plane_state->uapi.src_h = fb->height << 16; 224 225 plane_state->uapi.crtc_x = 0; 226 plane_state->uapi.crtc_y = 0; 227 plane_state->uapi.crtc_w = fb->width; 228 plane_state->uapi.crtc_h = fb->height; 229 230 plane_state->uapi.fb = fb; 231 drm_framebuffer_get(fb); 232 233 plane_state->uapi.crtc = &crtc->base; 234 intel_plane_copy_uapi_to_hw_state(plane_state, plane_state, crtc); 235 236 atomic_or(plane->frontbuffer_bit, &to_intel_frontbuffer(fb)->bits); 237 238 plane_config->vma = vma; 239 240 /* 241 * Flip to the newly created mapping ASAP, so we can re-use the 242 * first part of GGTT for WOPCM, prevent flickering, and prevent 243 * the lookup of sysmem scratch pages. 244 */ 245 plane->check_plane(crtc_state, plane_state); 246 plane->async_flip(plane, crtc_state, plane_state, true); 247 return; 248 249 nofb: 250 /* 251 * We've failed to reconstruct the BIOS FB. Current display state 252 * indicates that the primary plane is visible, but has a NULL FB, 253 * which will lead to problems later if we don't fix it up. The 254 * simplest solution is to just disable the primary plane now and 255 * pretend the BIOS never had it enabled. 256 */ 257 intel_plane_disable_noatomic(crtc, plane); 258 } 259 260 static void plane_config_fini(struct intel_initial_plane_config *plane_config) 261 { 262 if (plane_config->fb) { 263 struct drm_framebuffer *fb = &plane_config->fb->base; 264 265 /* We may only have the stub and not a full framebuffer */ 266 if (drm_framebuffer_read_refcount(fb)) 267 drm_framebuffer_put(fb); 268 else 269 kfree(fb); 270 } 271 } 272 273 void intel_initial_plane_config(struct drm_i915_private *i915) 274 { 275 struct intel_initial_plane_config plane_configs[I915_MAX_PIPES] = {}; 276 struct intel_crtc *crtc; 277 278 for_each_intel_crtc(&i915->drm, crtc) { 279 struct intel_initial_plane_config *plane_config = 280 &plane_configs[crtc->pipe]; 281 282 if (!to_intel_crtc_state(crtc->base.state)->uapi.active) 283 continue; 284 285 /* 286 * Note that reserving the BIOS fb up front prevents us 287 * from stuffing other stolen allocations like the ring 288 * on top. This prevents some ugliness at boot time, and 289 * can even allow for smooth boot transitions if the BIOS 290 * fb is large enough for the active pipe configuration. 291 */ 292 i915->display.funcs.display->get_initial_plane_config(crtc, plane_config); 293 294 /* 295 * If the fb is shared between multiple heads, we'll 296 * just get the first one. 297 */ 298 intel_find_initial_plane_obj(crtc, plane_configs); 299 300 if (i915->display.funcs.display->fixup_initial_plane_config(crtc, plane_config)) 301 intel_crtc_wait_for_next_vblank(crtc); 302 303 plane_config_fini(plane_config); 304 } 305 } 306