1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2021 Intel Corporation 4 */ 5 6 #include <drm/ttm/ttm_bo.h> 7 8 #include "i915_vma.h" 9 #include "intel_display_core.h" 10 #include "intel_display_types.h" 11 #include "intel_dpt.h" 12 #include "intel_fb.h" 13 #include "intel_fb_pin.h" 14 #include "intel_fbdev.h" 15 #include "xe_bo.h" 16 #include "xe_device.h" 17 #include "xe_ggtt.h" 18 #include "xe_pm.h" 19 20 static void 21 write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_ofs, 22 u32 width, u32 height, u32 src_stride, u32 dst_stride) 23 { 24 struct xe_device *xe = xe_bo_device(bo); 25 struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt; 26 u32 column, row; 27 u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]); 28 29 /* TODO: Maybe rewrite so we can traverse the bo addresses sequentially, 30 * by writing dpt/ggtt in a different order? 31 */ 32 33 for (column = 0; column < width; column++) { 34 u32 src_idx = src_stride * (height - 1) + column + bo_ofs; 35 36 for (row = 0; row < height; row++) { 37 u64 addr = xe_bo_addr(bo, src_idx * XE_PAGE_SIZE, XE_PAGE_SIZE); 38 39 iosys_map_wr(map, *dpt_ofs, u64, pte | addr); 40 *dpt_ofs += 8; 41 src_idx -= src_stride; 42 } 43 44 /* The DE ignores the PTEs for the padding tiles */ 45 *dpt_ofs += (dst_stride - height) * 8; 46 } 47 48 /* Align to next page */ 49 *dpt_ofs = ALIGN(*dpt_ofs, 4096); 50 } 51 52 static void 53 write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, 54 u32 bo_ofs, u32 width, u32 height, u32 src_stride, 55 u32 dst_stride) 56 { 57 struct xe_device *xe = xe_bo_device(bo); 58 struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt; 59 u32 column, row; 60 u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]); 61 62 for (row = 0; row < height; row++) { 63 u32 src_idx = src_stride * row + bo_ofs; 64 65 for (column = 0; column < width; column++) { 66 u64 addr = xe_bo_addr(bo, src_idx * XE_PAGE_SIZE, XE_PAGE_SIZE); 67 iosys_map_wr(map, *dpt_ofs, u64, pte | addr); 68 69 *dpt_ofs += 8; 70 src_idx++; 71 } 72 73 /* The DE ignores the PTEs for the padding tiles */ 74 *dpt_ofs += (dst_stride - width) * 8; 75 } 76 77 /* Align to next page */ 78 *dpt_ofs = ALIGN(*dpt_ofs, 4096); 79 } 80 81 static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb, 82 const struct i915_gtt_view *view, 83 struct i915_vma *vma, 84 unsigned int alignment) 85 { 86 struct xe_device *xe = to_xe_device(fb->base.dev); 87 struct xe_tile *tile0 = xe_device_get_root_tile(xe); 88 struct xe_ggtt *ggtt = tile0->mem.ggtt; 89 struct drm_gem_object *obj = intel_fb_bo(&fb->base); 90 struct xe_bo *bo = gem_to_xe_bo(obj), *dpt; 91 u32 dpt_size, size = bo->ttm.base.size; 92 93 if (view->type == I915_GTT_VIEW_NORMAL) 94 dpt_size = ALIGN(size / XE_PAGE_SIZE * 8, XE_PAGE_SIZE); 95 else if (view->type == I915_GTT_VIEW_REMAPPED) 96 dpt_size = ALIGN(intel_remapped_info_size(&fb->remapped_view.gtt.remapped) * 8, 97 XE_PAGE_SIZE); 98 else 99 /* display uses 4K tiles instead of bytes here, convert to entries.. */ 100 dpt_size = ALIGN(intel_rotation_info_size(&view->rotated) * 8, 101 XE_PAGE_SIZE); 102 103 if (IS_DGFX(xe)) 104 dpt = xe_bo_create_pin_map_at_aligned(xe, tile0, NULL, 105 dpt_size, ~0ull, 106 ttm_bo_type_kernel, 107 XE_BO_FLAG_VRAM0 | 108 XE_BO_FLAG_GGTT | 109 XE_BO_FLAG_PAGETABLE, 110 alignment); 111 else 112 dpt = xe_bo_create_pin_map_at_aligned(xe, tile0, NULL, 113 dpt_size, ~0ull, 114 ttm_bo_type_kernel, 115 XE_BO_FLAG_STOLEN | 116 XE_BO_FLAG_GGTT | 117 XE_BO_FLAG_PAGETABLE, 118 alignment); 119 if (IS_ERR(dpt)) 120 dpt = xe_bo_create_pin_map_at_aligned(xe, tile0, NULL, 121 dpt_size, ~0ull, 122 ttm_bo_type_kernel, 123 XE_BO_FLAG_SYSTEM | 124 XE_BO_FLAG_GGTT | 125 XE_BO_FLAG_PAGETABLE, 126 alignment); 127 if (IS_ERR(dpt)) 128 return PTR_ERR(dpt); 129 130 if (view->type == I915_GTT_VIEW_NORMAL) { 131 u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]); 132 u32 x; 133 134 for (x = 0; x < size / XE_PAGE_SIZE; x++) { 135 u64 addr = xe_bo_addr(bo, x * XE_PAGE_SIZE, XE_PAGE_SIZE); 136 137 iosys_map_wr(&dpt->vmap, x * 8, u64, pte | addr); 138 } 139 } else if (view->type == I915_GTT_VIEW_REMAPPED) { 140 const struct intel_remapped_info *remap_info = &view->remapped; 141 u32 i, dpt_ofs = 0; 142 143 for (i = 0; i < ARRAY_SIZE(remap_info->plane); i++) 144 write_dpt_remapped(bo, &dpt->vmap, &dpt_ofs, 145 remap_info->plane[i].offset, 146 remap_info->plane[i].width, 147 remap_info->plane[i].height, 148 remap_info->plane[i].src_stride, 149 remap_info->plane[i].dst_stride); 150 151 } else { 152 const struct intel_rotation_info *rot_info = &view->rotated; 153 u32 i, dpt_ofs = 0; 154 155 for (i = 0; i < ARRAY_SIZE(rot_info->plane); i++) 156 write_dpt_rotated(bo, &dpt->vmap, &dpt_ofs, 157 rot_info->plane[i].offset, 158 rot_info->plane[i].width, 159 rot_info->plane[i].height, 160 rot_info->plane[i].src_stride, 161 rot_info->plane[i].dst_stride); 162 } 163 164 vma->dpt = dpt; 165 vma->node = dpt->ggtt_node[tile0->id]; 166 return 0; 167 } 168 169 static void 170 write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt, u32 *ggtt_ofs, u32 bo_ofs, 171 u32 width, u32 height, u32 src_stride, u32 dst_stride) 172 { 173 struct xe_device *xe = xe_bo_device(bo); 174 u32 column, row; 175 u64 pte = ggtt->pt_ops->pte_encode_flags(bo, xe->pat.idx[XE_CACHE_NONE]); 176 177 for (column = 0; column < width; column++) { 178 u32 src_idx = src_stride * (height - 1) + column + bo_ofs; 179 180 for (row = 0; row < height; row++) { 181 u64 addr = xe_bo_addr(bo, src_idx * XE_PAGE_SIZE, XE_PAGE_SIZE); 182 183 ggtt->pt_ops->ggtt_set_pte(ggtt, *ggtt_ofs, pte | addr); 184 *ggtt_ofs += XE_PAGE_SIZE; 185 src_idx -= src_stride; 186 } 187 188 /* The DE ignores the PTEs for the padding tiles */ 189 *ggtt_ofs += (dst_stride - height) * XE_PAGE_SIZE; 190 } 191 } 192 193 static int __xe_pin_fb_vma_ggtt(const struct intel_framebuffer *fb, 194 const struct i915_gtt_view *view, 195 struct i915_vma *vma, 196 unsigned int alignment) 197 { 198 struct drm_gem_object *obj = intel_fb_bo(&fb->base); 199 struct xe_bo *bo = gem_to_xe_bo(obj); 200 struct xe_device *xe = to_xe_device(fb->base.dev); 201 struct xe_tile *tile0 = xe_device_get_root_tile(xe); 202 struct xe_ggtt *ggtt = tile0->mem.ggtt; 203 u32 align; 204 int ret; 205 206 /* TODO: Consider sharing framebuffer mapping? 207 * embed i915_vma inside intel_framebuffer 208 */ 209 xe_pm_runtime_get_noresume(xe); 210 ret = mutex_lock_interruptible(&ggtt->lock); 211 if (ret) 212 goto out; 213 214 align = XE_PAGE_SIZE; 215 if (xe_bo_is_vram(bo) && ggtt->flags & XE_GGTT_FLAGS_64K) 216 align = max_t(u32, align, SZ_64K); 217 218 if (bo->ggtt_node[tile0->id] && view->type == I915_GTT_VIEW_NORMAL) { 219 vma->node = bo->ggtt_node[tile0->id]; 220 } else if (view->type == I915_GTT_VIEW_NORMAL) { 221 vma->node = xe_ggtt_node_init(ggtt); 222 if (IS_ERR(vma->node)) { 223 ret = PTR_ERR(vma->node); 224 goto out_unlock; 225 } 226 227 ret = xe_ggtt_node_insert_locked(vma->node, bo->size, align, 0); 228 if (ret) { 229 xe_ggtt_node_fini(vma->node); 230 goto out_unlock; 231 } 232 233 xe_ggtt_map_bo(ggtt, vma->node, bo, xe->pat.idx[XE_CACHE_NONE]); 234 } else { 235 u32 i, ggtt_ofs; 236 const struct intel_rotation_info *rot_info = &view->rotated; 237 238 /* display seems to use tiles instead of bytes here, so convert it back.. */ 239 u32 size = intel_rotation_info_size(rot_info) * XE_PAGE_SIZE; 240 241 vma->node = xe_ggtt_node_init(ggtt); 242 if (IS_ERR(vma->node)) { 243 ret = PTR_ERR(vma->node); 244 goto out_unlock; 245 } 246 247 ret = xe_ggtt_node_insert_locked(vma->node, size, align, 0); 248 if (ret) { 249 xe_ggtt_node_fini(vma->node); 250 goto out_unlock; 251 } 252 253 ggtt_ofs = vma->node->base.start; 254 255 for (i = 0; i < ARRAY_SIZE(rot_info->plane); i++) 256 write_ggtt_rotated(bo, ggtt, &ggtt_ofs, 257 rot_info->plane[i].offset, 258 rot_info->plane[i].width, 259 rot_info->plane[i].height, 260 rot_info->plane[i].src_stride, 261 rot_info->plane[i].dst_stride); 262 } 263 264 out_unlock: 265 mutex_unlock(&ggtt->lock); 266 out: 267 xe_pm_runtime_put(xe); 268 return ret; 269 } 270 271 static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb, 272 const struct i915_gtt_view *view, 273 unsigned int alignment) 274 { 275 struct drm_device *dev = fb->base.dev; 276 struct xe_device *xe = to_xe_device(dev); 277 struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); 278 struct drm_gem_object *obj = intel_fb_bo(&fb->base); 279 struct xe_bo *bo = gem_to_xe_bo(obj); 280 int ret; 281 282 if (!vma) 283 return ERR_PTR(-ENODEV); 284 285 refcount_set(&vma->ref, 1); 286 if (IS_DGFX(to_xe_device(bo->ttm.base.dev)) && 287 intel_fb_rc_ccs_cc_plane(&fb->base) >= 0 && 288 !(bo->flags & XE_BO_FLAG_NEEDS_CPU_ACCESS)) { 289 struct xe_tile *tile = xe_device_get_root_tile(xe); 290 291 /* 292 * If we need to able to access the clear-color value stored in 293 * the buffer, then we require that such buffers are also CPU 294 * accessible. This is important on small-bar systems where 295 * only some subset of VRAM is CPU accessible. 296 */ 297 if (tile->mem.vram.io_size < tile->mem.vram.usable_size) { 298 ret = -EINVAL; 299 goto err; 300 } 301 } 302 303 /* 304 * Pin the framebuffer, we can't use xe_bo_(un)pin functions as the 305 * assumptions are incorrect for framebuffers 306 */ 307 ret = ttm_bo_reserve(&bo->ttm, false, false, NULL); 308 if (ret) 309 goto err; 310 311 if (IS_DGFX(xe)) 312 ret = xe_bo_migrate(bo, XE_PL_VRAM0); 313 else 314 ret = xe_bo_validate(bo, NULL, true); 315 if (!ret) 316 ttm_bo_pin(&bo->ttm); 317 ttm_bo_unreserve(&bo->ttm); 318 if (ret) 319 goto err; 320 321 vma->bo = bo; 322 if (intel_fb_uses_dpt(&fb->base)) 323 ret = __xe_pin_fb_vma_dpt(fb, view, vma, alignment); 324 else 325 ret = __xe_pin_fb_vma_ggtt(fb, view, vma, alignment); 326 if (ret) 327 goto err_unpin; 328 329 /* Ensure DPT writes are flushed */ 330 xe_device_l2_flush(xe); 331 return vma; 332 333 err_unpin: 334 ttm_bo_reserve(&bo->ttm, false, false, NULL); 335 ttm_bo_unpin(&bo->ttm); 336 ttm_bo_unreserve(&bo->ttm); 337 err: 338 kfree(vma); 339 return ERR_PTR(ret); 340 } 341 342 static void __xe_unpin_fb_vma(struct i915_vma *vma) 343 { 344 u8 tile_id = xe_device_get_root_tile(xe_bo_device(vma->bo))->id; 345 346 if (!refcount_dec_and_test(&vma->ref)) 347 return; 348 349 if (vma->dpt) 350 xe_bo_unpin_map_no_vm(vma->dpt); 351 else if (!xe_ggtt_node_allocated(vma->bo->ggtt_node[tile_id]) || 352 vma->bo->ggtt_node[tile_id]->base.start != vma->node->base.start) 353 xe_ggtt_node_remove(vma->node, false); 354 355 ttm_bo_reserve(&vma->bo->ttm, false, false, NULL); 356 ttm_bo_unpin(&vma->bo->ttm); 357 ttm_bo_unreserve(&vma->bo->ttm); 358 kfree(vma); 359 } 360 361 struct i915_vma * 362 intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, 363 const struct i915_gtt_view *view, 364 unsigned int alignment, 365 unsigned int phys_alignment, 366 unsigned int vtd_guard, 367 bool uses_fence, 368 unsigned long *out_flags) 369 { 370 *out_flags = 0; 371 372 return __xe_pin_fb_vma(to_intel_framebuffer(fb), view, phys_alignment); 373 } 374 375 void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) 376 { 377 __xe_unpin_fb_vma(vma); 378 } 379 380 static bool reuse_vma(struct intel_plane_state *new_plane_state, 381 const struct intel_plane_state *old_plane_state) 382 { 383 struct intel_framebuffer *fb = to_intel_framebuffer(new_plane_state->hw.fb); 384 struct xe_device *xe = to_xe_device(fb->base.dev); 385 struct intel_display *display = xe->display; 386 struct i915_vma *vma; 387 388 if (old_plane_state->hw.fb == new_plane_state->hw.fb && 389 !memcmp(&old_plane_state->view.gtt, 390 &new_plane_state->view.gtt, 391 sizeof(new_plane_state->view.gtt))) { 392 vma = old_plane_state->ggtt_vma; 393 goto found; 394 } 395 396 if (fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { 397 vma = intel_fbdev_vma_pointer(display->fbdev.fbdev); 398 if (vma) 399 goto found; 400 } 401 402 return false; 403 404 found: 405 refcount_inc(&vma->ref); 406 new_plane_state->ggtt_vma = vma; 407 return true; 408 } 409 410 int intel_plane_pin_fb(struct intel_plane_state *new_plane_state, 411 const struct intel_plane_state *old_plane_state) 412 { 413 struct drm_framebuffer *fb = new_plane_state->hw.fb; 414 struct drm_gem_object *obj = intel_fb_bo(fb); 415 struct xe_bo *bo = gem_to_xe_bo(obj); 416 struct i915_vma *vma; 417 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); 418 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); 419 unsigned int alignment = plane->min_alignment(plane, fb, 0); 420 421 if (reuse_vma(new_plane_state, old_plane_state)) 422 return 0; 423 424 /* We reject creating !SCANOUT fb's, so this is weird.. */ 425 drm_WARN_ON(bo->ttm.base.dev, !(bo->flags & XE_BO_FLAG_SCANOUT)); 426 427 vma = __xe_pin_fb_vma(intel_fb, &new_plane_state->view.gtt, alignment); 428 429 if (IS_ERR(vma)) 430 return PTR_ERR(vma); 431 432 new_plane_state->ggtt_vma = vma; 433 return 0; 434 } 435 436 void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) 437 { 438 __xe_unpin_fb_vma(old_plane_state->ggtt_vma); 439 old_plane_state->ggtt_vma = NULL; 440 } 441 442 /* 443 * For Xe introduce dummy intel_dpt_create which just return NULL, 444 * intel_dpt_destroy which does nothing, and fake intel_dpt_ofsset returning 0; 445 */ 446 struct i915_address_space *intel_dpt_create(struct intel_framebuffer *fb) 447 { 448 return NULL; 449 } 450 451 void intel_dpt_destroy(struct i915_address_space *vm) 452 { 453 return; 454 } 455 456 u64 intel_dpt_offset(struct i915_vma *dpt_vma) 457 { 458 return 0; 459 } 460 461 void intel_fb_get_map(struct i915_vma *vma, struct iosys_map *map) 462 { 463 *map = vma->bo->vmap; 464 } 465