1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 #ifndef _XE_I915_DRV_H_ 6 #define _XE_I915_DRV_H_ 7 8 /* 9 * "Adaptation header" to allow i915 display to also build for xe driver. 10 * TODO: refactor i915 and xe so this can cease to exist 11 */ 12 13 #include <drm/drm_drv.h> 14 15 #include "gem/i915_gem_object.h" 16 17 #include "soc/intel_pch.h" 18 #include "xe_device.h" 19 #include "xe_bo.h" 20 #include "xe_pm.h" 21 #include "xe_step.h" 22 #include "i915_gem.h" 23 #include "i915_gem_stolen.h" 24 #include "i915_gpu_error.h" 25 #include "i915_reg_defs.h" 26 #include "i915_utils.h" 27 #include "intel_gt_types.h" 28 #include "intel_step.h" 29 #include "intel_uc_fw.h" 30 #include "intel_uncore.h" 31 #include "intel_runtime_pm.h" 32 #include <linux/pm_runtime.h> 33 34 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 35 { 36 return container_of(dev, struct drm_i915_private, drm); 37 } 38 39 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 40 { 41 return dev_get_drvdata(kdev); 42 } 43 44 45 #define INTEL_JASPERLAKE 0 46 #define INTEL_ELKHARTLAKE 0 47 #define IS_PLATFORM(xe, x) ((xe)->info.platform == x) 48 #define INTEL_INFO(dev_priv) (&((dev_priv)->info)) 49 #define INTEL_DEVID(dev_priv) ((dev_priv)->info.devid) 50 #define IS_I830(dev_priv) (dev_priv && 0) 51 #define IS_I845G(dev_priv) (dev_priv && 0) 52 #define IS_I85X(dev_priv) (dev_priv && 0) 53 #define IS_I865G(dev_priv) (dev_priv && 0) 54 #define IS_I915G(dev_priv) (dev_priv && 0) 55 #define IS_I915GM(dev_priv) (dev_priv && 0) 56 #define IS_I945G(dev_priv) (dev_priv && 0) 57 #define IS_I945GM(dev_priv) (dev_priv && 0) 58 #define IS_I965G(dev_priv) (dev_priv && 0) 59 #define IS_I965GM(dev_priv) (dev_priv && 0) 60 #define IS_G45(dev_priv) (dev_priv && 0) 61 #define IS_GM45(dev_priv) (dev_priv && 0) 62 #define IS_G4X(dev_priv) (dev_priv && 0) 63 #define IS_PINEVIEW(dev_priv) (dev_priv && 0) 64 #define IS_G33(dev_priv) (dev_priv && 0) 65 #define IS_IRONLAKE(dev_priv) (dev_priv && 0) 66 #define IS_IRONLAKE_M(dev_priv) (dev_priv && 0) 67 #define IS_SANDYBRIDGE(dev_priv) (dev_priv && 0) 68 #define IS_IVYBRIDGE(dev_priv) (dev_priv && 0) 69 #define IS_IVB_GT1(dev_priv) (dev_priv && 0) 70 #define IS_VALLEYVIEW(dev_priv) (dev_priv && 0) 71 #define IS_CHERRYVIEW(dev_priv) (dev_priv && 0) 72 #define IS_HASWELL(dev_priv) (dev_priv && 0) 73 #define IS_BROADWELL(dev_priv) (dev_priv && 0) 74 #define IS_SKYLAKE(dev_priv) (dev_priv && 0) 75 #define IS_BROXTON(dev_priv) (dev_priv && 0) 76 #define IS_KABYLAKE(dev_priv) (dev_priv && 0) 77 #define IS_GEMINILAKE(dev_priv) (dev_priv && 0) 78 #define IS_COFFEELAKE(dev_priv) (dev_priv && 0) 79 #define IS_COMETLAKE(dev_priv) (dev_priv && 0) 80 #define IS_ICELAKE(dev_priv) (dev_priv && 0) 81 #define IS_JASPERLAKE(dev_priv) (dev_priv && 0) 82 #define IS_ELKHARTLAKE(dev_priv) (dev_priv && 0) 83 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_TIGERLAKE) 84 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_ROCKETLAKE) 85 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1) 86 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S) 87 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P) 88 #define IS_XEHPSDV(dev_priv) (dev_priv && 0) 89 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) 90 #define IS_PONTEVECCHIO(dev_priv) IS_PLATFORM(dev_priv, XE_PVC) 91 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE) 92 #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE) 93 94 #define IS_HASWELL_ULT(dev_priv) (dev_priv && 0) 95 #define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0) 96 #define IS_BROADWELL_ULX(dev_priv) (dev_priv && 0) 97 98 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) 99 100 #define INTEL_DISPLAY_ENABLED(xe) (HAS_DISPLAY((xe)) && !intel_opregion_headless_sku((xe))) 101 102 #define IS_GRAPHICS_VER(xe, first, last) \ 103 ((xe)->info.graphics_verx100 >= first * 100 && \ 104 (xe)->info.graphics_verx100 <= (last*100 + 99)) 105 #define IS_MOBILE(xe) (xe && 0) 106 #define HAS_LLC(xe) (!IS_DGFX((xe))) 107 108 #define HAS_GMD_ID(xe) GRAPHICS_VERx100(xe) >= 1270 109 110 /* Workarounds not handled yet */ 111 #define IS_DISPLAY_STEP(xe, first, last) ({u8 __step = (xe)->info.step.display; first <= __step && __step <= last; }) 112 #define IS_GRAPHICS_STEP(xe, first, last) ({u8 __step = (xe)->info.step.graphics; first <= __step && __step <= last; }) 113 114 #define IS_LP(xe) (0) 115 #define IS_GEN9_LP(xe) (0) 116 #define IS_GEN9_BC(xe) (0) 117 118 #define IS_TIGERLAKE_UY(xe) (xe && 0) 119 #define IS_COMETLAKE_ULX(xe) (xe && 0) 120 #define IS_COFFEELAKE_ULX(xe) (xe && 0) 121 #define IS_KABYLAKE_ULX(xe) (xe && 0) 122 #define IS_SKYLAKE_ULX(xe) (xe && 0) 123 #define IS_HASWELL_ULX(xe) (xe && 0) 124 #define IS_COMETLAKE_ULT(xe) (xe && 0) 125 #define IS_COFFEELAKE_ULT(xe) (xe && 0) 126 #define IS_KABYLAKE_ULT(xe) (xe && 0) 127 #define IS_SKYLAKE_ULT(xe) (xe && 0) 128 129 #define IS_DG1_GRAPHICS_STEP(xe, first, last) (IS_DG1(xe) && IS_GRAPHICS_STEP(xe, first, last)) 130 #define IS_DG2_GRAPHICS_STEP(xe, variant, first, last) \ 131 ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_ ## variant && \ 132 IS_GRAPHICS_STEP(xe, first, last)) 133 #define IS_XEHPSDV_GRAPHICS_STEP(xe, first, last) (IS_XEHPSDV(xe) && IS_GRAPHICS_STEP(xe, first, last)) 134 135 /* XXX: No basedie stepping support yet */ 136 #define IS_PVC_BD_STEP(xe, first, last) (!WARN_ON(1) && IS_PONTEVECCHIO(xe)) 137 138 #define IS_TIGERLAKE_DISPLAY_STEP(xe, first, last) (IS_TIGERLAKE(xe) && IS_DISPLAY_STEP(xe, first, last)) 139 #define IS_ROCKETLAKE_DISPLAY_STEP(xe, first, last) (IS_ROCKETLAKE(xe) && IS_DISPLAY_STEP(xe, first, last)) 140 #define IS_DG1_DISPLAY_STEP(xe, first, last) (IS_DG1(xe) && IS_DISPLAY_STEP(xe, first, last)) 141 #define IS_DG2_DISPLAY_STEP(xe, first, last) (IS_DG2(xe) && IS_DISPLAY_STEP(xe, first, last)) 142 #define IS_ADLP_DISPLAY_STEP(xe, first, last) (IS_ALDERLAKE_P(xe) && IS_DISPLAY_STEP(xe, first, last)) 143 #define IS_ADLS_DISPLAY_STEP(xe, first, last) (IS_ALDERLAKE_S(xe) && IS_DISPLAY_STEP(xe, first, last)) 144 #define IS_JSL_EHL_DISPLAY_STEP(xe, first, last) (IS_JSL_EHL(xe) && IS_DISPLAY_STEP(xe, first, last)) 145 #define IS_MTL_DISPLAY_STEP(xe, first, last) (IS_METEORLAKE(xe) && IS_DISPLAY_STEP(xe, first, last)) 146 147 /* FIXME: Add subplatform here */ 148 #define IS_MTL_GRAPHICS_STEP(xe, sub, first, last) (IS_METEORLAKE(xe) && IS_DISPLAY_STEP(xe, first, last)) 149 150 #define IS_DG2_G10(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G10) 151 #define IS_DG2_G11(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G11) 152 #define IS_DG2_G12(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G12) 153 #define IS_RAPTORLAKE_U(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU) 154 #define IS_ICL_WITH_PORT_F(xe) (xe && 0) 155 #define HAS_FLAT_CCS(xe) (xe_device_has_flat_ccs(xe)) 156 #define to_intel_bo(x) gem_to_xe_bo((x)) 157 #define mkwrite_device_info(xe) (INTEL_INFO(xe)) 158 159 #define HAS_128_BYTE_Y_TILING(xe) (xe || 1) 160 161 #define intel_has_gpu_reset(a) (a && 0) 162 163 #include "intel_wakeref.h" 164 165 static inline intel_wakeref_t intel_runtime_pm_get(struct xe_runtime_pm *pm) 166 { 167 struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); 168 169 if (xe_pm_runtime_get(xe) < 0) { 170 xe_pm_runtime_put(xe); 171 return 0; 172 } 173 return 1; 174 } 175 176 static inline intel_wakeref_t intel_runtime_pm_get_if_in_use(struct xe_runtime_pm *pm) 177 { 178 struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); 179 180 return xe_pm_runtime_get_if_active(xe); 181 } 182 183 static inline void intel_runtime_pm_put_unchecked(struct xe_runtime_pm *pm) 184 { 185 struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); 186 187 xe_pm_runtime_put(xe); 188 } 189 190 static inline void intel_runtime_pm_put(struct xe_runtime_pm *pm, intel_wakeref_t wakeref) 191 { 192 if (wakeref) 193 intel_runtime_pm_put_unchecked(pm); 194 } 195 196 #define intel_runtime_pm_get_raw intel_runtime_pm_get 197 #define intel_runtime_pm_put_raw intel_runtime_pm_put 198 #define assert_rpm_wakelock_held(x) do { } while (0) 199 #define assert_rpm_raw_wakeref_held(x) do { } while (0) 200 201 #define intel_uncore_forcewake_get(x, y) do { } while (0) 202 #define intel_uncore_forcewake_put(x, y) do { } while (0) 203 204 #define intel_uncore_arm_unclaimed_mmio_detection(x) do { } while (0) 205 206 #define I915_PRIORITY_DISPLAY 0 207 struct i915_sched_attr { 208 int priority; 209 }; 210 #define i915_gem_fence_wait_priority(fence, attr) do { (void) attr; } while (0) 211 212 #define with_intel_runtime_pm(rpm, wf) \ 213 for ((wf) = intel_runtime_pm_get(rpm); (wf); \ 214 intel_runtime_pm_put((rpm), (wf)), (wf) = 0) 215 216 #define pdev_to_i915 pdev_to_xe_device 217 #define RUNTIME_INFO(xe) (&(xe)->info.i915_runtime) 218 219 #define FORCEWAKE_ALL XE_FORCEWAKE_ALL 220 #define HPD_STORM_DEFAULT_THRESHOLD 50 221 222 #ifdef CONFIG_ARM64 223 /* 224 * arm64 indirectly includes linux/rtc.h, 225 * which defines a irq_lock, so include it 226 * here before #define-ing it 227 */ 228 #include <linux/rtc.h> 229 #endif 230 231 #define irq_lock irq.lock 232 233 #endif 234