1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 #ifndef _XE_I915_DRV_H_ 6 #define _XE_I915_DRV_H_ 7 8 /* 9 * "Adaptation header" to allow i915 display to also build for xe driver. 10 * TODO: refactor i915 and xe so this can cease to exist 11 */ 12 13 #include <drm/drm_drv.h> 14 15 #include "gem/i915_gem_object.h" 16 17 #include "soc/intel_pch.h" 18 #include "xe_device.h" 19 #include "xe_bo.h" 20 #include "xe_pm.h" 21 #include "xe_step.h" 22 #include "i915_gem_stolen.h" 23 #include "i915_gpu_error.h" 24 #include "i915_reg_defs.h" 25 #include "i915_utils.h" 26 #include "intel_gt_types.h" 27 #include "intel_step.h" 28 #include "intel_uncore.h" 29 #include "intel_runtime_pm.h" 30 #include <linux/pm_runtime.h> 31 32 static inline struct drm_i915_private *to_i915(const struct drm_device *dev) 33 { 34 return container_of(dev, struct drm_i915_private, drm); 35 } 36 37 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) 38 { 39 return dev_get_drvdata(kdev); 40 } 41 42 #define IS_PLATFORM(xe, x) ((xe)->info.platform == x) 43 #define INTEL_INFO(dev_priv) (&((dev_priv)->info)) 44 #define IS_I830(dev_priv) (dev_priv && 0) 45 #define IS_I845G(dev_priv) (dev_priv && 0) 46 #define IS_I85X(dev_priv) (dev_priv && 0) 47 #define IS_I865G(dev_priv) (dev_priv && 0) 48 #define IS_I915G(dev_priv) (dev_priv && 0) 49 #define IS_I915GM(dev_priv) (dev_priv && 0) 50 #define IS_I945G(dev_priv) (dev_priv && 0) 51 #define IS_I945GM(dev_priv) (dev_priv && 0) 52 #define IS_I965G(dev_priv) (dev_priv && 0) 53 #define IS_I965GM(dev_priv) (dev_priv && 0) 54 #define IS_G45(dev_priv) (dev_priv && 0) 55 #define IS_GM45(dev_priv) (dev_priv && 0) 56 #define IS_G4X(dev_priv) (dev_priv && 0) 57 #define IS_PINEVIEW(dev_priv) (dev_priv && 0) 58 #define IS_G33(dev_priv) (dev_priv && 0) 59 #define IS_IRONLAKE(dev_priv) (dev_priv && 0) 60 #define IS_IRONLAKE_M(dev_priv) (dev_priv && 0) 61 #define IS_SANDYBRIDGE(dev_priv) (dev_priv && 0) 62 #define IS_IVYBRIDGE(dev_priv) (dev_priv && 0) 63 #define IS_IVB_GT1(dev_priv) (dev_priv && 0) 64 #define IS_VALLEYVIEW(dev_priv) (dev_priv && 0) 65 #define IS_CHERRYVIEW(dev_priv) (dev_priv && 0) 66 #define IS_HASWELL(dev_priv) (dev_priv && 0) 67 #define IS_BROADWELL(dev_priv) (dev_priv && 0) 68 #define IS_SKYLAKE(dev_priv) (dev_priv && 0) 69 #define IS_BROXTON(dev_priv) (dev_priv && 0) 70 #define IS_KABYLAKE(dev_priv) (dev_priv && 0) 71 #define IS_GEMINILAKE(dev_priv) (dev_priv && 0) 72 #define IS_COFFEELAKE(dev_priv) (dev_priv && 0) 73 #define IS_COMETLAKE(dev_priv) (dev_priv && 0) 74 #define IS_ICELAKE(dev_priv) (dev_priv && 0) 75 #define IS_JASPERLAKE(dev_priv) (dev_priv && 0) 76 #define IS_ELKHARTLAKE(dev_priv) (dev_priv && 0) 77 #define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_TIGERLAKE) 78 #define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_ROCKETLAKE) 79 #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, XE_DG1) 80 #define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_S) 81 #define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, XE_ALDERLAKE_P) 82 #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, XE_DG2) 83 #define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE) 84 #define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE) 85 #define IS_BATTLEMAGE(dev_priv) IS_PLATFORM(dev_priv, XE_BATTLEMAGE) 86 87 #define IS_HASWELL_ULT(dev_priv) (dev_priv && 0) 88 #define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0) 89 #define IS_BROADWELL_ULX(dev_priv) (dev_priv && 0) 90 91 #define IP_VER(ver, rel) ((ver) << 8 | (rel)) 92 93 #define IS_MOBILE(xe) (xe && 0) 94 95 #define HAS_GMD_ID(xe) GRAPHICS_VERx100(xe) >= 1270 96 97 /* Workarounds not handled yet */ 98 #define IS_DISPLAY_STEP(xe, first, last) ({u8 __step = (xe)->info.step.display; first <= __step && __step <= last; }) 99 100 #define IS_LP(xe) (0) 101 #define IS_GEN9_LP(xe) (0) 102 #define IS_GEN9_BC(xe) (0) 103 104 #define IS_TIGERLAKE_UY(xe) (xe && 0) 105 #define IS_COMETLAKE_ULX(xe) (xe && 0) 106 #define IS_COFFEELAKE_ULX(xe) (xe && 0) 107 #define IS_KABYLAKE_ULX(xe) (xe && 0) 108 #define IS_SKYLAKE_ULX(xe) (xe && 0) 109 #define IS_HASWELL_ULX(xe) (xe && 0) 110 #define IS_COMETLAKE_ULT(xe) (xe && 0) 111 #define IS_COFFEELAKE_ULT(xe) (xe && 0) 112 #define IS_KABYLAKE_ULT(xe) (xe && 0) 113 #define IS_SKYLAKE_ULT(xe) (xe && 0) 114 115 #define IS_DG2_G10(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G10) 116 #define IS_DG2_G11(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G11) 117 #define IS_DG2_G12(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_DG2_G12) 118 #define IS_RAPTORLAKE_U(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU) 119 #define IS_ICL_WITH_PORT_F(xe) (xe && 0) 120 #define HAS_FLAT_CCS(xe) (xe_device_has_flat_ccs(xe)) 121 #define to_intel_bo(x) gem_to_xe_bo((x)) 122 123 #define HAS_128_BYTE_Y_TILING(xe) (xe || 1) 124 125 #include "intel_wakeref.h" 126 127 static inline intel_wakeref_t intel_runtime_pm_get(struct xe_runtime_pm *pm) 128 { 129 struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); 130 131 return xe_pm_runtime_resume_and_get(xe); 132 } 133 134 static inline intel_wakeref_t intel_runtime_pm_get_if_in_use(struct xe_runtime_pm *pm) 135 { 136 struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); 137 138 return xe_pm_runtime_get_if_in_use(xe); 139 } 140 141 static inline intel_wakeref_t intel_runtime_pm_get_noresume(struct xe_runtime_pm *pm) 142 { 143 struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); 144 145 xe_pm_runtime_get_noresume(xe); 146 return true; 147 } 148 149 static inline void intel_runtime_pm_put_unchecked(struct xe_runtime_pm *pm) 150 { 151 struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); 152 153 xe_pm_runtime_put(xe); 154 } 155 156 static inline void intel_runtime_pm_put(struct xe_runtime_pm *pm, intel_wakeref_t wakeref) 157 { 158 if (wakeref) 159 intel_runtime_pm_put_unchecked(pm); 160 } 161 162 #define intel_runtime_pm_get_raw intel_runtime_pm_get 163 #define intel_runtime_pm_put_raw intel_runtime_pm_put 164 #define assert_rpm_wakelock_held(x) do { } while (0) 165 #define assert_rpm_raw_wakeref_held(x) do { } while (0) 166 167 #define intel_uncore_forcewake_get(x, y) do { } while (0) 168 #define intel_uncore_forcewake_put(x, y) do { } while (0) 169 170 #define intel_uncore_arm_unclaimed_mmio_detection(x) do { } while (0) 171 172 #define I915_PRIORITY_DISPLAY 0 173 struct i915_sched_attr { 174 int priority; 175 }; 176 #define i915_gem_fence_wait_priority(fence, attr) do { (void) attr; } while (0) 177 178 #define with_intel_runtime_pm(rpm, wf) \ 179 for ((wf) = intel_runtime_pm_get(rpm); (wf); \ 180 intel_runtime_pm_put((rpm), (wf)), (wf) = 0) 181 182 #define pdev_to_i915 pdev_to_xe_device 183 #define RUNTIME_INFO(xe) (&(xe)->info.i915_runtime) 184 185 #define FORCEWAKE_ALL XE_FORCEWAKE_ALL 186 187 #ifdef CONFIG_ARM64 188 /* 189 * arm64 indirectly includes linux/rtc.h, 190 * which defines a irq_lock, so include it 191 * here before #define-ing it 192 */ 193 #include <linux/rtc.h> 194 #endif 195 196 #define irq_lock irq.lock 197 198 #endif 199