1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2021 Intel Corporation 4 */ 5 6 #ifndef _ABI_GUC_COMMUNICATION_MMIO_ABI_H 7 #define _ABI_GUC_COMMUNICATION_MMIO_ABI_H 8 9 /** 10 * DOC: GuC MMIO based communication 11 * 12 * The MMIO based communication between Host and GuC relies on special 13 * hardware registers which format could be defined by the software 14 * (so called scratch registers). 15 * 16 * Each MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H) 17 * messages, which maximum length depends on number of available scratch 18 * registers, is directly written into those scratch registers. 19 * 20 * For Gen9+, there are 16 software scratch registers 0xC180-0xC1B8, 21 * but no H2G command takes more than 4 parameters and the GuC firmware 22 * itself uses an 4-element array to store the H2G message. 23 * 24 * For Gen11+, there are additional 4 registers 0x190240-0x19024C, which 25 * are, regardless on lower count, preferred over legacy ones. 26 * 27 * The MMIO based communication is mainly used during driver initialization 28 * phase to setup the `CTB based communication`_ that will be used afterwards. 29 */ 30 31 #define GUC_MAX_MMIO_MSG_LEN 4 32 33 /** 34 * DOC: MMIO HXG Message 35 * 36 * Format of the MMIO messages follows definitions of `HXG Message`_. 37 * 38 * +---+-------+--------------------------------------------------------------+ 39 * | | Bits | Description | 40 * +===+=======+==============================================================+ 41 * | 0 | 31:0 | | 42 * +---+-------+ | 43 * |...| | [Embedded `HXG Message`_] | 44 * +---+-------+ | 45 * | n | 31:0 | | 46 * +---+-------+--------------------------------------------------------------+ 47 */ 48 49 #endif 50