1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2023 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29 #include "vmwgfx_drv.h" 30 31 #include "vmwgfx_bo.h" 32 #include "vmwgfx_binding.h" 33 #include "vmwgfx_devcaps.h" 34 #include "vmwgfx_mksstat.h" 35 #include "vmwgfx_vkms.h" 36 #include "ttm_object.h" 37 38 #include <drm/drm_aperture.h> 39 #include <drm/drm_drv.h> 40 #include <drm/drm_fbdev_generic.h> 41 #include <drm/drm_gem_ttm_helper.h> 42 #include <drm/drm_ioctl.h> 43 #include <drm/drm_module.h> 44 #include <drm/drm_sysfs.h> 45 #include <drm/ttm/ttm_range_manager.h> 46 #include <drm/ttm/ttm_placement.h> 47 #include <generated/utsrelease.h> 48 49 #ifdef CONFIG_X86 50 #include <asm/hypervisor.h> 51 #endif 52 #include <linux/cc_platform.h> 53 #include <linux/dma-mapping.h> 54 #include <linux/module.h> 55 #include <linux/pci.h> 56 #include <linux/version.h> 57 58 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 59 60 /* 61 * Fully encoded drm commands. Might move to vmw_drm.h 62 */ 63 64 #define DRM_IOCTL_VMW_GET_PARAM \ 65 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 66 struct drm_vmw_getparam_arg) 67 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 68 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 69 union drm_vmw_alloc_dmabuf_arg) 70 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 72 struct drm_vmw_unref_dmabuf_arg) 73 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 74 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 75 struct drm_vmw_cursor_bypass_arg) 76 77 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 79 struct drm_vmw_control_stream_arg) 80 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 81 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 82 struct drm_vmw_stream_arg) 83 #define DRM_IOCTL_VMW_UNREF_STREAM \ 84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 85 struct drm_vmw_stream_arg) 86 87 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 88 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 89 struct drm_vmw_context_arg) 90 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 92 struct drm_vmw_context_arg) 93 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 94 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 95 union drm_vmw_surface_create_arg) 96 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 97 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 98 struct drm_vmw_surface_arg) 99 #define DRM_IOCTL_VMW_REF_SURFACE \ 100 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 101 union drm_vmw_surface_reference_arg) 102 #define DRM_IOCTL_VMW_EXECBUF \ 103 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 104 struct drm_vmw_execbuf_arg) 105 #define DRM_IOCTL_VMW_GET_3D_CAP \ 106 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 107 struct drm_vmw_get_3d_cap_arg) 108 #define DRM_IOCTL_VMW_FENCE_WAIT \ 109 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 110 struct drm_vmw_fence_wait_arg) 111 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 112 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 113 struct drm_vmw_fence_signaled_arg) 114 #define DRM_IOCTL_VMW_FENCE_UNREF \ 115 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 116 struct drm_vmw_fence_arg) 117 #define DRM_IOCTL_VMW_FENCE_EVENT \ 118 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 119 struct drm_vmw_fence_event_arg) 120 #define DRM_IOCTL_VMW_PRESENT \ 121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 122 struct drm_vmw_present_arg) 123 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 124 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 125 struct drm_vmw_present_readback_arg) 126 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 127 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 128 struct drm_vmw_update_layout_arg) 129 #define DRM_IOCTL_VMW_CREATE_SHADER \ 130 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 131 struct drm_vmw_shader_create_arg) 132 #define DRM_IOCTL_VMW_UNREF_SHADER \ 133 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 134 struct drm_vmw_shader_arg) 135 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 136 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 137 union drm_vmw_gb_surface_create_arg) 138 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 139 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 140 union drm_vmw_gb_surface_reference_arg) 141 #define DRM_IOCTL_VMW_SYNCCPU \ 142 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 143 struct drm_vmw_synccpu_arg) 144 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 145 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 146 struct drm_vmw_context_arg) 147 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 148 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 149 union drm_vmw_gb_surface_create_ext_arg) 150 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 151 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 152 union drm_vmw_gb_surface_reference_ext_arg) 153 #define DRM_IOCTL_VMW_MSG \ 154 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 155 struct drm_vmw_msg_arg) 156 #define DRM_IOCTL_VMW_MKSSTAT_RESET \ 157 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) 158 #define DRM_IOCTL_VMW_MKSSTAT_ADD \ 159 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ 160 struct drm_vmw_mksstat_add_arg) 161 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ 162 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ 163 struct drm_vmw_mksstat_remove_arg) 164 165 /* 166 * Ioctl definitions. 167 */ 168 169 static const struct drm_ioctl_desc vmw_ioctls[] = { 170 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, 171 DRM_RENDER_ALLOW), 172 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, 173 DRM_RENDER_ALLOW), 174 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 175 DRM_RENDER_ALLOW), 176 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, 177 vmw_kms_cursor_bypass_ioctl, 178 DRM_MASTER), 179 180 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 181 DRM_MASTER), 182 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 183 DRM_MASTER), 184 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 185 DRM_MASTER), 186 187 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 188 DRM_RENDER_ALLOW), 189 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 190 DRM_RENDER_ALLOW), 191 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 192 DRM_RENDER_ALLOW), 193 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 194 DRM_RENDER_ALLOW), 195 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 196 DRM_RENDER_ALLOW), 197 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, 198 DRM_RENDER_ALLOW), 199 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 200 DRM_RENDER_ALLOW), 201 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, 202 vmw_fence_obj_signaled_ioctl, 203 DRM_RENDER_ALLOW), 204 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 205 DRM_RENDER_ALLOW), 206 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 207 DRM_RENDER_ALLOW), 208 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 209 DRM_RENDER_ALLOW), 210 211 /* these allow direct access to the framebuffers mark as master only */ 212 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, 213 DRM_MASTER | DRM_AUTH), 214 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, 215 vmw_present_readback_ioctl, 216 DRM_MASTER | DRM_AUTH), 217 /* 218 * The permissions of the below ioctl are overridden in 219 * vmw_generic_ioctl(). We require either 220 * DRM_MASTER or capable(CAP_SYS_ADMIN). 221 */ 222 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, 223 vmw_kms_update_layout_ioctl, 224 DRM_RENDER_ALLOW), 225 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, 226 vmw_shader_define_ioctl, 227 DRM_RENDER_ALLOW), 228 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, 229 vmw_shader_destroy_ioctl, 230 DRM_RENDER_ALLOW), 231 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, 232 vmw_gb_surface_define_ioctl, 233 DRM_RENDER_ALLOW), 234 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, 235 vmw_gb_surface_reference_ioctl, 236 DRM_RENDER_ALLOW), 237 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, 238 vmw_user_bo_synccpu_ioctl, 239 DRM_RENDER_ALLOW), 240 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, 241 vmw_extended_context_define_ioctl, 242 DRM_RENDER_ALLOW), 243 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, 244 vmw_gb_surface_define_ext_ioctl, 245 DRM_RENDER_ALLOW), 246 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, 247 vmw_gb_surface_reference_ext_ioctl, 248 DRM_RENDER_ALLOW), 249 DRM_IOCTL_DEF_DRV(VMW_MSG, 250 vmw_msg_ioctl, 251 DRM_RENDER_ALLOW), 252 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, 253 vmw_mksstat_reset_ioctl, 254 DRM_RENDER_ALLOW), 255 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, 256 vmw_mksstat_add_ioctl, 257 DRM_RENDER_ALLOW), 258 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, 259 vmw_mksstat_remove_ioctl, 260 DRM_RENDER_ALLOW), 261 }; 262 263 static const struct pci_device_id vmw_pci_id_list[] = { 264 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, 265 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, 266 { } 267 }; 268 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 269 270 static int vmw_restrict_iommu; 271 static int vmw_force_coherent; 272 static int vmw_restrict_dma_mask; 273 static int vmw_assume_16bpp; 274 275 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 276 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 277 void *ptr); 278 279 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 280 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 281 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 282 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 283 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 284 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 285 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 286 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 287 288 289 struct bitmap_name { 290 uint32 value; 291 const char *name; 292 }; 293 294 static const struct bitmap_name cap1_names[] = { 295 { SVGA_CAP_RECT_COPY, "rect copy" }, 296 { SVGA_CAP_CURSOR, "cursor" }, 297 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, 298 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, 299 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, 300 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, 301 { SVGA_CAP_3D, "3D" }, 302 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, 303 { SVGA_CAP_MULTIMON, "multimon" }, 304 { SVGA_CAP_PITCHLOCK, "pitchlock" }, 305 { SVGA_CAP_IRQMASK, "irq mask" }, 306 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, 307 { SVGA_CAP_GMR, "gmr" }, 308 { SVGA_CAP_TRACES, "traces" }, 309 { SVGA_CAP_GMR2, "gmr2" }, 310 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, 311 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, 312 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, 313 { SVGA_CAP_GBOBJECTS, "gbobject" }, 314 { SVGA_CAP_DX, "dx" }, 315 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, 316 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, 317 { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, 318 }; 319 320 321 static const struct bitmap_name cap2_names[] = { 322 { SVGA_CAP2_GROW_OTABLE, "grow otable" }, 323 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, 324 { SVGA_CAP2_DX2, "dx2" }, 325 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, 326 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, 327 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, 328 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, 329 { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, 330 { SVGA_CAP2_MSHINT, "mshint" }, 331 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, 332 { SVGA_CAP2_DX3, "dx3" }, 333 { SVGA_CAP2_FRAME_TYPE, "frame type" }, 334 { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, 335 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, 336 { SVGA_CAP2_EXTRA_REGS, "extra regs" }, 337 { SVGA_CAP2_LO_STAGING, "lo staging" }, 338 }; 339 340 static void vmw_print_bitmap(struct drm_device *drm, 341 const char *prefix, uint32_t bitmap, 342 const struct bitmap_name *bnames, 343 uint32_t num_names) 344 { 345 char buf[512]; 346 uint32_t i; 347 uint32_t offset = 0; 348 for (i = 0; i < num_names; ++i) { 349 if ((bitmap & bnames[i].value) != 0) { 350 offset += snprintf(buf + offset, 351 ARRAY_SIZE(buf) - offset, 352 "%s, ", bnames[i].name); 353 bitmap &= ~bnames[i].value; 354 } 355 } 356 357 drm_info(drm, "%s: %s\n", prefix, buf); 358 if (bitmap != 0) 359 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap); 360 } 361 362 363 static void vmw_print_sm_type(struct vmw_private *dev_priv) 364 { 365 static const char *names[] = { 366 [VMW_SM_LEGACY] = "Legacy", 367 [VMW_SM_4] = "SM4", 368 [VMW_SM_4_1] = "SM4_1", 369 [VMW_SM_5] = "SM_5", 370 [VMW_SM_5_1X] = "SM_5_1X", 371 [VMW_SM_MAX] = "Invalid" 372 }; 373 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); 374 drm_info(&dev_priv->drm, "Available shader model: %s.\n", 375 names[dev_priv->sm_type]); 376 } 377 378 /** 379 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 380 * 381 * @dev_priv: A device private structure. 382 * 383 * This function creates a small buffer object that holds the query 384 * result for dummy queries emitted as query barriers. 385 * The function will then map the first page and initialize a pending 386 * occlusion query result structure, Finally it will unmap the buffer. 387 * No interruptible waits are done within this function. 388 * 389 * Returns an error if bo creation or initialization fails. 390 */ 391 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 392 { 393 int ret; 394 struct vmw_bo *vbo; 395 struct ttm_bo_kmap_obj map; 396 volatile SVGA3dQueryResult *result; 397 bool dummy; 398 struct vmw_bo_params bo_params = { 399 .domain = VMW_BO_DOMAIN_SYS, 400 .busy_domain = VMW_BO_DOMAIN_SYS, 401 .bo_type = ttm_bo_type_kernel, 402 .size = PAGE_SIZE, 403 .pin = true 404 }; 405 406 /* 407 * Create the vbo as pinned, so that a tryreserve will 408 * immediately succeed. This is because we're the only 409 * user of the bo currently. 410 */ 411 ret = vmw_bo_create(dev_priv, &bo_params, &vbo); 412 if (unlikely(ret != 0)) 413 return ret; 414 415 ret = ttm_bo_reserve(&vbo->tbo, false, true, NULL); 416 BUG_ON(ret != 0); 417 vmw_bo_pin_reserved(vbo, true); 418 419 ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map); 420 if (likely(ret == 0)) { 421 result = ttm_kmap_obj_virtual(&map, &dummy); 422 result->totalSize = sizeof(*result); 423 result->state = SVGA3D_QUERYSTATE_PENDING; 424 result->result32 = 0xff; 425 ttm_bo_kunmap(&map); 426 } 427 vmw_bo_pin_reserved(vbo, false); 428 ttm_bo_unreserve(&vbo->tbo); 429 430 if (unlikely(ret != 0)) { 431 DRM_ERROR("Dummy query buffer map failed.\n"); 432 vmw_bo_unreference(&vbo); 433 } else 434 dev_priv->dummy_query_bo = vbo; 435 436 return ret; 437 } 438 439 static int vmw_device_init(struct vmw_private *dev_priv) 440 { 441 bool uses_fb_traces = false; 442 443 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 444 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 445 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 446 447 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | 448 SVGA_REG_ENABLE_HIDE); 449 450 uses_fb_traces = !vmw_cmd_supported(dev_priv) && 451 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; 452 453 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); 454 dev_priv->fifo = vmw_fifo_create(dev_priv); 455 if (IS_ERR(dev_priv->fifo)) { 456 int err = PTR_ERR(dev_priv->fifo); 457 dev_priv->fifo = NULL; 458 return err; 459 } else if (!dev_priv->fifo) { 460 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); 461 } 462 463 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); 464 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); 465 return 0; 466 } 467 468 static void vmw_device_fini(struct vmw_private *vmw) 469 { 470 /* 471 * Legacy sync 472 */ 473 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 474 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) 475 ; 476 477 vmw->last_read_seqno = vmw_fence_read(vmw); 478 479 vmw_write(vmw, SVGA_REG_CONFIG_DONE, 480 vmw->config_done_state); 481 vmw_write(vmw, SVGA_REG_ENABLE, 482 vmw->enable_state); 483 vmw_write(vmw, SVGA_REG_TRACES, 484 vmw->traces_state); 485 486 vmw_fifo_destroy(vmw); 487 } 488 489 /** 490 * vmw_request_device_late - Perform late device setup 491 * 492 * @dev_priv: Pointer to device private. 493 * 494 * This function performs setup of otables and enables large command 495 * buffer submission. These tasks are split out to a separate function 496 * because it reverts vmw_release_device_early and is intended to be used 497 * by an error path in the hibernation code. 498 */ 499 static int vmw_request_device_late(struct vmw_private *dev_priv) 500 { 501 int ret; 502 503 if (dev_priv->has_mob) { 504 ret = vmw_otables_setup(dev_priv); 505 if (unlikely(ret != 0)) { 506 DRM_ERROR("Unable to initialize " 507 "guest Memory OBjects.\n"); 508 return ret; 509 } 510 } 511 512 if (dev_priv->cman) { 513 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096); 514 if (ret) { 515 struct vmw_cmdbuf_man *man = dev_priv->cman; 516 517 dev_priv->cman = NULL; 518 vmw_cmdbuf_man_destroy(man); 519 } 520 } 521 522 return 0; 523 } 524 525 static int vmw_request_device(struct vmw_private *dev_priv) 526 { 527 int ret; 528 529 ret = vmw_device_init(dev_priv); 530 if (unlikely(ret != 0)) { 531 DRM_ERROR("Unable to initialize the device.\n"); 532 return ret; 533 } 534 vmw_fence_fifo_up(dev_priv->fman); 535 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 536 if (IS_ERR(dev_priv->cman)) { 537 dev_priv->cman = NULL; 538 dev_priv->sm_type = VMW_SM_LEGACY; 539 } 540 541 ret = vmw_request_device_late(dev_priv); 542 if (ret) 543 goto out_no_mob; 544 545 ret = vmw_dummy_query_bo_create(dev_priv); 546 if (unlikely(ret != 0)) 547 goto out_no_query_bo; 548 549 return 0; 550 551 out_no_query_bo: 552 if (dev_priv->cman) 553 vmw_cmdbuf_remove_pool(dev_priv->cman); 554 if (dev_priv->has_mob) { 555 struct ttm_resource_manager *man; 556 557 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 558 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 559 vmw_otables_takedown(dev_priv); 560 } 561 if (dev_priv->cman) 562 vmw_cmdbuf_man_destroy(dev_priv->cman); 563 out_no_mob: 564 vmw_fence_fifo_down(dev_priv->fman); 565 vmw_device_fini(dev_priv); 566 return ret; 567 } 568 569 /** 570 * vmw_release_device_early - Early part of fifo takedown. 571 * 572 * @dev_priv: Pointer to device private struct. 573 * 574 * This is the first part of command submission takedown, to be called before 575 * buffer management is taken down. 576 */ 577 static void vmw_release_device_early(struct vmw_private *dev_priv) 578 { 579 /* 580 * Previous destructions should've released 581 * the pinned bo. 582 */ 583 584 BUG_ON(dev_priv->pinned_bo != NULL); 585 586 vmw_bo_unreference(&dev_priv->dummy_query_bo); 587 if (dev_priv->cman) 588 vmw_cmdbuf_remove_pool(dev_priv->cman); 589 590 if (dev_priv->has_mob) { 591 struct ttm_resource_manager *man; 592 593 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 594 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 595 vmw_otables_takedown(dev_priv); 596 } 597 } 598 599 /** 600 * vmw_release_device_late - Late part of fifo takedown. 601 * 602 * @dev_priv: Pointer to device private struct. 603 * 604 * This is the last part of the command submission takedown, to be called when 605 * command submission is no longer needed. It may wait on pending fences. 606 */ 607 static void vmw_release_device_late(struct vmw_private *dev_priv) 608 { 609 vmw_fence_fifo_down(dev_priv->fman); 610 if (dev_priv->cman) 611 vmw_cmdbuf_man_destroy(dev_priv->cman); 612 613 vmw_device_fini(dev_priv); 614 } 615 616 /* 617 * Sets the initial_[width|height] fields on the given vmw_private. 618 * 619 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 620 * clamping the value to fb_max_[width|height] fields and the 621 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 622 * If the values appear to be invalid, set them to 623 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 624 */ 625 static void vmw_get_initial_size(struct vmw_private *dev_priv) 626 { 627 uint32_t width; 628 uint32_t height; 629 630 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 631 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 632 633 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH); 634 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT); 635 636 if (width > dev_priv->fb_max_width || 637 height > dev_priv->fb_max_height) { 638 639 /* 640 * This is a host error and shouldn't occur. 641 */ 642 643 width = VMWGFX_MIN_INITIAL_WIDTH; 644 height = VMWGFX_MIN_INITIAL_HEIGHT; 645 } 646 647 dev_priv->initial_width = width; 648 dev_priv->initial_height = height; 649 } 650 651 /** 652 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 653 * system. 654 * 655 * @dev_priv: Pointer to a struct vmw_private 656 * 657 * This functions tries to determine what actions need to be taken by the 658 * driver to make system pages visible to the device. 659 * If this function decides that DMA is not possible, it returns -EINVAL. 660 * The driver may then try to disable features of the device that require 661 * DMA. 662 */ 663 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 664 { 665 static const char *names[vmw_dma_map_max] = { 666 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 667 [vmw_dma_map_populate] = "Caching DMA mappings.", 668 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 669 670 /* 671 * When running with SEV we always want dma mappings, because 672 * otherwise ttm tt pool pages will bounce through swiotlb running 673 * out of available space. 674 */ 675 if (vmw_force_coherent || cc_platform_has(CC_ATTR_MEM_ENCRYPT)) 676 dev_priv->map_mode = vmw_dma_alloc_coherent; 677 else if (vmw_restrict_iommu) 678 dev_priv->map_mode = vmw_dma_map_bind; 679 else 680 dev_priv->map_mode = vmw_dma_map_populate; 681 682 drm_info(&dev_priv->drm, 683 "DMA map mode: %s\n", names[dev_priv->map_mode]); 684 return 0; 685 } 686 687 /** 688 * vmw_dma_masks - set required page- and dma masks 689 * 690 * @dev_priv: Pointer to struct drm-device 691 * 692 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 693 * restriction also for 64-bit systems. 694 */ 695 static int vmw_dma_masks(struct vmw_private *dev_priv) 696 { 697 struct drm_device *dev = &dev_priv->drm; 698 int ret = 0; 699 700 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 701 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { 702 drm_info(&dev_priv->drm, 703 "Restricting DMA addresses to 44 bits.\n"); 704 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 705 } 706 707 return ret; 708 } 709 710 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 711 { 712 int ret; 713 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 714 dev_priv->vram_size >> PAGE_SHIFT); 715 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 716 return ret; 717 } 718 719 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 720 { 721 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 722 } 723 724 static int vmw_setup_pci_resources(struct vmw_private *dev, 725 u32 pci_id) 726 { 727 resource_size_t rmmio_start; 728 resource_size_t rmmio_size; 729 resource_size_t fifo_start; 730 resource_size_t fifo_size; 731 int ret; 732 struct pci_dev *pdev = to_pci_dev(dev->drm.dev); 733 734 pci_set_master(pdev); 735 736 ret = pci_request_regions(pdev, "vmwgfx probe"); 737 if (ret) 738 return ret; 739 740 dev->pci_id = pci_id; 741 if (pci_id == VMWGFX_PCI_ID_SVGA3) { 742 rmmio_start = pci_resource_start(pdev, 0); 743 rmmio_size = pci_resource_len(pdev, 0); 744 dev->vram_start = pci_resource_start(pdev, 2); 745 dev->vram_size = pci_resource_len(pdev, 2); 746 747 drm_info(&dev->drm, 748 "Register MMIO at 0x%pa size is %llu kiB\n", 749 &rmmio_start, (uint64_t)rmmio_size / 1024); 750 dev->rmmio = devm_ioremap(dev->drm.dev, 751 rmmio_start, 752 rmmio_size); 753 if (!dev->rmmio) { 754 drm_err(&dev->drm, 755 "Failed mapping registers mmio memory.\n"); 756 pci_release_regions(pdev); 757 return -ENOMEM; 758 } 759 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { 760 dev->io_start = pci_resource_start(pdev, 0); 761 dev->vram_start = pci_resource_start(pdev, 1); 762 dev->vram_size = pci_resource_len(pdev, 1); 763 fifo_start = pci_resource_start(pdev, 2); 764 fifo_size = pci_resource_len(pdev, 2); 765 766 drm_info(&dev->drm, 767 "FIFO at %pa size is %llu kiB\n", 768 &fifo_start, (uint64_t)fifo_size / 1024); 769 dev->fifo_mem = devm_memremap(dev->drm.dev, 770 fifo_start, 771 fifo_size, 772 MEMREMAP_WB); 773 774 if (IS_ERR(dev->fifo_mem)) { 775 drm_err(&dev->drm, 776 "Failed mapping FIFO memory.\n"); 777 pci_release_regions(pdev); 778 return PTR_ERR(dev->fifo_mem); 779 } 780 } else { 781 pci_release_regions(pdev); 782 return -EINVAL; 783 } 784 785 /* 786 * This is approximate size of the vram, the exact size will only 787 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource 788 * size will be equal to or bigger than the size reported by 789 * SVGA_REG_VRAM_SIZE. 790 */ 791 drm_info(&dev->drm, 792 "VRAM at %pa size is %llu kiB\n", 793 &dev->vram_start, (uint64_t)dev->vram_size / 1024); 794 795 return 0; 796 } 797 798 static int vmw_detect_version(struct vmw_private *dev) 799 { 800 uint32_t svga_id; 801 802 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? 803 SVGA_ID_3 : SVGA_ID_2); 804 svga_id = vmw_read(dev, SVGA_REG_ID); 805 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { 806 drm_err(&dev->drm, 807 "Unsupported SVGA ID 0x%x on chipset 0x%x\n", 808 svga_id, dev->pci_id); 809 return -ENOSYS; 810 } 811 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); 812 drm_info(&dev->drm, 813 "Running on SVGA version %d.\n", (svga_id & 0xff)); 814 return 0; 815 } 816 817 static void vmw_write_driver_id(struct vmw_private *dev) 818 { 819 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) { 820 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 821 SVGA_REG_GUEST_DRIVER_ID_LINUX); 822 823 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1, 824 LINUX_VERSION_MAJOR << 24 | 825 LINUX_VERSION_PATCHLEVEL << 16 | 826 LINUX_VERSION_SUBLEVEL); 827 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2, 828 VMWGFX_DRIVER_MAJOR << 24 | 829 VMWGFX_DRIVER_MINOR << 16 | 830 VMWGFX_DRIVER_PATCHLEVEL); 831 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0); 832 833 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 834 SVGA_REG_GUEST_DRIVER_ID_SUBMIT); 835 } 836 } 837 838 static void vmw_sw_context_init(struct vmw_private *dev_priv) 839 { 840 struct vmw_sw_context *sw_context = &dev_priv->ctx; 841 842 hash_init(sw_context->res_ht); 843 } 844 845 static void vmw_sw_context_fini(struct vmw_private *dev_priv) 846 { 847 struct vmw_sw_context *sw_context = &dev_priv->ctx; 848 849 vfree(sw_context->cmd_bounce); 850 if (sw_context->staged_bindings) 851 vmw_binding_state_free(sw_context->staged_bindings); 852 } 853 854 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 855 { 856 int ret; 857 enum vmw_res_type i; 858 bool refuse_dma = false; 859 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 860 861 dev_priv->drm.dev_private = dev_priv; 862 863 vmw_sw_context_init(dev_priv); 864 865 mutex_init(&dev_priv->cmdbuf_mutex); 866 mutex_init(&dev_priv->binding_mutex); 867 spin_lock_init(&dev_priv->resource_lock); 868 spin_lock_init(&dev_priv->hw_lock); 869 spin_lock_init(&dev_priv->waiter_lock); 870 spin_lock_init(&dev_priv->cursor_lock); 871 872 ret = vmw_setup_pci_resources(dev_priv, pci_id); 873 if (ret) 874 return ret; 875 ret = vmw_detect_version(dev_priv); 876 if (ret) 877 goto out_no_pci_or_version; 878 879 880 for (i = vmw_res_context; i < vmw_res_max; ++i) { 881 idr_init_base(&dev_priv->res_idr[i], 1); 882 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 883 } 884 885 init_waitqueue_head(&dev_priv->fence_queue); 886 init_waitqueue_head(&dev_priv->fifo_queue); 887 dev_priv->fence_queue_waiters = 0; 888 dev_priv->fifo_queue_waiters = 0; 889 890 dev_priv->used_memory_size = 0; 891 892 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 893 894 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 895 vmw_print_bitmap(&dev_priv->drm, "Capabilities", 896 dev_priv->capabilities, 897 cap1_names, ARRAY_SIZE(cap1_names)); 898 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 899 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 900 vmw_print_bitmap(&dev_priv->drm, "Capabilities2", 901 dev_priv->capabilities2, 902 cap2_names, ARRAY_SIZE(cap2_names)); 903 } 904 905 if (!vmwgfx_supported(dev_priv)) { 906 vmw_disable_backdoor(); 907 drm_err_once(&dev_priv->drm, 908 "vmwgfx seems to be running on an unsupported hypervisor."); 909 drm_err_once(&dev_priv->drm, 910 "This configuration is likely broken."); 911 drm_err_once(&dev_priv->drm, 912 "Please switch to a supported graphics device to avoid problems."); 913 } 914 915 vmw_vkms_init(dev_priv); 916 917 ret = vmw_dma_select_mode(dev_priv); 918 if (unlikely(ret != 0)) { 919 drm_info(&dev_priv->drm, 920 "Restricting capabilities since DMA not available.\n"); 921 refuse_dma = true; 922 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 923 drm_info(&dev_priv->drm, 924 "Disabling 3D acceleration.\n"); 925 } 926 927 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 928 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 929 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 930 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 931 932 vmw_get_initial_size(dev_priv); 933 934 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 935 dev_priv->max_gmr_ids = 936 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 937 dev_priv->max_gmr_pages = 938 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 939 dev_priv->memory_size = 940 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 941 dev_priv->memory_size -= dev_priv->vram_size; 942 } else { 943 /* 944 * An arbitrary limit of 512MiB on surface 945 * memory. But all HWV8 hardware supports GMR2. 946 */ 947 dev_priv->memory_size = 512*1024*1024; 948 } 949 dev_priv->max_mob_pages = 0; 950 dev_priv->max_mob_size = 0; 951 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 952 uint64_t mem_size; 953 954 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 955 mem_size = vmw_read(dev_priv, 956 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 957 else 958 mem_size = 959 vmw_read(dev_priv, 960 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 961 962 /* 963 * Workaround for low memory 2D VMs to compensate for the 964 * allocation taken by fbdev 965 */ 966 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 967 mem_size *= 3; 968 969 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 970 dev_priv->max_primary_mem = 971 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM); 972 dev_priv->max_mob_size = 973 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 974 dev_priv->stdu_max_width = 975 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 976 dev_priv->stdu_max_height = 977 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 978 979 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 980 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 981 dev_priv->texture_max_width = vmw_read(dev_priv, 982 SVGA_REG_DEV_CAP); 983 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 984 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 985 dev_priv->texture_max_height = vmw_read(dev_priv, 986 SVGA_REG_DEV_CAP); 987 } else { 988 dev_priv->texture_max_width = 8192; 989 dev_priv->texture_max_height = 8192; 990 dev_priv->max_primary_mem = dev_priv->vram_size; 991 } 992 drm_info(&dev_priv->drm, 993 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n", 994 (u64)dev_priv->vram_size / 1024, 995 (u64)dev_priv->fifo_mem_size / 1024, 996 dev_priv->memory_size / 1024); 997 998 drm_info(&dev_priv->drm, 999 "MOB limits: max mob size = %u kB, max mob pages = %u\n", 1000 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); 1001 1002 ret = vmw_dma_masks(dev_priv); 1003 if (unlikely(ret != 0)) 1004 goto out_err0; 1005 1006 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX); 1007 1008 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 1009 drm_info(&dev_priv->drm, 1010 "Max GMR ids is %u\n", 1011 (unsigned)dev_priv->max_gmr_ids); 1012 drm_info(&dev_priv->drm, 1013 "Max number of GMR pages is %u\n", 1014 (unsigned)dev_priv->max_gmr_pages); 1015 } 1016 drm_info(&dev_priv->drm, 1017 "Maximum display memory size is %llu kiB\n", 1018 (uint64_t)dev_priv->max_primary_mem / 1024); 1019 1020 /* Need mmio memory to check for fifo pitchlock cap. */ 1021 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 1022 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 1023 !vmw_fifo_have_pitchlock(dev_priv)) { 1024 ret = -ENOSYS; 1025 DRM_ERROR("Hardware has no pitchlock\n"); 1026 goto out_err0; 1027 } 1028 1029 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops); 1030 1031 if (unlikely(dev_priv->tdev == NULL)) { 1032 drm_err(&dev_priv->drm, 1033 "Unable to initialize TTM object management.\n"); 1034 ret = -ENOMEM; 1035 goto out_err0; 1036 } 1037 1038 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 1039 ret = vmw_irq_install(dev_priv); 1040 if (ret != 0) { 1041 drm_err(&dev_priv->drm, 1042 "Failed installing irq: %d\n", ret); 1043 goto out_no_irq; 1044 } 1045 } 1046 1047 dev_priv->fman = vmw_fence_manager_init(dev_priv); 1048 if (unlikely(dev_priv->fman == NULL)) { 1049 ret = -ENOMEM; 1050 goto out_no_fman; 1051 } 1052 1053 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver, 1054 dev_priv->drm.dev, 1055 dev_priv->drm.anon_inode->i_mapping, 1056 dev_priv->drm.vma_offset_manager, 1057 dev_priv->map_mode == vmw_dma_alloc_coherent, 1058 false); 1059 if (unlikely(ret != 0)) { 1060 drm_err(&dev_priv->drm, 1061 "Failed initializing TTM buffer object driver.\n"); 1062 goto out_no_bdev; 1063 } 1064 1065 /* 1066 * Enable VRAM, but initially don't use it until SVGA is enabled and 1067 * unhidden. 1068 */ 1069 1070 ret = vmw_vram_manager_init(dev_priv); 1071 if (unlikely(ret != 0)) { 1072 drm_err(&dev_priv->drm, 1073 "Failed initializing memory manager for VRAM.\n"); 1074 goto out_no_vram; 1075 } 1076 1077 ret = vmw_devcaps_create(dev_priv); 1078 if (unlikely(ret != 0)) { 1079 drm_err(&dev_priv->drm, 1080 "Failed initializing device caps.\n"); 1081 goto out_no_vram; 1082 } 1083 1084 /* 1085 * "Guest Memory Regions" is an aperture like feature with 1086 * one slot per bo. There is an upper limit of the number of 1087 * slots as well as the bo size. 1088 */ 1089 dev_priv->has_gmr = true; 1090 /* TODO: This is most likely not correct */ 1091 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 1092 refuse_dma || 1093 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 1094 drm_info(&dev_priv->drm, 1095 "No GMR memory available. " 1096 "Graphics memory resources are very limited.\n"); 1097 dev_priv->has_gmr = false; 1098 } 1099 1100 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 1101 dev_priv->has_mob = true; 1102 1103 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 1104 drm_info(&dev_priv->drm, 1105 "No MOB memory available. " 1106 "3D will be disabled.\n"); 1107 dev_priv->has_mob = false; 1108 } 1109 if (vmw_sys_man_init(dev_priv) != 0) { 1110 drm_info(&dev_priv->drm, 1111 "No MOB page table memory available. " 1112 "3D will be disabled.\n"); 1113 dev_priv->has_mob = false; 1114 } 1115 } 1116 1117 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 1118 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) 1119 dev_priv->sm_type = VMW_SM_4; 1120 } 1121 1122 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 1123 if (has_sm4_context(dev_priv) && 1124 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 1125 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41)) 1126 dev_priv->sm_type = VMW_SM_4_1; 1127 if (has_sm4_1_context(dev_priv) && 1128 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 1129 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) { 1130 dev_priv->sm_type = VMW_SM_5; 1131 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43)) 1132 dev_priv->sm_type = VMW_SM_5_1X; 1133 } 1134 } 1135 } 1136 1137 ret = vmw_kms_init(dev_priv); 1138 if (unlikely(ret != 0)) 1139 goto out_no_kms; 1140 vmw_overlay_init(dev_priv); 1141 1142 ret = vmw_request_device(dev_priv); 1143 if (ret) 1144 goto out_no_fifo; 1145 1146 vmw_print_sm_type(dev_priv); 1147 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)", 1148 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 1149 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); 1150 vmw_write_driver_id(dev_priv); 1151 1152 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 1153 register_pm_notifier(&dev_priv->pm_nb); 1154 1155 return 0; 1156 1157 out_no_fifo: 1158 vmw_overlay_close(dev_priv); 1159 vmw_kms_close(dev_priv); 1160 out_no_kms: 1161 if (dev_priv->has_mob) { 1162 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1163 vmw_sys_man_fini(dev_priv); 1164 } 1165 if (dev_priv->has_gmr) 1166 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1167 vmw_devcaps_destroy(dev_priv); 1168 vmw_vram_manager_fini(dev_priv); 1169 out_no_vram: 1170 ttm_device_fini(&dev_priv->bdev); 1171 out_no_bdev: 1172 vmw_fence_manager_takedown(dev_priv->fman); 1173 out_no_fman: 1174 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1175 vmw_irq_uninstall(&dev_priv->drm); 1176 out_no_irq: 1177 ttm_object_device_release(&dev_priv->tdev); 1178 out_err0: 1179 for (i = vmw_res_context; i < vmw_res_max; ++i) 1180 idr_destroy(&dev_priv->res_idr[i]); 1181 1182 if (dev_priv->ctx.staged_bindings) 1183 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1184 out_no_pci_or_version: 1185 pci_release_regions(pdev); 1186 return ret; 1187 } 1188 1189 static void vmw_driver_unload(struct drm_device *dev) 1190 { 1191 struct vmw_private *dev_priv = vmw_priv(dev); 1192 struct pci_dev *pdev = to_pci_dev(dev->dev); 1193 enum vmw_res_type i; 1194 1195 unregister_pm_notifier(&dev_priv->pm_nb); 1196 1197 vmw_sw_context_fini(dev_priv); 1198 vmw_fifo_resource_dec(dev_priv); 1199 1200 vmw_svga_disable(dev_priv); 1201 1202 vmw_vkms_cleanup(dev_priv); 1203 vmw_kms_close(dev_priv); 1204 vmw_overlay_close(dev_priv); 1205 1206 if (dev_priv->has_gmr) 1207 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1208 1209 vmw_release_device_early(dev_priv); 1210 if (dev_priv->has_mob) { 1211 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1212 vmw_sys_man_fini(dev_priv); 1213 } 1214 vmw_devcaps_destroy(dev_priv); 1215 vmw_vram_manager_fini(dev_priv); 1216 ttm_device_fini(&dev_priv->bdev); 1217 vmw_release_device_late(dev_priv); 1218 vmw_fence_manager_takedown(dev_priv->fman); 1219 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1220 vmw_irq_uninstall(&dev_priv->drm); 1221 1222 ttm_object_device_release(&dev_priv->tdev); 1223 1224 for (i = vmw_res_context; i < vmw_res_max; ++i) 1225 idr_destroy(&dev_priv->res_idr[i]); 1226 1227 vmw_mksstat_remove_all(dev_priv); 1228 1229 pci_release_regions(pdev); 1230 } 1231 1232 static void vmw_postclose(struct drm_device *dev, 1233 struct drm_file *file_priv) 1234 { 1235 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1236 1237 ttm_object_file_release(&vmw_fp->tfile); 1238 kfree(vmw_fp); 1239 } 1240 1241 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1242 { 1243 struct vmw_private *dev_priv = vmw_priv(dev); 1244 struct vmw_fpriv *vmw_fp; 1245 int ret = -ENOMEM; 1246 1247 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1248 if (unlikely(!vmw_fp)) 1249 return ret; 1250 1251 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev); 1252 if (unlikely(vmw_fp->tfile == NULL)) 1253 goto out_no_tfile; 1254 1255 file_priv->driver_priv = vmw_fp; 1256 1257 return 0; 1258 1259 out_no_tfile: 1260 kfree(vmw_fp); 1261 return ret; 1262 } 1263 1264 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1265 unsigned long arg, 1266 long (*ioctl_func)(struct file *, unsigned int, 1267 unsigned long)) 1268 { 1269 struct drm_file *file_priv = filp->private_data; 1270 struct drm_device *dev = file_priv->minor->dev; 1271 unsigned int nr = DRM_IOCTL_NR(cmd); 1272 unsigned int flags; 1273 1274 /* 1275 * Do extra checking on driver private ioctls. 1276 */ 1277 1278 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1279 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1280 const struct drm_ioctl_desc *ioctl = 1281 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1282 1283 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1284 return ioctl_func(filp, cmd, arg); 1285 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1286 if (!drm_is_current_master(file_priv) && 1287 !capable(CAP_SYS_ADMIN)) 1288 return -EACCES; 1289 } 1290 1291 if (unlikely(ioctl->cmd != cmd)) 1292 goto out_io_encoding; 1293 1294 flags = ioctl->flags; 1295 } else if (!drm_ioctl_flags(nr, &flags)) 1296 return -EINVAL; 1297 1298 return ioctl_func(filp, cmd, arg); 1299 1300 out_io_encoding: 1301 DRM_ERROR("Invalid command format, ioctl %d\n", 1302 nr - DRM_COMMAND_BASE); 1303 1304 return -EINVAL; 1305 } 1306 1307 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1308 unsigned long arg) 1309 { 1310 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1311 } 1312 1313 #ifdef CONFIG_COMPAT 1314 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1315 unsigned long arg) 1316 { 1317 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1318 } 1319 #endif 1320 1321 static void vmw_master_set(struct drm_device *dev, 1322 struct drm_file *file_priv, 1323 bool from_open) 1324 { 1325 /* 1326 * Inform a new master that the layout may have changed while 1327 * it was gone. 1328 */ 1329 if (!from_open) 1330 drm_sysfs_hotplug_event(dev); 1331 } 1332 1333 static void vmw_master_drop(struct drm_device *dev, 1334 struct drm_file *file_priv) 1335 { 1336 struct vmw_private *dev_priv = vmw_priv(dev); 1337 1338 vmw_kms_legacy_hotspot_clear(dev_priv); 1339 } 1340 1341 bool vmwgfx_supported(struct vmw_private *vmw) 1342 { 1343 #if defined(CONFIG_X86) 1344 return hypervisor_is_type(X86_HYPER_VMWARE); 1345 #elif defined(CONFIG_ARM64) 1346 /* 1347 * On aarch64 only svga3 is supported 1348 */ 1349 return vmw->pci_id == VMWGFX_PCI_ID_SVGA3; 1350 #else 1351 drm_warn_once(&vmw->drm, 1352 "vmwgfx is running on an unknown architecture."); 1353 return false; 1354 #endif 1355 } 1356 1357 /** 1358 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1359 * 1360 * @dev_priv: Pointer to device private struct. 1361 * Needs the reservation sem to be held in non-exclusive mode. 1362 */ 1363 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1364 { 1365 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1366 1367 if (!ttm_resource_manager_used(man)) { 1368 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE); 1369 ttm_resource_manager_set_used(man, true); 1370 } 1371 } 1372 1373 /** 1374 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1375 * 1376 * @dev_priv: Pointer to device private struct. 1377 */ 1378 void vmw_svga_enable(struct vmw_private *dev_priv) 1379 { 1380 __vmw_svga_enable(dev_priv); 1381 } 1382 1383 /** 1384 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1385 * 1386 * @dev_priv: Pointer to device private struct. 1387 * Needs the reservation sem to be held in exclusive mode. 1388 * Will not empty VRAM. VRAM must be emptied by caller. 1389 */ 1390 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1391 { 1392 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1393 1394 if (ttm_resource_manager_used(man)) { 1395 ttm_resource_manager_set_used(man, false); 1396 vmw_write(dev_priv, SVGA_REG_ENABLE, 1397 SVGA_REG_ENABLE_HIDE | 1398 SVGA_REG_ENABLE_ENABLE); 1399 } 1400 } 1401 1402 /** 1403 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1404 * running. 1405 * 1406 * @dev_priv: Pointer to device private struct. 1407 * Will empty VRAM. 1408 */ 1409 void vmw_svga_disable(struct vmw_private *dev_priv) 1410 { 1411 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1412 /* 1413 * Disabling SVGA will turn off device modesetting capabilities, so 1414 * notify KMS about that so that it doesn't cache atomic state that 1415 * isn't valid anymore, for example crtcs turned on. 1416 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1417 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1418 * end up with lock order reversal. Thus, a master may actually perform 1419 * a new modeset just after we call vmw_kms_lost_device() and race with 1420 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1421 * to be inconsistent with the device, causing modesetting problems. 1422 * 1423 */ 1424 vmw_kms_lost_device(&dev_priv->drm); 1425 if (ttm_resource_manager_used(man)) { 1426 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1427 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1428 ttm_resource_manager_set_used(man, false); 1429 vmw_write(dev_priv, SVGA_REG_ENABLE, 1430 SVGA_REG_ENABLE_HIDE | 1431 SVGA_REG_ENABLE_ENABLE); 1432 } 1433 } 1434 1435 static void vmw_remove(struct pci_dev *pdev) 1436 { 1437 struct drm_device *dev = pci_get_drvdata(pdev); 1438 1439 drm_dev_unregister(dev); 1440 vmw_driver_unload(dev); 1441 } 1442 1443 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw) 1444 { 1445 struct drm_minor *minor = vmw->drm.primary; 1446 struct dentry *root = minor->debugfs_root; 1447 1448 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM), 1449 root, "system_ttm"); 1450 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM), 1451 root, "vram_ttm"); 1452 if (vmw->has_gmr) 1453 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR), 1454 root, "gmr_ttm"); 1455 if (vmw->has_mob) { 1456 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB), 1457 root, "mob_ttm"); 1458 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM), 1459 root, "system_mob_ttm"); 1460 } 1461 } 1462 1463 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1464 void *ptr) 1465 { 1466 struct vmw_private *dev_priv = 1467 container_of(nb, struct vmw_private, pm_nb); 1468 1469 switch (val) { 1470 case PM_HIBERNATION_PREPARE: 1471 /* 1472 * Take the reservation sem in write mode, which will make sure 1473 * there are no other processes holding a buffer object 1474 * reservation, meaning we should be able to evict all buffer 1475 * objects if needed. 1476 * Once user-space processes have been frozen, we can release 1477 * the lock again. 1478 */ 1479 dev_priv->suspend_locked = true; 1480 break; 1481 case PM_POST_HIBERNATION: 1482 case PM_POST_RESTORE: 1483 if (READ_ONCE(dev_priv->suspend_locked)) { 1484 dev_priv->suspend_locked = false; 1485 } 1486 break; 1487 default: 1488 break; 1489 } 1490 return 0; 1491 } 1492 1493 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1494 { 1495 struct drm_device *dev = pci_get_drvdata(pdev); 1496 struct vmw_private *dev_priv = vmw_priv(dev); 1497 1498 if (dev_priv->refuse_hibernation) 1499 return -EBUSY; 1500 1501 pci_save_state(pdev); 1502 pci_disable_device(pdev); 1503 pci_set_power_state(pdev, PCI_D3hot); 1504 return 0; 1505 } 1506 1507 static int vmw_pci_resume(struct pci_dev *pdev) 1508 { 1509 pci_set_power_state(pdev, PCI_D0); 1510 pci_restore_state(pdev); 1511 return pci_enable_device(pdev); 1512 } 1513 1514 static int vmw_pm_suspend(struct device *kdev) 1515 { 1516 struct pci_dev *pdev = to_pci_dev(kdev); 1517 struct pm_message dummy; 1518 1519 dummy.event = 0; 1520 1521 return vmw_pci_suspend(pdev, dummy); 1522 } 1523 1524 static int vmw_pm_resume(struct device *kdev) 1525 { 1526 struct pci_dev *pdev = to_pci_dev(kdev); 1527 1528 return vmw_pci_resume(pdev); 1529 } 1530 1531 static int vmw_pm_freeze(struct device *kdev) 1532 { 1533 struct pci_dev *pdev = to_pci_dev(kdev); 1534 struct drm_device *dev = pci_get_drvdata(pdev); 1535 struct vmw_private *dev_priv = vmw_priv(dev); 1536 struct ttm_operation_ctx ctx = { 1537 .interruptible = false, 1538 .no_wait_gpu = false 1539 }; 1540 int ret; 1541 1542 /* 1543 * No user-space processes should be running now. 1544 */ 1545 ret = vmw_kms_suspend(&dev_priv->drm); 1546 if (ret) { 1547 DRM_ERROR("Failed to freeze modesetting.\n"); 1548 return ret; 1549 } 1550 1551 vmw_execbuf_release_pinned_bo(dev_priv); 1552 vmw_resource_evict_all(dev_priv); 1553 vmw_release_device_early(dev_priv); 1554 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0); 1555 vmw_fifo_resource_dec(dev_priv); 1556 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1557 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1558 vmw_fifo_resource_inc(dev_priv); 1559 WARN_ON(vmw_request_device_late(dev_priv)); 1560 dev_priv->suspend_locked = false; 1561 if (dev_priv->suspend_state) 1562 vmw_kms_resume(dev); 1563 return -EBUSY; 1564 } 1565 1566 vmw_fence_fifo_down(dev_priv->fman); 1567 __vmw_svga_disable(dev_priv); 1568 1569 vmw_release_device_late(dev_priv); 1570 return 0; 1571 } 1572 1573 static int vmw_pm_restore(struct device *kdev) 1574 { 1575 struct pci_dev *pdev = to_pci_dev(kdev); 1576 struct drm_device *dev = pci_get_drvdata(pdev); 1577 struct vmw_private *dev_priv = vmw_priv(dev); 1578 int ret; 1579 1580 vmw_detect_version(dev_priv); 1581 1582 vmw_fifo_resource_inc(dev_priv); 1583 1584 ret = vmw_request_device(dev_priv); 1585 if (ret) 1586 return ret; 1587 1588 __vmw_svga_enable(dev_priv); 1589 1590 vmw_fence_fifo_up(dev_priv->fman); 1591 dev_priv->suspend_locked = false; 1592 if (dev_priv->suspend_state) 1593 vmw_kms_resume(&dev_priv->drm); 1594 1595 return 0; 1596 } 1597 1598 static const struct dev_pm_ops vmw_pm_ops = { 1599 .freeze = vmw_pm_freeze, 1600 .thaw = vmw_pm_restore, 1601 .restore = vmw_pm_restore, 1602 .suspend = vmw_pm_suspend, 1603 .resume = vmw_pm_resume, 1604 }; 1605 1606 static const struct file_operations vmwgfx_driver_fops = { 1607 .owner = THIS_MODULE, 1608 .open = drm_open, 1609 .release = drm_release, 1610 .unlocked_ioctl = vmw_unlocked_ioctl, 1611 .mmap = drm_gem_mmap, 1612 .poll = drm_poll, 1613 .read = drm_read, 1614 #if defined(CONFIG_COMPAT) 1615 .compat_ioctl = vmw_compat_ioctl, 1616 #endif 1617 .llseek = noop_llseek, 1618 }; 1619 1620 static const struct drm_driver driver = { 1621 .driver_features = 1622 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM | DRIVER_CURSOR_HOTSPOT, 1623 .ioctls = vmw_ioctls, 1624 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1625 .master_set = vmw_master_set, 1626 .master_drop = vmw_master_drop, 1627 .open = vmw_driver_open, 1628 .postclose = vmw_postclose, 1629 1630 .dumb_create = vmw_dumb_create, 1631 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1632 1633 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1634 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1635 .gem_prime_import_sg_table = vmw_prime_import_sg_table, 1636 1637 .fops = &vmwgfx_driver_fops, 1638 .name = VMWGFX_DRIVER_NAME, 1639 .desc = VMWGFX_DRIVER_DESC, 1640 .date = VMWGFX_DRIVER_DATE, 1641 .major = VMWGFX_DRIVER_MAJOR, 1642 .minor = VMWGFX_DRIVER_MINOR, 1643 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1644 }; 1645 1646 static struct pci_driver vmw_pci_driver = { 1647 .name = VMWGFX_DRIVER_NAME, 1648 .id_table = vmw_pci_id_list, 1649 .probe = vmw_probe, 1650 .remove = vmw_remove, 1651 .driver = { 1652 .pm = &vmw_pm_ops 1653 } 1654 }; 1655 1656 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1657 { 1658 struct vmw_private *vmw; 1659 int ret; 1660 1661 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver); 1662 if (ret) 1663 goto out_error; 1664 1665 ret = pcim_enable_device(pdev); 1666 if (ret) 1667 goto out_error; 1668 1669 vmw = devm_drm_dev_alloc(&pdev->dev, &driver, 1670 struct vmw_private, drm); 1671 if (IS_ERR(vmw)) { 1672 ret = PTR_ERR(vmw); 1673 goto out_error; 1674 } 1675 1676 pci_set_drvdata(pdev, &vmw->drm); 1677 1678 ret = vmw_driver_load(vmw, ent->device); 1679 if (ret) 1680 goto out_error; 1681 1682 ret = drm_dev_register(&vmw->drm, 0); 1683 if (ret) 1684 goto out_unload; 1685 1686 vmw_fifo_resource_inc(vmw); 1687 vmw_svga_enable(vmw); 1688 drm_fbdev_generic_setup(&vmw->drm, 0); 1689 1690 vmw_debugfs_gem_init(vmw); 1691 vmw_debugfs_resource_managers_init(vmw); 1692 1693 return 0; 1694 out_unload: 1695 vmw_driver_unload(&vmw->drm); 1696 out_error: 1697 return ret; 1698 } 1699 1700 drm_module_pci_driver(vmw_pci_driver); 1701 1702 MODULE_AUTHOR("VMware Inc. and others"); 1703 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1704 MODULE_LICENSE("GPL and additional rights"); 1705 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1706 __stringify(VMWGFX_DRIVER_MINOR) "." 1707 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1708 "0"); 1709