1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 #include <linux/module.h> 28 #include <linux/console.h> 29 30 #include <drm/drmP.h> 31 #include "vmwgfx_drv.h" 32 #include "vmwgfx_binding.h" 33 #include "ttm_object.h" 34 #include <drm/ttm/ttm_placement.h> 35 #include <drm/ttm/ttm_bo_driver.h> 36 #include <drm/ttm/ttm_module.h> 37 #include <linux/dma_remapping.h> 38 39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 40 #define VMWGFX_CHIP_SVGAII 0 41 #define VMW_FB_RESERVATION 0 42 43 #define VMW_MIN_INITIAL_WIDTH 800 44 #define VMW_MIN_INITIAL_HEIGHT 600 45 46 #ifndef VMWGFX_GIT_VERSION 47 #define VMWGFX_GIT_VERSION "Unknown" 48 #endif 49 50 #define VMWGFX_REPO "In Tree" 51 52 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 53 54 55 /** 56 * Fully encoded drm commands. Might move to vmw_drm.h 57 */ 58 59 #define DRM_IOCTL_VMW_GET_PARAM \ 60 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 61 struct drm_vmw_getparam_arg) 62 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 63 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 64 union drm_vmw_alloc_dmabuf_arg) 65 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 66 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 67 struct drm_vmw_unref_dmabuf_arg) 68 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 69 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 70 struct drm_vmw_cursor_bypass_arg) 71 72 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 73 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 74 struct drm_vmw_control_stream_arg) 75 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 76 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 77 struct drm_vmw_stream_arg) 78 #define DRM_IOCTL_VMW_UNREF_STREAM \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 80 struct drm_vmw_stream_arg) 81 82 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 83 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 84 struct drm_vmw_context_arg) 85 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 86 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 87 struct drm_vmw_context_arg) 88 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 89 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 90 union drm_vmw_surface_create_arg) 91 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 93 struct drm_vmw_surface_arg) 94 #define DRM_IOCTL_VMW_REF_SURFACE \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 96 union drm_vmw_surface_reference_arg) 97 #define DRM_IOCTL_VMW_EXECBUF \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 99 struct drm_vmw_execbuf_arg) 100 #define DRM_IOCTL_VMW_GET_3D_CAP \ 101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 102 struct drm_vmw_get_3d_cap_arg) 103 #define DRM_IOCTL_VMW_FENCE_WAIT \ 104 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 105 struct drm_vmw_fence_wait_arg) 106 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 107 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 108 struct drm_vmw_fence_signaled_arg) 109 #define DRM_IOCTL_VMW_FENCE_UNREF \ 110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 111 struct drm_vmw_fence_arg) 112 #define DRM_IOCTL_VMW_FENCE_EVENT \ 113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 114 struct drm_vmw_fence_event_arg) 115 #define DRM_IOCTL_VMW_PRESENT \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 117 struct drm_vmw_present_arg) 118 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 120 struct drm_vmw_present_readback_arg) 121 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 123 struct drm_vmw_update_layout_arg) 124 #define DRM_IOCTL_VMW_CREATE_SHADER \ 125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 126 struct drm_vmw_shader_create_arg) 127 #define DRM_IOCTL_VMW_UNREF_SHADER \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 129 struct drm_vmw_shader_arg) 130 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 132 union drm_vmw_gb_surface_create_arg) 133 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 134 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 135 union drm_vmw_gb_surface_reference_arg) 136 #define DRM_IOCTL_VMW_SYNCCPU \ 137 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 138 struct drm_vmw_synccpu_arg) 139 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 141 struct drm_vmw_context_arg) 142 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 143 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 144 union drm_vmw_gb_surface_create_ext_arg) 145 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 147 union drm_vmw_gb_surface_reference_ext_arg) 148 149 /** 150 * The core DRM version of this macro doesn't account for 151 * DRM_COMMAND_BASE. 152 */ 153 154 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 155 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 156 157 /** 158 * Ioctl definitions. 159 */ 160 161 static const struct drm_ioctl_desc vmw_ioctls[] = { 162 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 163 DRM_AUTH | DRM_RENDER_ALLOW), 164 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 165 DRM_AUTH | DRM_RENDER_ALLOW), 166 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 167 DRM_RENDER_ALLOW), 168 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 169 vmw_kms_cursor_bypass_ioctl, 170 DRM_MASTER), 171 172 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 173 DRM_MASTER), 174 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 175 DRM_MASTER), 176 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 177 DRM_MASTER), 178 179 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 180 DRM_AUTH | DRM_RENDER_ALLOW), 181 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 182 DRM_RENDER_ALLOW), 183 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 184 DRM_AUTH | DRM_RENDER_ALLOW), 185 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 186 DRM_RENDER_ALLOW), 187 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 188 DRM_AUTH | DRM_RENDER_ALLOW), 189 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | 190 DRM_RENDER_ALLOW), 191 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 192 DRM_RENDER_ALLOW), 193 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 194 vmw_fence_obj_signaled_ioctl, 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 197 DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 199 DRM_AUTH | DRM_RENDER_ALLOW), 200 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 201 DRM_AUTH | DRM_RENDER_ALLOW), 202 203 /* these allow direct access to the framebuffers mark as master only */ 204 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 205 DRM_MASTER | DRM_AUTH), 206 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 207 vmw_present_readback_ioctl, 208 DRM_MASTER | DRM_AUTH), 209 /* 210 * The permissions of the below ioctl are overridden in 211 * vmw_generic_ioctl(). We require either 212 * DRM_MASTER or capable(CAP_SYS_ADMIN). 213 */ 214 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 215 vmw_kms_update_layout_ioctl, 216 DRM_RENDER_ALLOW), 217 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 218 vmw_shader_define_ioctl, 219 DRM_AUTH | DRM_RENDER_ALLOW), 220 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 221 vmw_shader_destroy_ioctl, 222 DRM_RENDER_ALLOW), 223 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 224 vmw_gb_surface_define_ioctl, 225 DRM_AUTH | DRM_RENDER_ALLOW), 226 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 227 vmw_gb_surface_reference_ioctl, 228 DRM_AUTH | DRM_RENDER_ALLOW), 229 VMW_IOCTL_DEF(VMW_SYNCCPU, 230 vmw_user_bo_synccpu_ioctl, 231 DRM_RENDER_ALLOW), 232 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 233 vmw_extended_context_define_ioctl, 234 DRM_AUTH | DRM_RENDER_ALLOW), 235 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 236 vmw_gb_surface_define_ext_ioctl, 237 DRM_AUTH | DRM_RENDER_ALLOW), 238 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 239 vmw_gb_surface_reference_ext_ioctl, 240 DRM_AUTH | DRM_RENDER_ALLOW), 241 }; 242 243 static const struct pci_device_id vmw_pci_id_list[] = { 244 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 245 {0, 0, 0} 246 }; 247 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 248 249 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 250 static int vmw_force_iommu; 251 static int vmw_restrict_iommu; 252 static int vmw_force_coherent; 253 static int vmw_restrict_dma_mask; 254 static int vmw_assume_16bpp; 255 256 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 257 static void vmw_master_init(struct vmw_master *); 258 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 259 void *ptr); 260 261 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 262 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 263 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 264 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 265 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 266 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 267 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 268 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 269 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 270 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 271 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 272 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 273 274 275 static void vmw_print_capabilities2(uint32_t capabilities2) 276 { 277 DRM_INFO("Capabilities2:\n"); 278 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 279 DRM_INFO(" Grow oTable.\n"); 280 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 281 DRM_INFO(" IntraSurface copy.\n"); 282 } 283 284 static void vmw_print_capabilities(uint32_t capabilities) 285 { 286 DRM_INFO("Capabilities:\n"); 287 if (capabilities & SVGA_CAP_RECT_COPY) 288 DRM_INFO(" Rect copy.\n"); 289 if (capabilities & SVGA_CAP_CURSOR) 290 DRM_INFO(" Cursor.\n"); 291 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 292 DRM_INFO(" Cursor bypass.\n"); 293 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 294 DRM_INFO(" Cursor bypass 2.\n"); 295 if (capabilities & SVGA_CAP_8BIT_EMULATION) 296 DRM_INFO(" 8bit emulation.\n"); 297 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 298 DRM_INFO(" Alpha cursor.\n"); 299 if (capabilities & SVGA_CAP_3D) 300 DRM_INFO(" 3D.\n"); 301 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 302 DRM_INFO(" Extended Fifo.\n"); 303 if (capabilities & SVGA_CAP_MULTIMON) 304 DRM_INFO(" Multimon.\n"); 305 if (capabilities & SVGA_CAP_PITCHLOCK) 306 DRM_INFO(" Pitchlock.\n"); 307 if (capabilities & SVGA_CAP_IRQMASK) 308 DRM_INFO(" Irq mask.\n"); 309 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 310 DRM_INFO(" Display Topology.\n"); 311 if (capabilities & SVGA_CAP_GMR) 312 DRM_INFO(" GMR.\n"); 313 if (capabilities & SVGA_CAP_TRACES) 314 DRM_INFO(" Traces.\n"); 315 if (capabilities & SVGA_CAP_GMR2) 316 DRM_INFO(" GMR2.\n"); 317 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 318 DRM_INFO(" Screen Object 2.\n"); 319 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 320 DRM_INFO(" Command Buffers.\n"); 321 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 322 DRM_INFO(" Command Buffers 2.\n"); 323 if (capabilities & SVGA_CAP_GBOBJECTS) 324 DRM_INFO(" Guest Backed Resources.\n"); 325 if (capabilities & SVGA_CAP_DX) 326 DRM_INFO(" DX Features.\n"); 327 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 328 DRM_INFO(" HP Command Queue.\n"); 329 } 330 331 /** 332 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 333 * 334 * @dev_priv: A device private structure. 335 * 336 * This function creates a small buffer object that holds the query 337 * result for dummy queries emitted as query barriers. 338 * The function will then map the first page and initialize a pending 339 * occlusion query result structure, Finally it will unmap the buffer. 340 * No interruptible waits are done within this function. 341 * 342 * Returns an error if bo creation or initialization fails. 343 */ 344 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 345 { 346 int ret; 347 struct vmw_buffer_object *vbo; 348 struct ttm_bo_kmap_obj map; 349 volatile SVGA3dQueryResult *result; 350 bool dummy; 351 352 /* 353 * Create the vbo as pinned, so that a tryreserve will 354 * immediately succeed. This is because we're the only 355 * user of the bo currently. 356 */ 357 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 358 if (!vbo) 359 return -ENOMEM; 360 361 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 362 &vmw_sys_ne_placement, false, 363 &vmw_bo_bo_free); 364 if (unlikely(ret != 0)) 365 return ret; 366 367 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 368 BUG_ON(ret != 0); 369 vmw_bo_pin_reserved(vbo, true); 370 371 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 372 if (likely(ret == 0)) { 373 result = ttm_kmap_obj_virtual(&map, &dummy); 374 result->totalSize = sizeof(*result); 375 result->state = SVGA3D_QUERYSTATE_PENDING; 376 result->result32 = 0xff; 377 ttm_bo_kunmap(&map); 378 } 379 vmw_bo_pin_reserved(vbo, false); 380 ttm_bo_unreserve(&vbo->base); 381 382 if (unlikely(ret != 0)) { 383 DRM_ERROR("Dummy query buffer map failed.\n"); 384 vmw_bo_unreference(&vbo); 385 } else 386 dev_priv->dummy_query_bo = vbo; 387 388 return ret; 389 } 390 391 /** 392 * vmw_request_device_late - Perform late device setup 393 * 394 * @dev_priv: Pointer to device private. 395 * 396 * This function performs setup of otables and enables large command 397 * buffer submission. These tasks are split out to a separate function 398 * because it reverts vmw_release_device_early and is intended to be used 399 * by an error path in the hibernation code. 400 */ 401 static int vmw_request_device_late(struct vmw_private *dev_priv) 402 { 403 int ret; 404 405 if (dev_priv->has_mob) { 406 ret = vmw_otables_setup(dev_priv); 407 if (unlikely(ret != 0)) { 408 DRM_ERROR("Unable to initialize " 409 "guest Memory OBjects.\n"); 410 return ret; 411 } 412 } 413 414 if (dev_priv->cman) { 415 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 416 256*4096, 2*4096); 417 if (ret) { 418 struct vmw_cmdbuf_man *man = dev_priv->cman; 419 420 dev_priv->cman = NULL; 421 vmw_cmdbuf_man_destroy(man); 422 } 423 } 424 425 return 0; 426 } 427 428 static int vmw_request_device(struct vmw_private *dev_priv) 429 { 430 int ret; 431 432 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 433 if (unlikely(ret != 0)) { 434 DRM_ERROR("Unable to initialize FIFO.\n"); 435 return ret; 436 } 437 vmw_fence_fifo_up(dev_priv->fman); 438 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 439 if (IS_ERR(dev_priv->cman)) { 440 dev_priv->cman = NULL; 441 dev_priv->has_dx = false; 442 } 443 444 ret = vmw_request_device_late(dev_priv); 445 if (ret) 446 goto out_no_mob; 447 448 ret = vmw_dummy_query_bo_create(dev_priv); 449 if (unlikely(ret != 0)) 450 goto out_no_query_bo; 451 452 return 0; 453 454 out_no_query_bo: 455 if (dev_priv->cman) 456 vmw_cmdbuf_remove_pool(dev_priv->cman); 457 if (dev_priv->has_mob) { 458 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 459 vmw_otables_takedown(dev_priv); 460 } 461 if (dev_priv->cman) 462 vmw_cmdbuf_man_destroy(dev_priv->cman); 463 out_no_mob: 464 vmw_fence_fifo_down(dev_priv->fman); 465 vmw_fifo_release(dev_priv, &dev_priv->fifo); 466 return ret; 467 } 468 469 /** 470 * vmw_release_device_early - Early part of fifo takedown. 471 * 472 * @dev_priv: Pointer to device private struct. 473 * 474 * This is the first part of command submission takedown, to be called before 475 * buffer management is taken down. 476 */ 477 static void vmw_release_device_early(struct vmw_private *dev_priv) 478 { 479 /* 480 * Previous destructions should've released 481 * the pinned bo. 482 */ 483 484 BUG_ON(dev_priv->pinned_bo != NULL); 485 486 vmw_bo_unreference(&dev_priv->dummy_query_bo); 487 if (dev_priv->cman) 488 vmw_cmdbuf_remove_pool(dev_priv->cman); 489 490 if (dev_priv->has_mob) { 491 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 492 vmw_otables_takedown(dev_priv); 493 } 494 } 495 496 /** 497 * vmw_release_device_late - Late part of fifo takedown. 498 * 499 * @dev_priv: Pointer to device private struct. 500 * 501 * This is the last part of the command submission takedown, to be called when 502 * command submission is no longer needed. It may wait on pending fences. 503 */ 504 static void vmw_release_device_late(struct vmw_private *dev_priv) 505 { 506 vmw_fence_fifo_down(dev_priv->fman); 507 if (dev_priv->cman) 508 vmw_cmdbuf_man_destroy(dev_priv->cman); 509 510 vmw_fifo_release(dev_priv, &dev_priv->fifo); 511 } 512 513 /** 514 * Sets the initial_[width|height] fields on the given vmw_private. 515 * 516 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 517 * clamping the value to fb_max_[width|height] fields and the 518 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 519 * If the values appear to be invalid, set them to 520 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 521 */ 522 static void vmw_get_initial_size(struct vmw_private *dev_priv) 523 { 524 uint32_t width; 525 uint32_t height; 526 527 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 528 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 529 530 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 531 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 532 533 if (width > dev_priv->fb_max_width || 534 height > dev_priv->fb_max_height) { 535 536 /* 537 * This is a host error and shouldn't occur. 538 */ 539 540 width = VMW_MIN_INITIAL_WIDTH; 541 height = VMW_MIN_INITIAL_HEIGHT; 542 } 543 544 dev_priv->initial_width = width; 545 dev_priv->initial_height = height; 546 } 547 548 /** 549 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 550 * system. 551 * 552 * @dev_priv: Pointer to a struct vmw_private 553 * 554 * This functions tries to determine the IOMMU setup and what actions 555 * need to be taken by the driver to make system pages visible to the 556 * device. 557 * If this function decides that DMA is not possible, it returns -EINVAL. 558 * The driver may then try to disable features of the device that require 559 * DMA. 560 */ 561 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 562 { 563 static const char *names[vmw_dma_map_max] = { 564 [vmw_dma_phys] = "Using physical TTM page addresses.", 565 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 566 [vmw_dma_map_populate] = "Keeping DMA mappings.", 567 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 568 #ifdef CONFIG_X86 569 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); 570 571 #ifdef CONFIG_INTEL_IOMMU 572 if (intel_iommu_enabled) { 573 dev_priv->map_mode = vmw_dma_map_populate; 574 goto out_fixup; 575 } 576 #endif 577 578 if (!(vmw_force_iommu || vmw_force_coherent)) { 579 dev_priv->map_mode = vmw_dma_phys; 580 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 581 return 0; 582 } 583 584 dev_priv->map_mode = vmw_dma_map_populate; 585 586 if (dma_ops->sync_single_for_cpu) 587 dev_priv->map_mode = vmw_dma_alloc_coherent; 588 #ifdef CONFIG_SWIOTLB 589 if (swiotlb_nr_tbl() == 0) 590 dev_priv->map_mode = vmw_dma_map_populate; 591 #endif 592 593 #ifdef CONFIG_INTEL_IOMMU 594 out_fixup: 595 #endif 596 if (dev_priv->map_mode == vmw_dma_map_populate && 597 vmw_restrict_iommu) 598 dev_priv->map_mode = vmw_dma_map_bind; 599 600 if (vmw_force_coherent) 601 dev_priv->map_mode = vmw_dma_alloc_coherent; 602 603 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) 604 /* 605 * No coherent page pool 606 */ 607 if (dev_priv->map_mode == vmw_dma_alloc_coherent) 608 return -EINVAL; 609 #endif 610 611 #else /* CONFIG_X86 */ 612 dev_priv->map_mode = vmw_dma_map_populate; 613 #endif /* CONFIG_X86 */ 614 615 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 616 617 return 0; 618 } 619 620 /** 621 * vmw_dma_masks - set required page- and dma masks 622 * 623 * @dev: Pointer to struct drm-device 624 * 625 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 626 * restriction also for 64-bit systems. 627 */ 628 #ifdef CONFIG_INTEL_IOMMU 629 static int vmw_dma_masks(struct vmw_private *dev_priv) 630 { 631 struct drm_device *dev = dev_priv->dev; 632 633 if (intel_iommu_enabled && 634 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 635 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 636 return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); 637 } 638 return 0; 639 } 640 #else 641 static int vmw_dma_masks(struct vmw_private *dev_priv) 642 { 643 return 0; 644 } 645 #endif 646 647 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 648 { 649 struct vmw_private *dev_priv; 650 int ret; 651 uint32_t svga_id; 652 enum vmw_res_type i; 653 bool refuse_dma = false; 654 char host_log[100] = {0}; 655 656 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 657 if (unlikely(!dev_priv)) { 658 DRM_ERROR("Failed allocating a device private struct.\n"); 659 return -ENOMEM; 660 } 661 662 pci_set_master(dev->pdev); 663 664 dev_priv->dev = dev; 665 dev_priv->vmw_chipset = chipset; 666 dev_priv->last_read_seqno = (uint32_t) -100; 667 mutex_init(&dev_priv->cmdbuf_mutex); 668 mutex_init(&dev_priv->release_mutex); 669 mutex_init(&dev_priv->binding_mutex); 670 mutex_init(&dev_priv->requested_layout_mutex); 671 mutex_init(&dev_priv->global_kms_state_mutex); 672 ttm_lock_init(&dev_priv->reservation_sem); 673 spin_lock_init(&dev_priv->resource_lock); 674 spin_lock_init(&dev_priv->hw_lock); 675 spin_lock_init(&dev_priv->waiter_lock); 676 spin_lock_init(&dev_priv->cap_lock); 677 spin_lock_init(&dev_priv->svga_lock); 678 spin_lock_init(&dev_priv->cursor_lock); 679 680 for (i = vmw_res_context; i < vmw_res_max; ++i) { 681 idr_init(&dev_priv->res_idr[i]); 682 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 683 } 684 685 mutex_init(&dev_priv->init_mutex); 686 init_waitqueue_head(&dev_priv->fence_queue); 687 init_waitqueue_head(&dev_priv->fifo_queue); 688 dev_priv->fence_queue_waiters = 0; 689 dev_priv->fifo_queue_waiters = 0; 690 691 dev_priv->used_memory_size = 0; 692 693 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 694 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 695 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 696 697 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 698 699 dev_priv->enable_fb = enable_fbdev; 700 701 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 702 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 703 if (svga_id != SVGA_ID_2) { 704 ret = -ENOSYS; 705 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 706 goto out_err0; 707 } 708 709 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 710 711 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 712 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 713 } 714 715 716 ret = vmw_dma_select_mode(dev_priv); 717 if (unlikely(ret != 0)) { 718 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 719 refuse_dma = true; 720 } 721 722 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 723 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 724 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 725 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 726 727 vmw_get_initial_size(dev_priv); 728 729 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 730 dev_priv->max_gmr_ids = 731 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 732 dev_priv->max_gmr_pages = 733 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 734 dev_priv->memory_size = 735 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 736 dev_priv->memory_size -= dev_priv->vram_size; 737 } else { 738 /* 739 * An arbitrary limit of 512MiB on surface 740 * memory. But all HWV8 hardware supports GMR2. 741 */ 742 dev_priv->memory_size = 512*1024*1024; 743 } 744 dev_priv->max_mob_pages = 0; 745 dev_priv->max_mob_size = 0; 746 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 747 uint64_t mem_size = 748 vmw_read(dev_priv, 749 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 750 751 /* 752 * Workaround for low memory 2D VMs to compensate for the 753 * allocation taken by fbdev 754 */ 755 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 756 mem_size *= 3; 757 758 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 759 dev_priv->prim_bb_mem = 760 vmw_read(dev_priv, 761 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 762 dev_priv->max_mob_size = 763 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 764 dev_priv->stdu_max_width = 765 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 766 dev_priv->stdu_max_height = 767 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 768 769 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 770 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 771 dev_priv->texture_max_width = vmw_read(dev_priv, 772 SVGA_REG_DEV_CAP); 773 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 774 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 775 dev_priv->texture_max_height = vmw_read(dev_priv, 776 SVGA_REG_DEV_CAP); 777 } else { 778 dev_priv->texture_max_width = 8192; 779 dev_priv->texture_max_height = 8192; 780 dev_priv->prim_bb_mem = dev_priv->vram_size; 781 } 782 783 vmw_print_capabilities(dev_priv->capabilities); 784 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 785 vmw_print_capabilities2(dev_priv->capabilities2); 786 787 ret = vmw_dma_masks(dev_priv); 788 if (unlikely(ret != 0)) 789 goto out_err0; 790 791 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 792 DRM_INFO("Max GMR ids is %u\n", 793 (unsigned)dev_priv->max_gmr_ids); 794 DRM_INFO("Max number of GMR pages is %u\n", 795 (unsigned)dev_priv->max_gmr_pages); 796 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 797 (unsigned)dev_priv->memory_size / 1024); 798 } 799 DRM_INFO("Maximum display memory size is %u kiB\n", 800 dev_priv->prim_bb_mem / 1024); 801 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 802 dev_priv->vram_start, dev_priv->vram_size / 1024); 803 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 804 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 805 806 ret = vmw_ttm_global_init(dev_priv); 807 if (unlikely(ret != 0)) 808 goto out_err0; 809 810 811 vmw_master_init(&dev_priv->fbdev_master); 812 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 813 dev_priv->active_master = &dev_priv->fbdev_master; 814 815 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 816 dev_priv->mmio_size, MEMREMAP_WB); 817 818 if (unlikely(dev_priv->mmio_virt == NULL)) { 819 ret = -ENOMEM; 820 DRM_ERROR("Failed mapping MMIO.\n"); 821 goto out_err3; 822 } 823 824 /* Need mmio memory to check for fifo pitchlock cap. */ 825 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 826 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 827 !vmw_fifo_have_pitchlock(dev_priv)) { 828 ret = -ENOSYS; 829 DRM_ERROR("Hardware has no pitchlock\n"); 830 goto out_err4; 831 } 832 833 dev_priv->tdev = ttm_object_device_init 834 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); 835 836 if (unlikely(dev_priv->tdev == NULL)) { 837 DRM_ERROR("Unable to initialize TTM object management.\n"); 838 ret = -ENOMEM; 839 goto out_err4; 840 } 841 842 dev->dev_private = dev_priv; 843 844 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 845 dev_priv->stealth = (ret != 0); 846 if (dev_priv->stealth) { 847 /** 848 * Request at least the mmio PCI resource. 849 */ 850 851 DRM_INFO("It appears like vesafb is loaded. " 852 "Ignore above error if any.\n"); 853 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 854 if (unlikely(ret != 0)) { 855 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 856 goto out_no_device; 857 } 858 } 859 860 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 861 ret = vmw_irq_install(dev, dev->pdev->irq); 862 if (ret != 0) { 863 DRM_ERROR("Failed installing irq: %d\n", ret); 864 goto out_no_irq; 865 } 866 } 867 868 dev_priv->fman = vmw_fence_manager_init(dev_priv); 869 if (unlikely(dev_priv->fman == NULL)) { 870 ret = -ENOMEM; 871 goto out_no_fman; 872 } 873 874 ret = ttm_bo_device_init(&dev_priv->bdev, 875 dev_priv->bo_global_ref.ref.object, 876 &vmw_bo_driver, 877 dev->anon_inode->i_mapping, 878 VMWGFX_FILE_PAGE_OFFSET, 879 false); 880 if (unlikely(ret != 0)) { 881 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 882 goto out_no_bdev; 883 } 884 885 /* 886 * Enable VRAM, but initially don't use it until SVGA is enabled and 887 * unhidden. 888 */ 889 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 890 (dev_priv->vram_size >> PAGE_SHIFT)); 891 if (unlikely(ret != 0)) { 892 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 893 goto out_no_vram; 894 } 895 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 896 897 dev_priv->has_gmr = true; 898 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 899 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 900 VMW_PL_GMR) != 0) { 901 DRM_INFO("No GMR memory available. " 902 "Graphics memory resources are very limited.\n"); 903 dev_priv->has_gmr = false; 904 } 905 906 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 907 dev_priv->has_mob = true; 908 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 909 VMW_PL_MOB) != 0) { 910 DRM_INFO("No MOB memory available. " 911 "3D will be disabled.\n"); 912 dev_priv->has_mob = false; 913 } 914 } 915 916 if (dev_priv->has_mob) { 917 spin_lock(&dev_priv->cap_lock); 918 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 919 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 920 spin_unlock(&dev_priv->cap_lock); 921 } 922 923 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 924 ret = vmw_kms_init(dev_priv); 925 if (unlikely(ret != 0)) 926 goto out_no_kms; 927 vmw_overlay_init(dev_priv); 928 929 ret = vmw_request_device(dev_priv); 930 if (ret) 931 goto out_no_fifo; 932 933 if (dev_priv->has_dx) { 934 /* 935 * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 936 * support 937 */ 938 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) { 939 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 940 SVGA3D_DEVCAP_SM41); 941 dev_priv->has_sm4_1 = vmw_read(dev_priv, 942 SVGA_REG_DEV_CAP); 943 } 944 } 945 946 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 947 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 948 ? "yes." : "no."); 949 DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no."); 950 951 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 952 VMWGFX_REPO, VMWGFX_GIT_VERSION); 953 vmw_host_log(host_log); 954 955 memset(host_log, 0, sizeof(host_log)); 956 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 957 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 958 VMWGFX_DRIVER_PATCHLEVEL); 959 vmw_host_log(host_log); 960 961 if (dev_priv->enable_fb) { 962 vmw_fifo_resource_inc(dev_priv); 963 vmw_svga_enable(dev_priv); 964 vmw_fb_init(dev_priv); 965 } 966 967 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 968 register_pm_notifier(&dev_priv->pm_nb); 969 970 return 0; 971 972 out_no_fifo: 973 vmw_overlay_close(dev_priv); 974 vmw_kms_close(dev_priv); 975 out_no_kms: 976 if (dev_priv->has_mob) 977 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 978 if (dev_priv->has_gmr) 979 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 980 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 981 out_no_vram: 982 (void)ttm_bo_device_release(&dev_priv->bdev); 983 out_no_bdev: 984 vmw_fence_manager_takedown(dev_priv->fman); 985 out_no_fman: 986 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 987 vmw_irq_uninstall(dev_priv->dev); 988 out_no_irq: 989 if (dev_priv->stealth) 990 pci_release_region(dev->pdev, 2); 991 else 992 pci_release_regions(dev->pdev); 993 out_no_device: 994 ttm_object_device_release(&dev_priv->tdev); 995 out_err4: 996 memunmap(dev_priv->mmio_virt); 997 out_err3: 998 vmw_ttm_global_release(dev_priv); 999 out_err0: 1000 for (i = vmw_res_context; i < vmw_res_max; ++i) 1001 idr_destroy(&dev_priv->res_idr[i]); 1002 1003 if (dev_priv->ctx.staged_bindings) 1004 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1005 kfree(dev_priv); 1006 return ret; 1007 } 1008 1009 static void vmw_driver_unload(struct drm_device *dev) 1010 { 1011 struct vmw_private *dev_priv = vmw_priv(dev); 1012 enum vmw_res_type i; 1013 1014 unregister_pm_notifier(&dev_priv->pm_nb); 1015 1016 if (dev_priv->ctx.res_ht_initialized) 1017 drm_ht_remove(&dev_priv->ctx.res_ht); 1018 vfree(dev_priv->ctx.cmd_bounce); 1019 if (dev_priv->enable_fb) { 1020 vmw_fb_off(dev_priv); 1021 vmw_fb_close(dev_priv); 1022 vmw_fifo_resource_dec(dev_priv); 1023 vmw_svga_disable(dev_priv); 1024 } 1025 1026 vmw_kms_close(dev_priv); 1027 vmw_overlay_close(dev_priv); 1028 1029 if (dev_priv->has_gmr) 1030 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 1031 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 1032 1033 vmw_release_device_early(dev_priv); 1034 if (dev_priv->has_mob) 1035 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 1036 (void) ttm_bo_device_release(&dev_priv->bdev); 1037 vmw_release_device_late(dev_priv); 1038 vmw_fence_manager_takedown(dev_priv->fman); 1039 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1040 vmw_irq_uninstall(dev_priv->dev); 1041 if (dev_priv->stealth) 1042 pci_release_region(dev->pdev, 2); 1043 else 1044 pci_release_regions(dev->pdev); 1045 1046 ttm_object_device_release(&dev_priv->tdev); 1047 memunmap(dev_priv->mmio_virt); 1048 if (dev_priv->ctx.staged_bindings) 1049 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1050 vmw_ttm_global_release(dev_priv); 1051 1052 for (i = vmw_res_context; i < vmw_res_max; ++i) 1053 idr_destroy(&dev_priv->res_idr[i]); 1054 1055 kfree(dev_priv); 1056 } 1057 1058 static void vmw_postclose(struct drm_device *dev, 1059 struct drm_file *file_priv) 1060 { 1061 struct vmw_fpriv *vmw_fp; 1062 1063 vmw_fp = vmw_fpriv(file_priv); 1064 1065 if (vmw_fp->locked_master) { 1066 struct vmw_master *vmaster = 1067 vmw_master(vmw_fp->locked_master); 1068 1069 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1070 ttm_vt_unlock(&vmaster->lock); 1071 drm_master_put(&vmw_fp->locked_master); 1072 } 1073 1074 ttm_object_file_release(&vmw_fp->tfile); 1075 kfree(vmw_fp); 1076 } 1077 1078 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1079 { 1080 struct vmw_private *dev_priv = vmw_priv(dev); 1081 struct vmw_fpriv *vmw_fp; 1082 int ret = -ENOMEM; 1083 1084 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1085 if (unlikely(!vmw_fp)) 1086 return ret; 1087 1088 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1089 if (unlikely(vmw_fp->tfile == NULL)) 1090 goto out_no_tfile; 1091 1092 file_priv->driver_priv = vmw_fp; 1093 1094 return 0; 1095 1096 out_no_tfile: 1097 kfree(vmw_fp); 1098 return ret; 1099 } 1100 1101 static struct vmw_master *vmw_master_check(struct drm_device *dev, 1102 struct drm_file *file_priv, 1103 unsigned int flags) 1104 { 1105 int ret; 1106 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1107 struct vmw_master *vmaster; 1108 1109 if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH)) 1110 return NULL; 1111 1112 ret = mutex_lock_interruptible(&dev->master_mutex); 1113 if (unlikely(ret != 0)) 1114 return ERR_PTR(-ERESTARTSYS); 1115 1116 if (drm_is_current_master(file_priv)) { 1117 mutex_unlock(&dev->master_mutex); 1118 return NULL; 1119 } 1120 1121 /* 1122 * Check if we were previously master, but now dropped. In that 1123 * case, allow at least render node functionality. 1124 */ 1125 if (vmw_fp->locked_master) { 1126 mutex_unlock(&dev->master_mutex); 1127 1128 if (flags & DRM_RENDER_ALLOW) 1129 return NULL; 1130 1131 DRM_ERROR("Dropped master trying to access ioctl that " 1132 "requires authentication.\n"); 1133 return ERR_PTR(-EACCES); 1134 } 1135 mutex_unlock(&dev->master_mutex); 1136 1137 /* 1138 * Take the TTM lock. Possibly sleep waiting for the authenticating 1139 * master to become master again, or for a SIGTERM if the 1140 * authenticating master exits. 1141 */ 1142 vmaster = vmw_master(file_priv->master); 1143 ret = ttm_read_lock(&vmaster->lock, true); 1144 if (unlikely(ret != 0)) 1145 vmaster = ERR_PTR(ret); 1146 1147 return vmaster; 1148 } 1149 1150 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1151 unsigned long arg, 1152 long (*ioctl_func)(struct file *, unsigned int, 1153 unsigned long)) 1154 { 1155 struct drm_file *file_priv = filp->private_data; 1156 struct drm_device *dev = file_priv->minor->dev; 1157 unsigned int nr = DRM_IOCTL_NR(cmd); 1158 struct vmw_master *vmaster; 1159 unsigned int flags; 1160 long ret; 1161 1162 /* 1163 * Do extra checking on driver private ioctls. 1164 */ 1165 1166 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1167 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1168 const struct drm_ioctl_desc *ioctl = 1169 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1170 1171 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1172 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); 1173 if (unlikely(ret != 0)) 1174 return ret; 1175 1176 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) 1177 goto out_io_encoding; 1178 1179 return (long) vmw_execbuf_ioctl(dev, arg, file_priv, 1180 _IOC_SIZE(cmd)); 1181 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1182 if (!drm_is_current_master(file_priv) && 1183 !capable(CAP_SYS_ADMIN)) 1184 return -EACCES; 1185 } 1186 1187 if (unlikely(ioctl->cmd != cmd)) 1188 goto out_io_encoding; 1189 1190 flags = ioctl->flags; 1191 } else if (!drm_ioctl_flags(nr, &flags)) 1192 return -EINVAL; 1193 1194 vmaster = vmw_master_check(dev, file_priv, flags); 1195 if (IS_ERR(vmaster)) { 1196 ret = PTR_ERR(vmaster); 1197 1198 if (ret != -ERESTARTSYS) 1199 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", 1200 nr, ret); 1201 return ret; 1202 } 1203 1204 ret = ioctl_func(filp, cmd, arg); 1205 if (vmaster) 1206 ttm_read_unlock(&vmaster->lock); 1207 1208 return ret; 1209 1210 out_io_encoding: 1211 DRM_ERROR("Invalid command format, ioctl %d\n", 1212 nr - DRM_COMMAND_BASE); 1213 1214 return -EINVAL; 1215 } 1216 1217 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1218 unsigned long arg) 1219 { 1220 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1221 } 1222 1223 #ifdef CONFIG_COMPAT 1224 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1225 unsigned long arg) 1226 { 1227 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1228 } 1229 #endif 1230 1231 static void vmw_lastclose(struct drm_device *dev) 1232 { 1233 } 1234 1235 static void vmw_master_init(struct vmw_master *vmaster) 1236 { 1237 ttm_lock_init(&vmaster->lock); 1238 } 1239 1240 static int vmw_master_create(struct drm_device *dev, 1241 struct drm_master *master) 1242 { 1243 struct vmw_master *vmaster; 1244 1245 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); 1246 if (unlikely(!vmaster)) 1247 return -ENOMEM; 1248 1249 vmw_master_init(vmaster); 1250 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1251 master->driver_priv = vmaster; 1252 1253 return 0; 1254 } 1255 1256 static void vmw_master_destroy(struct drm_device *dev, 1257 struct drm_master *master) 1258 { 1259 struct vmw_master *vmaster = vmw_master(master); 1260 1261 master->driver_priv = NULL; 1262 kfree(vmaster); 1263 } 1264 1265 static int vmw_master_set(struct drm_device *dev, 1266 struct drm_file *file_priv, 1267 bool from_open) 1268 { 1269 struct vmw_private *dev_priv = vmw_priv(dev); 1270 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1271 struct vmw_master *active = dev_priv->active_master; 1272 struct vmw_master *vmaster = vmw_master(file_priv->master); 1273 int ret = 0; 1274 1275 if (active) { 1276 BUG_ON(active != &dev_priv->fbdev_master); 1277 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 1278 if (unlikely(ret != 0)) 1279 return ret; 1280 1281 ttm_lock_set_kill(&active->lock, true, SIGTERM); 1282 dev_priv->active_master = NULL; 1283 } 1284 1285 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1286 if (!from_open) { 1287 ttm_vt_unlock(&vmaster->lock); 1288 BUG_ON(vmw_fp->locked_master != file_priv->master); 1289 drm_master_put(&vmw_fp->locked_master); 1290 } 1291 1292 dev_priv->active_master = vmaster; 1293 drm_sysfs_hotplug_event(dev); 1294 1295 return 0; 1296 } 1297 1298 static void vmw_master_drop(struct drm_device *dev, 1299 struct drm_file *file_priv) 1300 { 1301 struct vmw_private *dev_priv = vmw_priv(dev); 1302 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1303 struct vmw_master *vmaster = vmw_master(file_priv->master); 1304 int ret; 1305 1306 /** 1307 * Make sure the master doesn't disappear while we have 1308 * it locked. 1309 */ 1310 1311 vmw_fp->locked_master = drm_master_get(file_priv->master); 1312 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 1313 vmw_kms_legacy_hotspot_clear(dev_priv); 1314 if (unlikely((ret != 0))) { 1315 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 1316 drm_master_put(&vmw_fp->locked_master); 1317 } 1318 1319 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1320 1321 if (!dev_priv->enable_fb) 1322 vmw_svga_disable(dev_priv); 1323 1324 dev_priv->active_master = &dev_priv->fbdev_master; 1325 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 1326 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 1327 } 1328 1329 /** 1330 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1331 * 1332 * @dev_priv: Pointer to device private struct. 1333 * Needs the reservation sem to be held in non-exclusive mode. 1334 */ 1335 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1336 { 1337 spin_lock(&dev_priv->svga_lock); 1338 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1339 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1340 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1341 } 1342 spin_unlock(&dev_priv->svga_lock); 1343 } 1344 1345 /** 1346 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1347 * 1348 * @dev_priv: Pointer to device private struct. 1349 */ 1350 void vmw_svga_enable(struct vmw_private *dev_priv) 1351 { 1352 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1353 __vmw_svga_enable(dev_priv); 1354 ttm_read_unlock(&dev_priv->reservation_sem); 1355 } 1356 1357 /** 1358 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1359 * 1360 * @dev_priv: Pointer to device private struct. 1361 * Needs the reservation sem to be held in exclusive mode. 1362 * Will not empty VRAM. VRAM must be emptied by caller. 1363 */ 1364 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1365 { 1366 spin_lock(&dev_priv->svga_lock); 1367 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1368 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1369 vmw_write(dev_priv, SVGA_REG_ENABLE, 1370 SVGA_REG_ENABLE_HIDE | 1371 SVGA_REG_ENABLE_ENABLE); 1372 } 1373 spin_unlock(&dev_priv->svga_lock); 1374 } 1375 1376 /** 1377 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1378 * running. 1379 * 1380 * @dev_priv: Pointer to device private struct. 1381 * Will empty VRAM. 1382 */ 1383 void vmw_svga_disable(struct vmw_private *dev_priv) 1384 { 1385 /* 1386 * Disabling SVGA will turn off device modesetting capabilities, so 1387 * notify KMS about that so that it doesn't cache atomic state that 1388 * isn't valid anymore, for example crtcs turned on. 1389 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1390 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1391 * end up with lock order reversal. Thus, a master may actually perform 1392 * a new modeset just after we call vmw_kms_lost_device() and race with 1393 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1394 * to be inconsistent with the device, causing modesetting problems. 1395 * 1396 */ 1397 vmw_kms_lost_device(dev_priv->dev); 1398 ttm_write_lock(&dev_priv->reservation_sem, false); 1399 spin_lock(&dev_priv->svga_lock); 1400 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1401 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1402 spin_unlock(&dev_priv->svga_lock); 1403 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1404 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1405 vmw_write(dev_priv, SVGA_REG_ENABLE, 1406 SVGA_REG_ENABLE_HIDE | 1407 SVGA_REG_ENABLE_ENABLE); 1408 } else 1409 spin_unlock(&dev_priv->svga_lock); 1410 ttm_write_unlock(&dev_priv->reservation_sem); 1411 } 1412 1413 static void vmw_remove(struct pci_dev *pdev) 1414 { 1415 struct drm_device *dev = pci_get_drvdata(pdev); 1416 1417 pci_disable_device(pdev); 1418 drm_put_dev(dev); 1419 } 1420 1421 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1422 void *ptr) 1423 { 1424 struct vmw_private *dev_priv = 1425 container_of(nb, struct vmw_private, pm_nb); 1426 1427 switch (val) { 1428 case PM_HIBERNATION_PREPARE: 1429 /* 1430 * Take the reservation sem in write mode, which will make sure 1431 * there are no other processes holding a buffer object 1432 * reservation, meaning we should be able to evict all buffer 1433 * objects if needed. 1434 * Once user-space processes have been frozen, we can release 1435 * the lock again. 1436 */ 1437 ttm_suspend_lock(&dev_priv->reservation_sem); 1438 dev_priv->suspend_locked = true; 1439 break; 1440 case PM_POST_HIBERNATION: 1441 case PM_POST_RESTORE: 1442 if (READ_ONCE(dev_priv->suspend_locked)) { 1443 dev_priv->suspend_locked = false; 1444 ttm_suspend_unlock(&dev_priv->reservation_sem); 1445 } 1446 break; 1447 default: 1448 break; 1449 } 1450 return 0; 1451 } 1452 1453 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1454 { 1455 struct drm_device *dev = pci_get_drvdata(pdev); 1456 struct vmw_private *dev_priv = vmw_priv(dev); 1457 1458 if (dev_priv->refuse_hibernation) 1459 return -EBUSY; 1460 1461 pci_save_state(pdev); 1462 pci_disable_device(pdev); 1463 pci_set_power_state(pdev, PCI_D3hot); 1464 return 0; 1465 } 1466 1467 static int vmw_pci_resume(struct pci_dev *pdev) 1468 { 1469 pci_set_power_state(pdev, PCI_D0); 1470 pci_restore_state(pdev); 1471 return pci_enable_device(pdev); 1472 } 1473 1474 static int vmw_pm_suspend(struct device *kdev) 1475 { 1476 struct pci_dev *pdev = to_pci_dev(kdev); 1477 struct pm_message dummy; 1478 1479 dummy.event = 0; 1480 1481 return vmw_pci_suspend(pdev, dummy); 1482 } 1483 1484 static int vmw_pm_resume(struct device *kdev) 1485 { 1486 struct pci_dev *pdev = to_pci_dev(kdev); 1487 1488 return vmw_pci_resume(pdev); 1489 } 1490 1491 static int vmw_pm_freeze(struct device *kdev) 1492 { 1493 struct pci_dev *pdev = to_pci_dev(kdev); 1494 struct drm_device *dev = pci_get_drvdata(pdev); 1495 struct vmw_private *dev_priv = vmw_priv(dev); 1496 int ret; 1497 1498 /* 1499 * Unlock for vmw_kms_suspend. 1500 * No user-space processes should be running now. 1501 */ 1502 ttm_suspend_unlock(&dev_priv->reservation_sem); 1503 ret = vmw_kms_suspend(dev_priv->dev); 1504 if (ret) { 1505 ttm_suspend_lock(&dev_priv->reservation_sem); 1506 DRM_ERROR("Failed to freeze modesetting.\n"); 1507 return ret; 1508 } 1509 if (dev_priv->enable_fb) 1510 vmw_fb_off(dev_priv); 1511 1512 ttm_suspend_lock(&dev_priv->reservation_sem); 1513 vmw_execbuf_release_pinned_bo(dev_priv); 1514 vmw_resource_evict_all(dev_priv); 1515 vmw_release_device_early(dev_priv); 1516 ttm_bo_swapout_all(&dev_priv->bdev); 1517 if (dev_priv->enable_fb) 1518 vmw_fifo_resource_dec(dev_priv); 1519 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1520 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1521 if (dev_priv->enable_fb) 1522 vmw_fifo_resource_inc(dev_priv); 1523 WARN_ON(vmw_request_device_late(dev_priv)); 1524 dev_priv->suspend_locked = false; 1525 ttm_suspend_unlock(&dev_priv->reservation_sem); 1526 if (dev_priv->suspend_state) 1527 vmw_kms_resume(dev); 1528 if (dev_priv->enable_fb) 1529 vmw_fb_on(dev_priv); 1530 return -EBUSY; 1531 } 1532 1533 vmw_fence_fifo_down(dev_priv->fman); 1534 __vmw_svga_disable(dev_priv); 1535 1536 vmw_release_device_late(dev_priv); 1537 return 0; 1538 } 1539 1540 static int vmw_pm_restore(struct device *kdev) 1541 { 1542 struct pci_dev *pdev = to_pci_dev(kdev); 1543 struct drm_device *dev = pci_get_drvdata(pdev); 1544 struct vmw_private *dev_priv = vmw_priv(dev); 1545 int ret; 1546 1547 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1548 (void) vmw_read(dev_priv, SVGA_REG_ID); 1549 1550 if (dev_priv->enable_fb) 1551 vmw_fifo_resource_inc(dev_priv); 1552 1553 ret = vmw_request_device(dev_priv); 1554 if (ret) 1555 return ret; 1556 1557 if (dev_priv->enable_fb) 1558 __vmw_svga_enable(dev_priv); 1559 1560 vmw_fence_fifo_up(dev_priv->fman); 1561 dev_priv->suspend_locked = false; 1562 ttm_suspend_unlock(&dev_priv->reservation_sem); 1563 if (dev_priv->suspend_state) 1564 vmw_kms_resume(dev_priv->dev); 1565 1566 if (dev_priv->enable_fb) 1567 vmw_fb_on(dev_priv); 1568 1569 return 0; 1570 } 1571 1572 static const struct dev_pm_ops vmw_pm_ops = { 1573 .freeze = vmw_pm_freeze, 1574 .thaw = vmw_pm_restore, 1575 .restore = vmw_pm_restore, 1576 .suspend = vmw_pm_suspend, 1577 .resume = vmw_pm_resume, 1578 }; 1579 1580 static const struct file_operations vmwgfx_driver_fops = { 1581 .owner = THIS_MODULE, 1582 .open = drm_open, 1583 .release = drm_release, 1584 .unlocked_ioctl = vmw_unlocked_ioctl, 1585 .mmap = vmw_mmap, 1586 .poll = vmw_fops_poll, 1587 .read = vmw_fops_read, 1588 #if defined(CONFIG_COMPAT) 1589 .compat_ioctl = vmw_compat_ioctl, 1590 #endif 1591 .llseek = noop_llseek, 1592 }; 1593 1594 static struct drm_driver driver = { 1595 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | 1596 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC, 1597 .load = vmw_driver_load, 1598 .unload = vmw_driver_unload, 1599 .lastclose = vmw_lastclose, 1600 .get_vblank_counter = vmw_get_vblank_counter, 1601 .enable_vblank = vmw_enable_vblank, 1602 .disable_vblank = vmw_disable_vblank, 1603 .ioctls = vmw_ioctls, 1604 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1605 .master_create = vmw_master_create, 1606 .master_destroy = vmw_master_destroy, 1607 .master_set = vmw_master_set, 1608 .master_drop = vmw_master_drop, 1609 .open = vmw_driver_open, 1610 .postclose = vmw_postclose, 1611 1612 .dumb_create = vmw_dumb_create, 1613 .dumb_map_offset = vmw_dumb_map_offset, 1614 .dumb_destroy = vmw_dumb_destroy, 1615 1616 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1617 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1618 1619 .fops = &vmwgfx_driver_fops, 1620 .name = VMWGFX_DRIVER_NAME, 1621 .desc = VMWGFX_DRIVER_DESC, 1622 .date = VMWGFX_DRIVER_DATE, 1623 .major = VMWGFX_DRIVER_MAJOR, 1624 .minor = VMWGFX_DRIVER_MINOR, 1625 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1626 }; 1627 1628 static struct pci_driver vmw_pci_driver = { 1629 .name = VMWGFX_DRIVER_NAME, 1630 .id_table = vmw_pci_id_list, 1631 .probe = vmw_probe, 1632 .remove = vmw_remove, 1633 .driver = { 1634 .pm = &vmw_pm_ops 1635 } 1636 }; 1637 1638 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1639 { 1640 return drm_get_pci_dev(pdev, ent, &driver); 1641 } 1642 1643 static int __init vmwgfx_init(void) 1644 { 1645 int ret; 1646 1647 if (vgacon_text_force()) 1648 return -EINVAL; 1649 1650 ret = pci_register_driver(&vmw_pci_driver); 1651 if (ret) 1652 DRM_ERROR("Failed initializing DRM.\n"); 1653 return ret; 1654 } 1655 1656 static void __exit vmwgfx_exit(void) 1657 { 1658 pci_unregister_driver(&vmw_pci_driver); 1659 } 1660 1661 module_init(vmwgfx_init); 1662 module_exit(vmwgfx_exit); 1663 1664 MODULE_AUTHOR("VMware Inc. and others"); 1665 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1666 MODULE_LICENSE("GPL and additional rights"); 1667 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1668 __stringify(VMWGFX_DRIVER_MINOR) "." 1669 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1670 "0"); 1671