1 /************************************************************************** 2 * 3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include "drmP.h" 29 #include "vmwgfx_drv.h" 30 #include "ttm/ttm_placement.h" 31 #include "ttm/ttm_bo_driver.h" 32 #include "ttm/ttm_object.h" 33 #include "ttm/ttm_module.h" 34 35 #define VMWGFX_DRIVER_NAME "vmwgfx" 36 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 37 #define VMWGFX_CHIP_SVGAII 0 38 #define VMW_FB_RESERVATION 0 39 40 /** 41 * Fully encoded drm commands. Might move to vmw_drm.h 42 */ 43 44 #define DRM_IOCTL_VMW_GET_PARAM \ 45 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 46 struct drm_vmw_getparam_arg) 47 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 48 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 49 union drm_vmw_alloc_dmabuf_arg) 50 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 51 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 52 struct drm_vmw_unref_dmabuf_arg) 53 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 54 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 55 struct drm_vmw_cursor_bypass_arg) 56 57 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 58 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 59 struct drm_vmw_control_stream_arg) 60 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 61 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 62 struct drm_vmw_stream_arg) 63 #define DRM_IOCTL_VMW_UNREF_STREAM \ 64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 65 struct drm_vmw_stream_arg) 66 67 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 68 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 69 struct drm_vmw_context_arg) 70 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 72 struct drm_vmw_context_arg) 73 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 74 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 75 union drm_vmw_surface_create_arg) 76 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 78 struct drm_vmw_surface_arg) 79 #define DRM_IOCTL_VMW_REF_SURFACE \ 80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 81 union drm_vmw_surface_reference_arg) 82 #define DRM_IOCTL_VMW_EXECBUF \ 83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 84 struct drm_vmw_execbuf_arg) 85 #define DRM_IOCTL_VMW_FIFO_DEBUG \ 86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FIFO_DEBUG, \ 87 struct drm_vmw_fifo_debug_arg) 88 #define DRM_IOCTL_VMW_FENCE_WAIT \ 89 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 90 struct drm_vmw_fence_wait_arg) 91 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 92 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 93 struct drm_vmw_update_layout_arg) 94 95 96 /** 97 * The core DRM version of this macro doesn't account for 98 * DRM_COMMAND_BASE. 99 */ 100 101 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 102 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func} 103 104 /** 105 * Ioctl definitions. 106 */ 107 108 static struct drm_ioctl_desc vmw_ioctls[] = { 109 VMW_IOCTL_DEF(DRM_IOCTL_VMW_GET_PARAM, vmw_getparam_ioctl, 110 DRM_AUTH | DRM_UNLOCKED), 111 VMW_IOCTL_DEF(DRM_IOCTL_VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, 112 DRM_AUTH | DRM_UNLOCKED), 113 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, 114 DRM_AUTH | DRM_UNLOCKED), 115 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CURSOR_BYPASS, 116 vmw_kms_cursor_bypass_ioctl, 117 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 118 119 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CONTROL_STREAM, vmw_overlay_ioctl, 120 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 121 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 122 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 123 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 124 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 125 126 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 127 DRM_AUTH | DRM_UNLOCKED), 128 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 129 DRM_AUTH | DRM_UNLOCKED), 130 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 131 DRM_AUTH | DRM_UNLOCKED), 132 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 133 DRM_AUTH | DRM_UNLOCKED), 134 VMW_IOCTL_DEF(DRM_IOCTL_VMW_REF_SURFACE, vmw_surface_reference_ioctl, 135 DRM_AUTH | DRM_UNLOCKED), 136 VMW_IOCTL_DEF(DRM_IOCTL_VMW_EXECBUF, vmw_execbuf_ioctl, 137 DRM_AUTH | DRM_UNLOCKED), 138 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl, 139 DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED), 140 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FENCE_WAIT, vmw_fence_wait_ioctl, 141 DRM_AUTH | DRM_UNLOCKED), 142 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UPDATE_LAYOUT, vmw_kms_update_layout_ioctl, 143 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED) 144 }; 145 146 static struct pci_device_id vmw_pci_id_list[] = { 147 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 148 {0, 0, 0} 149 }; 150 151 static char *vmw_devname = "vmwgfx"; 152 153 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 154 static void vmw_master_init(struct vmw_master *); 155 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 156 void *ptr); 157 158 static void vmw_print_capabilities(uint32_t capabilities) 159 { 160 DRM_INFO("Capabilities:\n"); 161 if (capabilities & SVGA_CAP_RECT_COPY) 162 DRM_INFO(" Rect copy.\n"); 163 if (capabilities & SVGA_CAP_CURSOR) 164 DRM_INFO(" Cursor.\n"); 165 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 166 DRM_INFO(" Cursor bypass.\n"); 167 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 168 DRM_INFO(" Cursor bypass 2.\n"); 169 if (capabilities & SVGA_CAP_8BIT_EMULATION) 170 DRM_INFO(" 8bit emulation.\n"); 171 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 172 DRM_INFO(" Alpha cursor.\n"); 173 if (capabilities & SVGA_CAP_3D) 174 DRM_INFO(" 3D.\n"); 175 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 176 DRM_INFO(" Extended Fifo.\n"); 177 if (capabilities & SVGA_CAP_MULTIMON) 178 DRM_INFO(" Multimon.\n"); 179 if (capabilities & SVGA_CAP_PITCHLOCK) 180 DRM_INFO(" Pitchlock.\n"); 181 if (capabilities & SVGA_CAP_IRQMASK) 182 DRM_INFO(" Irq mask.\n"); 183 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 184 DRM_INFO(" Display Topology.\n"); 185 if (capabilities & SVGA_CAP_GMR) 186 DRM_INFO(" GMR.\n"); 187 if (capabilities & SVGA_CAP_TRACES) 188 DRM_INFO(" Traces.\n"); 189 } 190 191 static int vmw_request_device(struct vmw_private *dev_priv) 192 { 193 int ret; 194 195 vmw_kms_save_vga(dev_priv); 196 197 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 198 if (unlikely(ret != 0)) { 199 DRM_ERROR("Unable to initialize FIFO.\n"); 200 return ret; 201 } 202 203 return 0; 204 } 205 206 static void vmw_release_device(struct vmw_private *dev_priv) 207 { 208 vmw_fifo_release(dev_priv, &dev_priv->fifo); 209 vmw_kms_restore_vga(dev_priv); 210 } 211 212 213 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 214 { 215 struct vmw_private *dev_priv; 216 int ret; 217 uint32_t svga_id; 218 219 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 220 if (unlikely(dev_priv == NULL)) { 221 DRM_ERROR("Failed allocating a device private struct.\n"); 222 return -ENOMEM; 223 } 224 memset(dev_priv, 0, sizeof(*dev_priv)); 225 226 dev_priv->dev = dev; 227 dev_priv->vmw_chipset = chipset; 228 dev_priv->last_read_sequence = (uint32_t) -100; 229 mutex_init(&dev_priv->hw_mutex); 230 mutex_init(&dev_priv->cmdbuf_mutex); 231 rwlock_init(&dev_priv->resource_lock); 232 idr_init(&dev_priv->context_idr); 233 idr_init(&dev_priv->surface_idr); 234 idr_init(&dev_priv->stream_idr); 235 ida_init(&dev_priv->gmr_ida); 236 mutex_init(&dev_priv->init_mutex); 237 init_waitqueue_head(&dev_priv->fence_queue); 238 init_waitqueue_head(&dev_priv->fifo_queue); 239 atomic_set(&dev_priv->fence_queue_waiters, 0); 240 atomic_set(&dev_priv->fifo_queue_waiters, 0); 241 INIT_LIST_HEAD(&dev_priv->gmr_lru); 242 243 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 244 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 245 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 246 247 mutex_lock(&dev_priv->hw_mutex); 248 249 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 250 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 251 if (svga_id != SVGA_ID_2) { 252 ret = -ENOSYS; 253 DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id); 254 mutex_unlock(&dev_priv->hw_mutex); 255 goto out_err0; 256 } 257 258 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 259 260 if (dev_priv->capabilities & SVGA_CAP_GMR) { 261 dev_priv->max_gmr_descriptors = 262 vmw_read(dev_priv, 263 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH); 264 dev_priv->max_gmr_ids = 265 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 266 } 267 268 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 269 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 270 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 271 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 272 273 mutex_unlock(&dev_priv->hw_mutex); 274 275 vmw_print_capabilities(dev_priv->capabilities); 276 277 if (dev_priv->capabilities & SVGA_CAP_GMR) { 278 DRM_INFO("Max GMR ids is %u\n", 279 (unsigned)dev_priv->max_gmr_ids); 280 DRM_INFO("Max GMR descriptors is %u\n", 281 (unsigned)dev_priv->max_gmr_descriptors); 282 } 283 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 284 dev_priv->vram_start, dev_priv->vram_size / 1024); 285 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 286 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 287 288 ret = vmw_ttm_global_init(dev_priv); 289 if (unlikely(ret != 0)) 290 goto out_err0; 291 292 293 vmw_master_init(&dev_priv->fbdev_master); 294 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 295 dev_priv->active_master = &dev_priv->fbdev_master; 296 297 298 ret = ttm_bo_device_init(&dev_priv->bdev, 299 dev_priv->bo_global_ref.ref.object, 300 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET, 301 false); 302 if (unlikely(ret != 0)) { 303 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 304 goto out_err1; 305 } 306 307 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 308 (dev_priv->vram_size >> PAGE_SHIFT)); 309 if (unlikely(ret != 0)) { 310 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 311 goto out_err2; 312 } 313 314 dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start, 315 dev_priv->mmio_size, DRM_MTRR_WC); 316 317 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, 318 dev_priv->mmio_size); 319 320 if (unlikely(dev_priv->mmio_virt == NULL)) { 321 ret = -ENOMEM; 322 DRM_ERROR("Failed mapping MMIO.\n"); 323 goto out_err3; 324 } 325 326 /* Need mmio memory to check for fifo pitchlock cap. */ 327 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 328 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 329 !vmw_fifo_have_pitchlock(dev_priv)) { 330 ret = -ENOSYS; 331 DRM_ERROR("Hardware has no pitchlock\n"); 332 goto out_err4; 333 } 334 335 dev_priv->tdev = ttm_object_device_init 336 (dev_priv->mem_global_ref.object, 12); 337 338 if (unlikely(dev_priv->tdev == NULL)) { 339 DRM_ERROR("Unable to initialize TTM object management.\n"); 340 ret = -ENOMEM; 341 goto out_err4; 342 } 343 344 dev->dev_private = dev_priv; 345 346 if (!dev->devname) 347 dev->devname = vmw_devname; 348 349 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 350 ret = drm_irq_install(dev); 351 if (unlikely(ret != 0)) { 352 DRM_ERROR("Failed installing irq: %d\n", ret); 353 goto out_no_irq; 354 } 355 } 356 357 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 358 dev_priv->stealth = (ret != 0); 359 if (dev_priv->stealth) { 360 /** 361 * Request at least the mmio PCI resource. 362 */ 363 364 DRM_INFO("It appears like vesafb is loaded. " 365 "Ignore above error if any.\n"); 366 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 367 if (unlikely(ret != 0)) { 368 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 369 goto out_no_device; 370 } 371 } 372 ret = vmw_request_device(dev_priv); 373 if (unlikely(ret != 0)) 374 goto out_no_device; 375 vmw_kms_init(dev_priv); 376 vmw_overlay_init(dev_priv); 377 vmw_fb_init(dev_priv); 378 379 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 380 register_pm_notifier(&dev_priv->pm_nb); 381 382 DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ? "Have 3D\n" : "No 3D\n"); 383 384 return 0; 385 386 out_no_device: 387 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 388 drm_irq_uninstall(dev_priv->dev); 389 if (dev->devname == vmw_devname) 390 dev->devname = NULL; 391 out_no_irq: 392 ttm_object_device_release(&dev_priv->tdev); 393 out_err4: 394 iounmap(dev_priv->mmio_virt); 395 out_err3: 396 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start, 397 dev_priv->mmio_size, DRM_MTRR_WC); 398 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 399 out_err2: 400 (void)ttm_bo_device_release(&dev_priv->bdev); 401 out_err1: 402 vmw_ttm_global_release(dev_priv); 403 out_err0: 404 ida_destroy(&dev_priv->gmr_ida); 405 idr_destroy(&dev_priv->surface_idr); 406 idr_destroy(&dev_priv->context_idr); 407 idr_destroy(&dev_priv->stream_idr); 408 kfree(dev_priv); 409 return ret; 410 } 411 412 static int vmw_driver_unload(struct drm_device *dev) 413 { 414 struct vmw_private *dev_priv = vmw_priv(dev); 415 416 unregister_pm_notifier(&dev_priv->pm_nb); 417 418 vmw_fb_close(dev_priv); 419 vmw_kms_close(dev_priv); 420 vmw_overlay_close(dev_priv); 421 vmw_release_device(dev_priv); 422 if (dev_priv->stealth) 423 pci_release_region(dev->pdev, 2); 424 else 425 pci_release_regions(dev->pdev); 426 427 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 428 drm_irq_uninstall(dev_priv->dev); 429 if (dev->devname == vmw_devname) 430 dev->devname = NULL; 431 ttm_object_device_release(&dev_priv->tdev); 432 iounmap(dev_priv->mmio_virt); 433 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start, 434 dev_priv->mmio_size, DRM_MTRR_WC); 435 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 436 (void)ttm_bo_device_release(&dev_priv->bdev); 437 vmw_ttm_global_release(dev_priv); 438 ida_destroy(&dev_priv->gmr_ida); 439 idr_destroy(&dev_priv->surface_idr); 440 idr_destroy(&dev_priv->context_idr); 441 idr_destroy(&dev_priv->stream_idr); 442 443 kfree(dev_priv); 444 445 return 0; 446 } 447 448 static void vmw_postclose(struct drm_device *dev, 449 struct drm_file *file_priv) 450 { 451 struct vmw_fpriv *vmw_fp; 452 453 vmw_fp = vmw_fpriv(file_priv); 454 ttm_object_file_release(&vmw_fp->tfile); 455 if (vmw_fp->locked_master) 456 drm_master_put(&vmw_fp->locked_master); 457 kfree(vmw_fp); 458 } 459 460 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 461 { 462 struct vmw_private *dev_priv = vmw_priv(dev); 463 struct vmw_fpriv *vmw_fp; 464 int ret = -ENOMEM; 465 466 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 467 if (unlikely(vmw_fp == NULL)) 468 return ret; 469 470 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 471 if (unlikely(vmw_fp->tfile == NULL)) 472 goto out_no_tfile; 473 474 file_priv->driver_priv = vmw_fp; 475 476 if (unlikely(dev_priv->bdev.dev_mapping == NULL)) 477 dev_priv->bdev.dev_mapping = 478 file_priv->filp->f_path.dentry->d_inode->i_mapping; 479 480 return 0; 481 482 out_no_tfile: 483 kfree(vmw_fp); 484 return ret; 485 } 486 487 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 488 unsigned long arg) 489 { 490 struct drm_file *file_priv = filp->private_data; 491 struct drm_device *dev = file_priv->minor->dev; 492 unsigned int nr = DRM_IOCTL_NR(cmd); 493 494 /* 495 * Do extra checking on driver private ioctls. 496 */ 497 498 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 499 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 500 struct drm_ioctl_desc *ioctl = 501 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 502 503 if (unlikely(ioctl->cmd != cmd)) { 504 DRM_ERROR("Invalid command format, ioctl %d\n", 505 nr - DRM_COMMAND_BASE); 506 return -EINVAL; 507 } 508 } 509 510 return drm_ioctl(filp, cmd, arg); 511 } 512 513 static int vmw_firstopen(struct drm_device *dev) 514 { 515 struct vmw_private *dev_priv = vmw_priv(dev); 516 dev_priv->is_opened = true; 517 518 return 0; 519 } 520 521 static void vmw_lastclose(struct drm_device *dev) 522 { 523 struct vmw_private *dev_priv = vmw_priv(dev); 524 struct drm_crtc *crtc; 525 struct drm_mode_set set; 526 int ret; 527 528 /** 529 * Do nothing on the lastclose call from drm_unload. 530 */ 531 532 if (!dev_priv->is_opened) 533 return; 534 535 dev_priv->is_opened = false; 536 set.x = 0; 537 set.y = 0; 538 set.fb = NULL; 539 set.mode = NULL; 540 set.connectors = NULL; 541 set.num_connectors = 0; 542 543 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 544 set.crtc = crtc; 545 ret = crtc->funcs->set_config(&set); 546 WARN_ON(ret != 0); 547 } 548 549 } 550 551 static void vmw_master_init(struct vmw_master *vmaster) 552 { 553 ttm_lock_init(&vmaster->lock); 554 } 555 556 static int vmw_master_create(struct drm_device *dev, 557 struct drm_master *master) 558 { 559 struct vmw_master *vmaster; 560 561 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); 562 if (unlikely(vmaster == NULL)) 563 return -ENOMEM; 564 565 ttm_lock_init(&vmaster->lock); 566 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 567 master->driver_priv = vmaster; 568 569 return 0; 570 } 571 572 static void vmw_master_destroy(struct drm_device *dev, 573 struct drm_master *master) 574 { 575 struct vmw_master *vmaster = vmw_master(master); 576 577 master->driver_priv = NULL; 578 kfree(vmaster); 579 } 580 581 582 static int vmw_master_set(struct drm_device *dev, 583 struct drm_file *file_priv, 584 bool from_open) 585 { 586 struct vmw_private *dev_priv = vmw_priv(dev); 587 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 588 struct vmw_master *active = dev_priv->active_master; 589 struct vmw_master *vmaster = vmw_master(file_priv->master); 590 int ret = 0; 591 592 if (active) { 593 BUG_ON(active != &dev_priv->fbdev_master); 594 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 595 if (unlikely(ret != 0)) 596 goto out_no_active_lock; 597 598 ttm_lock_set_kill(&active->lock, true, SIGTERM); 599 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); 600 if (unlikely(ret != 0)) { 601 DRM_ERROR("Unable to clean VRAM on " 602 "master drop.\n"); 603 } 604 605 dev_priv->active_master = NULL; 606 } 607 608 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 609 if (!from_open) { 610 ttm_vt_unlock(&vmaster->lock); 611 BUG_ON(vmw_fp->locked_master != file_priv->master); 612 drm_master_put(&vmw_fp->locked_master); 613 } 614 615 dev_priv->active_master = vmaster; 616 617 return 0; 618 619 out_no_active_lock: 620 vmw_release_device(dev_priv); 621 return ret; 622 } 623 624 static void vmw_master_drop(struct drm_device *dev, 625 struct drm_file *file_priv, 626 bool from_release) 627 { 628 struct vmw_private *dev_priv = vmw_priv(dev); 629 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 630 struct vmw_master *vmaster = vmw_master(file_priv->master); 631 int ret; 632 633 /** 634 * Make sure the master doesn't disappear while we have 635 * it locked. 636 */ 637 638 vmw_fp->locked_master = drm_master_get(file_priv->master); 639 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 640 641 if (unlikely((ret != 0))) { 642 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 643 drm_master_put(&vmw_fp->locked_master); 644 } 645 646 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 647 648 dev_priv->active_master = &dev_priv->fbdev_master; 649 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 650 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 651 652 vmw_fb_on(dev_priv); 653 } 654 655 656 static void vmw_remove(struct pci_dev *pdev) 657 { 658 struct drm_device *dev = pci_get_drvdata(pdev); 659 660 drm_put_dev(dev); 661 } 662 663 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 664 void *ptr) 665 { 666 struct vmw_private *dev_priv = 667 container_of(nb, struct vmw_private, pm_nb); 668 struct vmw_master *vmaster = dev_priv->active_master; 669 670 switch (val) { 671 case PM_HIBERNATION_PREPARE: 672 case PM_SUSPEND_PREPARE: 673 ttm_suspend_lock(&vmaster->lock); 674 675 /** 676 * This empties VRAM and unbinds all GMR bindings. 677 * Buffer contents is moved to swappable memory. 678 */ 679 ttm_bo_swapout_all(&dev_priv->bdev); 680 break; 681 case PM_POST_HIBERNATION: 682 case PM_POST_SUSPEND: 683 ttm_suspend_unlock(&vmaster->lock); 684 break; 685 case PM_RESTORE_PREPARE: 686 break; 687 case PM_POST_RESTORE: 688 break; 689 default: 690 break; 691 } 692 return 0; 693 } 694 695 /** 696 * These might not be needed with the virtual SVGA device. 697 */ 698 699 int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 700 { 701 pci_save_state(pdev); 702 pci_disable_device(pdev); 703 pci_set_power_state(pdev, PCI_D3hot); 704 return 0; 705 } 706 707 int vmw_pci_resume(struct pci_dev *pdev) 708 { 709 pci_set_power_state(pdev, PCI_D0); 710 pci_restore_state(pdev); 711 return pci_enable_device(pdev); 712 } 713 714 static struct drm_driver driver = { 715 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | 716 DRIVER_MODESET, 717 .load = vmw_driver_load, 718 .unload = vmw_driver_unload, 719 .firstopen = vmw_firstopen, 720 .lastclose = vmw_lastclose, 721 .irq_preinstall = vmw_irq_preinstall, 722 .irq_postinstall = vmw_irq_postinstall, 723 .irq_uninstall = vmw_irq_uninstall, 724 .irq_handler = vmw_irq_handler, 725 .reclaim_buffers_locked = NULL, 726 .get_map_ofs = drm_core_get_map_ofs, 727 .get_reg_ofs = drm_core_get_reg_ofs, 728 .ioctls = vmw_ioctls, 729 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls), 730 .dma_quiescent = NULL, /*vmw_dma_quiescent, */ 731 .master_create = vmw_master_create, 732 .master_destroy = vmw_master_destroy, 733 .master_set = vmw_master_set, 734 .master_drop = vmw_master_drop, 735 .open = vmw_driver_open, 736 .postclose = vmw_postclose, 737 .fops = { 738 .owner = THIS_MODULE, 739 .open = drm_open, 740 .release = drm_release, 741 .unlocked_ioctl = vmw_unlocked_ioctl, 742 .mmap = vmw_mmap, 743 .poll = drm_poll, 744 .fasync = drm_fasync, 745 #if defined(CONFIG_COMPAT) 746 .compat_ioctl = drm_compat_ioctl, 747 #endif 748 }, 749 .pci_driver = { 750 .name = VMWGFX_DRIVER_NAME, 751 .id_table = vmw_pci_id_list, 752 .probe = vmw_probe, 753 .remove = vmw_remove, 754 .suspend = vmw_pci_suspend, 755 .resume = vmw_pci_resume 756 }, 757 .name = VMWGFX_DRIVER_NAME, 758 .desc = VMWGFX_DRIVER_DESC, 759 .date = VMWGFX_DRIVER_DATE, 760 .major = VMWGFX_DRIVER_MAJOR, 761 .minor = VMWGFX_DRIVER_MINOR, 762 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 763 }; 764 765 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 766 { 767 return drm_get_pci_dev(pdev, ent, &driver); 768 } 769 770 static int __init vmwgfx_init(void) 771 { 772 int ret; 773 ret = drm_init(&driver); 774 if (ret) 775 DRM_ERROR("Failed initializing DRM.\n"); 776 return ret; 777 } 778 779 static void __exit vmwgfx_exit(void) 780 { 781 drm_exit(&driver); 782 } 783 784 module_init(vmwgfx_init); 785 module_exit(vmwgfx_exit); 786 787 MODULE_AUTHOR("VMware Inc. and others"); 788 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 789 MODULE_LICENSE("GPL and additional rights"); 790