1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright (c) 2009-2025 Broadcom. All Rights Reserved. The term 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. 6 * 7 **************************************************************************/ 8 9 #include "vmwgfx_drv.h" 10 11 #include "vmwgfx_bo.h" 12 #include "vmwgfx_binding.h" 13 #include "vmwgfx_devcaps.h" 14 #include "vmwgfx_mksstat.h" 15 #include "vmwgfx_vkms.h" 16 #include "ttm_object.h" 17 18 #include <drm/clients/drm_client_setup.h> 19 #include <drm/drm_drv.h> 20 #include <drm/drm_fbdev_ttm.h> 21 #include <drm/drm_gem_ttm_helper.h> 22 #include <drm/drm_ioctl.h> 23 #include <drm/drm_module.h> 24 #include <drm/drm_sysfs.h> 25 #include <drm/ttm/ttm_range_manager.h> 26 #include <drm/ttm/ttm_placement.h> 27 #include <generated/utsrelease.h> 28 29 #ifdef CONFIG_X86 30 #include <asm/hypervisor.h> 31 #endif 32 33 #include <linux/aperture.h> 34 #include <linux/cc_platform.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/module.h> 37 #include <linux/pci.h> 38 #include <linux/version.h> 39 #include <linux/vmalloc.h> 40 41 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 42 43 /* 44 * Fully encoded drm commands. Might move to vmw_drm.h 45 */ 46 47 #define DRM_IOCTL_VMW_GET_PARAM \ 48 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 49 struct drm_vmw_getparam_arg) 50 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 52 union drm_vmw_alloc_dmabuf_arg) 53 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 54 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 55 struct drm_vmw_unref_dmabuf_arg) 56 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 58 struct drm_vmw_cursor_bypass_arg) 59 60 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 61 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 62 struct drm_vmw_control_stream_arg) 63 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 64 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 65 struct drm_vmw_stream_arg) 66 #define DRM_IOCTL_VMW_UNREF_STREAM \ 67 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 68 struct drm_vmw_stream_arg) 69 70 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 71 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 72 struct drm_vmw_context_arg) 73 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 74 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 75 struct drm_vmw_context_arg) 76 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 77 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 78 union drm_vmw_surface_create_arg) 79 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 80 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 81 struct drm_vmw_surface_arg) 82 #define DRM_IOCTL_VMW_REF_SURFACE \ 83 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 84 union drm_vmw_surface_reference_arg) 85 #define DRM_IOCTL_VMW_EXECBUF \ 86 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 87 struct drm_vmw_execbuf_arg) 88 #define DRM_IOCTL_VMW_GET_3D_CAP \ 89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 90 struct drm_vmw_get_3d_cap_arg) 91 #define DRM_IOCTL_VMW_FENCE_WAIT \ 92 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 93 struct drm_vmw_fence_wait_arg) 94 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 96 struct drm_vmw_fence_signaled_arg) 97 #define DRM_IOCTL_VMW_FENCE_UNREF \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 99 struct drm_vmw_fence_arg) 100 #define DRM_IOCTL_VMW_FENCE_EVENT \ 101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 102 struct drm_vmw_fence_event_arg) 103 #define DRM_IOCTL_VMW_PRESENT \ 104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 105 struct drm_vmw_present_arg) 106 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 108 struct drm_vmw_present_readback_arg) 109 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 111 struct drm_vmw_update_layout_arg) 112 #define DRM_IOCTL_VMW_CREATE_SHADER \ 113 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 114 struct drm_vmw_shader_create_arg) 115 #define DRM_IOCTL_VMW_UNREF_SHADER \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 117 struct drm_vmw_shader_arg) 118 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 119 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 120 union drm_vmw_gb_surface_create_arg) 121 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 123 union drm_vmw_gb_surface_reference_arg) 124 #define DRM_IOCTL_VMW_SYNCCPU \ 125 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 126 struct drm_vmw_synccpu_arg) 127 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 128 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 129 struct drm_vmw_context_arg) 130 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 132 union drm_vmw_gb_surface_create_ext_arg) 133 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 134 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 135 union drm_vmw_gb_surface_reference_ext_arg) 136 #define DRM_IOCTL_VMW_MSG \ 137 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 138 struct drm_vmw_msg_arg) 139 #define DRM_IOCTL_VMW_MKSSTAT_RESET \ 140 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) 141 #define DRM_IOCTL_VMW_MKSSTAT_ADD \ 142 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ 143 struct drm_vmw_mksstat_add_arg) 144 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ 145 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ 146 struct drm_vmw_mksstat_remove_arg) 147 148 /* 149 * Ioctl definitions. 150 */ 151 152 static const struct drm_ioctl_desc vmw_ioctls[] = { 153 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, 154 DRM_RENDER_ALLOW), 155 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, 156 DRM_RENDER_ALLOW), 157 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 158 DRM_RENDER_ALLOW), 159 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, 160 vmw_kms_cursor_bypass_ioctl, 161 DRM_MASTER), 162 163 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 164 DRM_MASTER), 165 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 166 DRM_MASTER), 167 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 168 DRM_MASTER), 169 170 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 171 DRM_RENDER_ALLOW), 172 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 173 DRM_RENDER_ALLOW), 174 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 175 DRM_RENDER_ALLOW), 176 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 177 DRM_RENDER_ALLOW), 178 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 179 DRM_RENDER_ALLOW), 180 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, 181 DRM_RENDER_ALLOW), 182 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 183 DRM_RENDER_ALLOW), 184 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, 185 vmw_fence_obj_signaled_ioctl, 186 DRM_RENDER_ALLOW), 187 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 188 DRM_RENDER_ALLOW), 189 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 190 DRM_RENDER_ALLOW), 191 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 192 DRM_RENDER_ALLOW), 193 194 /* these allow direct access to the framebuffers mark as master only */ 195 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, 196 DRM_MASTER | DRM_AUTH), 197 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, 198 vmw_present_readback_ioctl, 199 DRM_MASTER | DRM_AUTH), 200 /* 201 * The permissions of the below ioctl are overridden in 202 * vmw_generic_ioctl(). We require either 203 * DRM_MASTER or capable(CAP_SYS_ADMIN). 204 */ 205 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, 206 vmw_kms_update_layout_ioctl, 207 DRM_RENDER_ALLOW), 208 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, 209 vmw_shader_define_ioctl, 210 DRM_RENDER_ALLOW), 211 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, 212 vmw_shader_destroy_ioctl, 213 DRM_RENDER_ALLOW), 214 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, 215 vmw_gb_surface_define_ioctl, 216 DRM_RENDER_ALLOW), 217 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, 218 vmw_gb_surface_reference_ioctl, 219 DRM_RENDER_ALLOW), 220 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, 221 vmw_user_bo_synccpu_ioctl, 222 DRM_RENDER_ALLOW), 223 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, 224 vmw_extended_context_define_ioctl, 225 DRM_RENDER_ALLOW), 226 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, 227 vmw_gb_surface_define_ext_ioctl, 228 DRM_RENDER_ALLOW), 229 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, 230 vmw_gb_surface_reference_ext_ioctl, 231 DRM_RENDER_ALLOW), 232 DRM_IOCTL_DEF_DRV(VMW_MSG, 233 vmw_msg_ioctl, 234 DRM_RENDER_ALLOW), 235 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, 236 vmw_mksstat_reset_ioctl, 237 DRM_RENDER_ALLOW), 238 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, 239 vmw_mksstat_add_ioctl, 240 DRM_RENDER_ALLOW), 241 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, 242 vmw_mksstat_remove_ioctl, 243 DRM_RENDER_ALLOW), 244 }; 245 246 static const struct pci_device_id vmw_pci_id_list[] = { 247 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, 248 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, 249 { } 250 }; 251 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 252 253 static int vmw_restrict_iommu; 254 static int vmw_force_coherent; 255 static int vmw_restrict_dma_mask; 256 static int vmw_assume_16bpp; 257 258 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 259 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 260 void *ptr); 261 262 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 263 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 264 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 265 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 266 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 267 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 268 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 269 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 270 271 272 struct bitmap_name { 273 uint32 value; 274 const char *name; 275 }; 276 277 static const struct bitmap_name cap1_names[] = { 278 { SVGA_CAP_RECT_COPY, "rect copy" }, 279 { SVGA_CAP_CURSOR, "cursor" }, 280 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, 281 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, 282 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, 283 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, 284 { SVGA_CAP_3D, "3D" }, 285 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, 286 { SVGA_CAP_MULTIMON, "multimon" }, 287 { SVGA_CAP_PITCHLOCK, "pitchlock" }, 288 { SVGA_CAP_IRQMASK, "irq mask" }, 289 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, 290 { SVGA_CAP_GMR, "gmr" }, 291 { SVGA_CAP_TRACES, "traces" }, 292 { SVGA_CAP_GMR2, "gmr2" }, 293 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, 294 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, 295 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, 296 { SVGA_CAP_GBOBJECTS, "gbobject" }, 297 { SVGA_CAP_DX, "dx" }, 298 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, 299 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, 300 { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, 301 }; 302 303 304 static const struct bitmap_name cap2_names[] = { 305 { SVGA_CAP2_GROW_OTABLE, "grow otable" }, 306 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, 307 { SVGA_CAP2_DX2, "dx2" }, 308 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, 309 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, 310 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, 311 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, 312 { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, 313 { SVGA_CAP2_MSHINT, "mshint" }, 314 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, 315 { SVGA_CAP2_DX3, "dx3" }, 316 { SVGA_CAP2_FRAME_TYPE, "frame type" }, 317 { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, 318 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, 319 { SVGA_CAP2_EXTRA_REGS, "extra regs" }, 320 { SVGA_CAP2_LO_STAGING, "lo staging" }, 321 }; 322 323 static void vmw_print_bitmap(struct drm_device *drm, 324 const char *prefix, uint32_t bitmap, 325 const struct bitmap_name *bnames, 326 uint32_t num_names) 327 { 328 char buf[512]; 329 uint32_t i; 330 uint32_t offset = 0; 331 for (i = 0; i < num_names; ++i) { 332 if ((bitmap & bnames[i].value) != 0) { 333 offset += snprintf(buf + offset, 334 ARRAY_SIZE(buf) - offset, 335 "%s, ", bnames[i].name); 336 bitmap &= ~bnames[i].value; 337 } 338 } 339 340 drm_info(drm, "%s: %s\n", prefix, buf); 341 if (bitmap != 0) 342 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap); 343 } 344 345 346 static void vmw_print_sm_type(struct vmw_private *dev_priv) 347 { 348 static const char *names[] = { 349 [VMW_SM_LEGACY] = "Legacy", 350 [VMW_SM_4] = "SM4", 351 [VMW_SM_4_1] = "SM4_1", 352 [VMW_SM_5] = "SM_5", 353 [VMW_SM_5_1X] = "SM_5_1X", 354 [VMW_SM_MAX] = "Invalid" 355 }; 356 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); 357 drm_info(&dev_priv->drm, "Available shader model: %s.\n", 358 names[dev_priv->sm_type]); 359 } 360 361 /** 362 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 363 * 364 * @dev_priv: A device private structure. 365 * 366 * This function creates a small buffer object that holds the query 367 * result for dummy queries emitted as query barriers. 368 * The function will then map the first page and initialize a pending 369 * occlusion query result structure, Finally it will unmap the buffer. 370 * No interruptible waits are done within this function. 371 * 372 * Returns an error if bo creation or initialization fails. 373 */ 374 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 375 { 376 int ret; 377 struct vmw_bo *vbo; 378 struct ttm_bo_kmap_obj map; 379 volatile SVGA3dQueryResult *result; 380 bool dummy; 381 struct vmw_bo_params bo_params = { 382 .domain = VMW_BO_DOMAIN_SYS, 383 .busy_domain = VMW_BO_DOMAIN_SYS, 384 .bo_type = ttm_bo_type_kernel, 385 .size = PAGE_SIZE, 386 .pin = true, 387 .keep_resv = true, 388 }; 389 390 /* 391 * Create the vbo as pinned, so that a tryreserve will 392 * immediately succeed. This is because we're the only 393 * user of the bo currently. 394 */ 395 ret = vmw_bo_create(dev_priv, &bo_params, &vbo); 396 if (unlikely(ret != 0)) 397 return ret; 398 399 ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map); 400 if (likely(ret == 0)) { 401 result = ttm_kmap_obj_virtual(&map, &dummy); 402 result->totalSize = sizeof(*result); 403 result->state = SVGA3D_QUERYSTATE_PENDING; 404 result->result32 = 0xff; 405 ttm_bo_kunmap(&map); 406 } 407 vmw_bo_pin_reserved(vbo, false); 408 ttm_bo_unreserve(&vbo->tbo); 409 410 if (unlikely(ret != 0)) { 411 DRM_ERROR("Dummy query buffer map failed.\n"); 412 vmw_bo_unreference(&vbo); 413 } else 414 dev_priv->dummy_query_bo = vbo; 415 416 return ret; 417 } 418 419 static int vmw_device_init(struct vmw_private *dev_priv) 420 { 421 bool uses_fb_traces = false; 422 423 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 424 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 425 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 426 427 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | 428 SVGA_REG_ENABLE_HIDE); 429 430 uses_fb_traces = !vmw_cmd_supported(dev_priv) && 431 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; 432 433 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); 434 dev_priv->fifo = vmw_fifo_create(dev_priv); 435 if (IS_ERR(dev_priv->fifo)) { 436 int err = PTR_ERR(dev_priv->fifo); 437 dev_priv->fifo = NULL; 438 return err; 439 } else if (!dev_priv->fifo) { 440 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); 441 } 442 443 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); 444 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); 445 return 0; 446 } 447 448 static void vmw_device_fini(struct vmw_private *vmw) 449 { 450 /* 451 * Legacy sync 452 */ 453 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 454 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) 455 ; 456 457 vmw->last_read_seqno = vmw_fence_read(vmw); 458 459 vmw_write(vmw, SVGA_REG_CONFIG_DONE, 460 vmw->config_done_state); 461 vmw_write(vmw, SVGA_REG_ENABLE, 462 vmw->enable_state); 463 vmw_write(vmw, SVGA_REG_TRACES, 464 vmw->traces_state); 465 466 vmw_fifo_destroy(vmw); 467 } 468 469 /** 470 * vmw_request_device_late - Perform late device setup 471 * 472 * @dev_priv: Pointer to device private. 473 * 474 * This function performs setup of otables and enables large command 475 * buffer submission. These tasks are split out to a separate function 476 * because it reverts vmw_release_device_early and is intended to be used 477 * by an error path in the hibernation code. 478 */ 479 static int vmw_request_device_late(struct vmw_private *dev_priv) 480 { 481 int ret; 482 483 if (dev_priv->has_mob) { 484 ret = vmw_otables_setup(dev_priv); 485 if (unlikely(ret != 0)) { 486 DRM_ERROR("Unable to initialize " 487 "guest Memory OBjects.\n"); 488 return ret; 489 } 490 } 491 492 if (dev_priv->cman) { 493 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096); 494 if (ret) { 495 struct vmw_cmdbuf_man *man = dev_priv->cman; 496 497 dev_priv->cman = NULL; 498 vmw_cmdbuf_man_destroy(man); 499 } 500 } 501 502 return 0; 503 } 504 505 static int vmw_request_device(struct vmw_private *dev_priv) 506 { 507 int ret; 508 509 ret = vmw_device_init(dev_priv); 510 if (unlikely(ret != 0)) { 511 DRM_ERROR("Unable to initialize the device.\n"); 512 return ret; 513 } 514 vmw_fence_fifo_up(dev_priv->fman); 515 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 516 if (IS_ERR(dev_priv->cman)) { 517 dev_priv->cman = NULL; 518 dev_priv->sm_type = VMW_SM_LEGACY; 519 } 520 521 ret = vmw_request_device_late(dev_priv); 522 if (ret) 523 goto out_no_mob; 524 525 ret = vmw_dummy_query_bo_create(dev_priv); 526 if (unlikely(ret != 0)) 527 goto out_no_query_bo; 528 529 return 0; 530 531 out_no_query_bo: 532 if (dev_priv->cman) 533 vmw_cmdbuf_remove_pool(dev_priv->cman); 534 if (dev_priv->has_mob) { 535 struct ttm_resource_manager *man; 536 537 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 538 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 539 vmw_otables_takedown(dev_priv); 540 } 541 if (dev_priv->cman) 542 vmw_cmdbuf_man_destroy(dev_priv->cman); 543 out_no_mob: 544 vmw_fence_fifo_down(dev_priv->fman); 545 vmw_device_fini(dev_priv); 546 return ret; 547 } 548 549 /** 550 * vmw_release_device_early - Early part of fifo takedown. 551 * 552 * @dev_priv: Pointer to device private struct. 553 * 554 * This is the first part of command submission takedown, to be called before 555 * buffer management is taken down. 556 */ 557 static void vmw_release_device_early(struct vmw_private *dev_priv) 558 { 559 /* 560 * Previous destructions should've released 561 * the pinned bo. 562 */ 563 564 BUG_ON(dev_priv->pinned_bo != NULL); 565 566 vmw_bo_unreference(&dev_priv->dummy_query_bo); 567 if (dev_priv->cman) 568 vmw_cmdbuf_remove_pool(dev_priv->cman); 569 570 if (dev_priv->has_mob) { 571 struct ttm_resource_manager *man; 572 573 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 574 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 575 vmw_otables_takedown(dev_priv); 576 } 577 } 578 579 /** 580 * vmw_release_device_late - Late part of fifo takedown. 581 * 582 * @dev_priv: Pointer to device private struct. 583 * 584 * This is the last part of the command submission takedown, to be called when 585 * command submission is no longer needed. It may wait on pending fences. 586 */ 587 static void vmw_release_device_late(struct vmw_private *dev_priv) 588 { 589 vmw_fence_fifo_down(dev_priv->fman); 590 if (dev_priv->cman) 591 vmw_cmdbuf_man_destroy(dev_priv->cman); 592 593 vmw_device_fini(dev_priv); 594 } 595 596 /* 597 * Sets the initial_[width|height] fields on the given vmw_private. 598 * 599 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 600 * clamping the value to fb_max_[width|height] fields and the 601 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 602 * If the values appear to be invalid, set them to 603 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 604 */ 605 static void vmw_get_initial_size(struct vmw_private *dev_priv) 606 { 607 uint32_t width; 608 uint32_t height; 609 610 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 611 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 612 613 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH); 614 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT); 615 616 if (width > dev_priv->fb_max_width || 617 height > dev_priv->fb_max_height) { 618 619 /* 620 * This is a host error and shouldn't occur. 621 */ 622 623 width = VMWGFX_MIN_INITIAL_WIDTH; 624 height = VMWGFX_MIN_INITIAL_HEIGHT; 625 } 626 627 dev_priv->initial_width = width; 628 dev_priv->initial_height = height; 629 } 630 631 /** 632 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 633 * system. 634 * 635 * @dev_priv: Pointer to a struct vmw_private 636 * 637 * This functions tries to determine what actions need to be taken by the 638 * driver to make system pages visible to the device. 639 * If this function decides that DMA is not possible, it returns -EINVAL. 640 * The driver may then try to disable features of the device that require 641 * DMA. 642 */ 643 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 644 { 645 static const char *names[vmw_dma_map_max] = { 646 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 647 [vmw_dma_map_populate] = "Caching DMA mappings.", 648 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 649 650 /* 651 * When running with SEV we always want dma mappings, because 652 * otherwise ttm tt pool pages will bounce through swiotlb running 653 * out of available space. 654 */ 655 if (vmw_force_coherent || cc_platform_has(CC_ATTR_MEM_ENCRYPT)) 656 dev_priv->map_mode = vmw_dma_alloc_coherent; 657 else if (vmw_restrict_iommu) 658 dev_priv->map_mode = vmw_dma_map_bind; 659 else 660 dev_priv->map_mode = vmw_dma_map_populate; 661 662 drm_info(&dev_priv->drm, 663 "DMA map mode: %s\n", names[dev_priv->map_mode]); 664 return 0; 665 } 666 667 /** 668 * vmw_dma_masks - set required page- and dma masks 669 * 670 * @dev_priv: Pointer to struct drm-device 671 * 672 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 673 * restriction also for 64-bit systems. 674 */ 675 static int vmw_dma_masks(struct vmw_private *dev_priv) 676 { 677 struct drm_device *dev = &dev_priv->drm; 678 int ret = 0; 679 680 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 681 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { 682 drm_info(&dev_priv->drm, 683 "Restricting DMA addresses to 44 bits.\n"); 684 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 685 } 686 687 return ret; 688 } 689 690 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 691 { 692 int ret; 693 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 694 dev_priv->vram_size >> PAGE_SHIFT); 695 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 696 return ret; 697 } 698 699 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 700 { 701 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 702 } 703 704 static int vmw_setup_pci_resources(struct vmw_private *dev, 705 u32 pci_id) 706 { 707 resource_size_t rmmio_start; 708 resource_size_t rmmio_size; 709 resource_size_t fifo_start; 710 resource_size_t fifo_size; 711 int ret; 712 struct pci_dev *pdev = to_pci_dev(dev->drm.dev); 713 714 pci_set_master(pdev); 715 716 ret = pci_request_regions(pdev, "vmwgfx probe"); 717 if (ret) 718 return ret; 719 720 dev->pci_id = pci_id; 721 if (pci_id == VMWGFX_PCI_ID_SVGA3) { 722 rmmio_start = pci_resource_start(pdev, 0); 723 rmmio_size = pci_resource_len(pdev, 0); 724 dev->vram_start = pci_resource_start(pdev, 2); 725 dev->vram_size = pci_resource_len(pdev, 2); 726 727 drm_info(&dev->drm, 728 "Register MMIO at 0x%pa size is %llu KiB\n", 729 &rmmio_start, (uint64_t)rmmio_size / 1024); 730 dev->rmmio = devm_ioremap(dev->drm.dev, 731 rmmio_start, 732 rmmio_size); 733 if (!dev->rmmio) { 734 drm_err(&dev->drm, 735 "Failed mapping registers mmio memory.\n"); 736 pci_release_regions(pdev); 737 return -ENOMEM; 738 } 739 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { 740 dev->io_start = pci_resource_start(pdev, 0); 741 dev->vram_start = pci_resource_start(pdev, 1); 742 dev->vram_size = pci_resource_len(pdev, 1); 743 fifo_start = pci_resource_start(pdev, 2); 744 fifo_size = pci_resource_len(pdev, 2); 745 746 drm_info(&dev->drm, 747 "FIFO at %pa size is %llu KiB\n", 748 &fifo_start, (uint64_t)fifo_size / 1024); 749 dev->fifo_mem = devm_memremap(dev->drm.dev, 750 fifo_start, 751 fifo_size, 752 MEMREMAP_WB | MEMREMAP_DEC); 753 754 if (IS_ERR(dev->fifo_mem)) { 755 drm_err(&dev->drm, 756 "Failed mapping FIFO memory.\n"); 757 pci_release_regions(pdev); 758 return PTR_ERR(dev->fifo_mem); 759 } 760 } else { 761 pci_release_regions(pdev); 762 return -EINVAL; 763 } 764 765 /* 766 * This is approximate size of the vram, the exact size will only 767 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource 768 * size will be equal to or bigger than the size reported by 769 * SVGA_REG_VRAM_SIZE. 770 */ 771 drm_info(&dev->drm, 772 "VRAM at %pa size is %llu KiB\n", 773 &dev->vram_start, (uint64_t)dev->vram_size / 1024); 774 775 return 0; 776 } 777 778 static int vmw_detect_version(struct vmw_private *dev) 779 { 780 uint32_t svga_id; 781 782 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? 783 SVGA_ID_3 : SVGA_ID_2); 784 svga_id = vmw_read(dev, SVGA_REG_ID); 785 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { 786 drm_err(&dev->drm, 787 "Unsupported SVGA ID 0x%x on chipset 0x%x\n", 788 svga_id, dev->pci_id); 789 return -ENOSYS; 790 } 791 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); 792 drm_info(&dev->drm, 793 "Running on SVGA version %d.\n", (svga_id & 0xff)); 794 return 0; 795 } 796 797 static void vmw_write_driver_id(struct vmw_private *dev) 798 { 799 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) { 800 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 801 SVGA_REG_GUEST_DRIVER_ID_LINUX); 802 803 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1, 804 LINUX_VERSION_MAJOR << 24 | 805 LINUX_VERSION_PATCHLEVEL << 16 | 806 LINUX_VERSION_SUBLEVEL); 807 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2, 808 VMWGFX_DRIVER_MAJOR << 24 | 809 VMWGFX_DRIVER_MINOR << 16 | 810 VMWGFX_DRIVER_PATCHLEVEL); 811 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0); 812 813 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 814 SVGA_REG_GUEST_DRIVER_ID_SUBMIT); 815 } 816 } 817 818 static void vmw_sw_context_init(struct vmw_private *dev_priv) 819 { 820 struct vmw_sw_context *sw_context = &dev_priv->ctx; 821 822 hash_init(sw_context->res_ht); 823 } 824 825 static void vmw_sw_context_fini(struct vmw_private *dev_priv) 826 { 827 struct vmw_sw_context *sw_context = &dev_priv->ctx; 828 829 vfree(sw_context->cmd_bounce); 830 if (sw_context->staged_bindings) 831 vmw_binding_state_free(sw_context->staged_bindings); 832 } 833 834 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 835 { 836 int ret; 837 enum vmw_res_type i; 838 bool refuse_dma = false; 839 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 840 841 vmw_sw_context_init(dev_priv); 842 843 mutex_init(&dev_priv->cmdbuf_mutex); 844 mutex_init(&dev_priv->binding_mutex); 845 spin_lock_init(&dev_priv->resource_lock); 846 spin_lock_init(&dev_priv->hw_lock); 847 spin_lock_init(&dev_priv->waiter_lock); 848 spin_lock_init(&dev_priv->cursor_lock); 849 850 ret = vmw_setup_pci_resources(dev_priv, pci_id); 851 if (ret) 852 return ret; 853 ret = vmw_detect_version(dev_priv); 854 if (ret) 855 goto out_no_pci_or_version; 856 857 858 for (i = vmw_res_context; i < vmw_res_max; ++i) { 859 idr_init_base(&dev_priv->res_idr[i], 1); 860 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 861 } 862 863 init_waitqueue_head(&dev_priv->fence_queue); 864 init_waitqueue_head(&dev_priv->fifo_queue); 865 dev_priv->fence_queue_waiters = 0; 866 dev_priv->fifo_queue_waiters = 0; 867 868 dev_priv->used_memory_size = 0; 869 870 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 871 872 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 873 vmw_print_bitmap(&dev_priv->drm, "Capabilities", 874 dev_priv->capabilities, 875 cap1_names, ARRAY_SIZE(cap1_names)); 876 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 877 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 878 vmw_print_bitmap(&dev_priv->drm, "Capabilities2", 879 dev_priv->capabilities2, 880 cap2_names, ARRAY_SIZE(cap2_names)); 881 } 882 883 if (!vmwgfx_supported(dev_priv)) { 884 vmw_disable_backdoor(); 885 drm_err_once(&dev_priv->drm, 886 "vmwgfx seems to be running on an unsupported hypervisor."); 887 drm_err_once(&dev_priv->drm, 888 "This configuration is likely broken."); 889 drm_err_once(&dev_priv->drm, 890 "Please switch to a supported graphics device to avoid problems."); 891 } 892 893 vmw_vkms_init(dev_priv); 894 895 ret = vmw_dma_select_mode(dev_priv); 896 if (unlikely(ret != 0)) { 897 drm_info(&dev_priv->drm, 898 "Restricting capabilities since DMA not available.\n"); 899 refuse_dma = true; 900 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 901 drm_info(&dev_priv->drm, 902 "Disabling 3D acceleration.\n"); 903 } 904 905 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 906 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 907 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 908 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 909 910 vmw_get_initial_size(dev_priv); 911 912 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 913 dev_priv->max_gmr_ids = 914 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 915 dev_priv->max_gmr_pages = 916 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 917 dev_priv->memory_size = 918 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 919 dev_priv->memory_size -= dev_priv->vram_size; 920 } else { 921 /* 922 * An arbitrary limit of 512MiB on surface 923 * memory. But all HWV8 hardware supports GMR2. 924 */ 925 dev_priv->memory_size = 512*1024*1024; 926 } 927 dev_priv->max_mob_pages = 0; 928 dev_priv->max_mob_size = 0; 929 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 930 uint64_t mem_size; 931 932 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 933 mem_size = vmw_read(dev_priv, 934 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 935 else 936 mem_size = 937 vmw_read(dev_priv, 938 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 939 940 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 941 dev_priv->max_primary_mem = 942 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM); 943 dev_priv->max_mob_size = 944 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 945 dev_priv->stdu_max_width = 946 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 947 dev_priv->stdu_max_height = 948 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 949 950 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 951 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 952 dev_priv->texture_max_width = vmw_read(dev_priv, 953 SVGA_REG_DEV_CAP); 954 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 955 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 956 dev_priv->texture_max_height = vmw_read(dev_priv, 957 SVGA_REG_DEV_CAP); 958 } else { 959 dev_priv->texture_max_width = 8192; 960 dev_priv->texture_max_height = 8192; 961 dev_priv->max_primary_mem = dev_priv->vram_size; 962 } 963 drm_info(&dev_priv->drm, 964 "Legacy memory limits: VRAM = %llu KiB, FIFO = %llu KiB, surface = %u KiB\n", 965 (u64)dev_priv->vram_size / 1024, 966 (u64)dev_priv->fifo_mem_size / 1024, 967 dev_priv->memory_size / 1024); 968 969 drm_info(&dev_priv->drm, 970 "MOB limits: max mob size = %u KiB, max mob pages = %u\n", 971 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); 972 973 ret = vmw_dma_masks(dev_priv); 974 if (unlikely(ret != 0)) 975 goto out_err0; 976 977 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX); 978 979 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 980 drm_info(&dev_priv->drm, 981 "Max GMR ids is %u\n", 982 (unsigned)dev_priv->max_gmr_ids); 983 drm_info(&dev_priv->drm, 984 "Max number of GMR pages is %u\n", 985 (unsigned)dev_priv->max_gmr_pages); 986 } 987 drm_info(&dev_priv->drm, 988 "Maximum display memory size is %llu KiB\n", 989 (uint64_t)dev_priv->max_primary_mem / 1024); 990 991 /* Need mmio memory to check for fifo pitchlock cap. */ 992 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 993 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 994 !vmw_fifo_have_pitchlock(dev_priv)) { 995 ret = -ENOSYS; 996 DRM_ERROR("Hardware has no pitchlock\n"); 997 goto out_err0; 998 } 999 1000 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops); 1001 1002 if (unlikely(dev_priv->tdev == NULL)) { 1003 drm_err(&dev_priv->drm, 1004 "Unable to initialize TTM object management.\n"); 1005 ret = -ENOMEM; 1006 goto out_err0; 1007 } 1008 1009 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 1010 ret = vmw_irq_install(dev_priv); 1011 if (ret != 0) { 1012 drm_err(&dev_priv->drm, 1013 "Failed installing irq: %d\n", ret); 1014 goto out_no_irq; 1015 } 1016 } 1017 1018 dev_priv->fman = vmw_fence_manager_init(dev_priv); 1019 if (unlikely(dev_priv->fman == NULL)) { 1020 ret = -ENOMEM; 1021 goto out_no_fman; 1022 } 1023 1024 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver, 1025 dev_priv->drm.dev, 1026 dev_priv->drm.anon_inode->i_mapping, 1027 dev_priv->drm.vma_offset_manager, 1028 dev_priv->map_mode == vmw_dma_alloc_coherent, 1029 false); 1030 if (unlikely(ret != 0)) { 1031 drm_err(&dev_priv->drm, 1032 "Failed initializing TTM buffer object driver.\n"); 1033 goto out_no_bdev; 1034 } 1035 1036 /* 1037 * Enable VRAM, but initially don't use it until SVGA is enabled and 1038 * unhidden. 1039 */ 1040 1041 ret = vmw_vram_manager_init(dev_priv); 1042 if (unlikely(ret != 0)) { 1043 drm_err(&dev_priv->drm, 1044 "Failed initializing memory manager for VRAM.\n"); 1045 goto out_no_vram; 1046 } 1047 1048 ret = vmw_devcaps_create(dev_priv); 1049 if (unlikely(ret != 0)) { 1050 drm_err(&dev_priv->drm, 1051 "Failed initializing device caps.\n"); 1052 goto out_no_vram; 1053 } 1054 1055 /* 1056 * "Guest Memory Regions" is an aperture like feature with 1057 * one slot per bo. There is an upper limit of the number of 1058 * slots as well as the bo size. 1059 */ 1060 dev_priv->has_gmr = true; 1061 /* TODO: This is most likely not correct */ 1062 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 1063 refuse_dma || 1064 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 1065 drm_info(&dev_priv->drm, 1066 "No GMR memory available. " 1067 "Graphics memory resources are very limited.\n"); 1068 dev_priv->has_gmr = false; 1069 } 1070 1071 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 1072 dev_priv->has_mob = true; 1073 1074 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 1075 drm_info(&dev_priv->drm, 1076 "No MOB memory available. " 1077 "3D will be disabled.\n"); 1078 dev_priv->has_mob = false; 1079 } 1080 if (vmw_sys_man_init(dev_priv) != 0) { 1081 drm_info(&dev_priv->drm, 1082 "No MOB page table memory available. " 1083 "3D will be disabled.\n"); 1084 dev_priv->has_mob = false; 1085 } 1086 } 1087 1088 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 1089 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) 1090 dev_priv->sm_type = VMW_SM_4; 1091 } 1092 1093 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 1094 if (has_sm4_context(dev_priv) && 1095 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 1096 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41)) 1097 dev_priv->sm_type = VMW_SM_4_1; 1098 if (has_sm4_1_context(dev_priv) && 1099 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 1100 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) { 1101 dev_priv->sm_type = VMW_SM_5; 1102 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43)) 1103 dev_priv->sm_type = VMW_SM_5_1X; 1104 } 1105 } 1106 } 1107 1108 ret = vmw_kms_init(dev_priv); 1109 if (unlikely(ret != 0)) 1110 goto out_no_kms; 1111 vmw_overlay_init(dev_priv); 1112 1113 ret = vmw_request_device(dev_priv); 1114 if (ret) 1115 goto out_no_fifo; 1116 1117 vmw_print_sm_type(dev_priv); 1118 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)", 1119 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 1120 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); 1121 vmw_write_driver_id(dev_priv); 1122 1123 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 1124 register_pm_notifier(&dev_priv->pm_nb); 1125 1126 return 0; 1127 1128 out_no_fifo: 1129 vmw_overlay_close(dev_priv); 1130 vmw_kms_close(dev_priv); 1131 out_no_kms: 1132 if (dev_priv->has_mob) { 1133 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1134 vmw_sys_man_fini(dev_priv); 1135 } 1136 if (dev_priv->has_gmr) 1137 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1138 vmw_devcaps_destroy(dev_priv); 1139 vmw_vram_manager_fini(dev_priv); 1140 out_no_vram: 1141 ttm_device_fini(&dev_priv->bdev); 1142 out_no_bdev: 1143 vmw_fence_manager_takedown(dev_priv->fman); 1144 out_no_fman: 1145 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1146 vmw_irq_uninstall(&dev_priv->drm); 1147 out_no_irq: 1148 ttm_object_device_release(&dev_priv->tdev); 1149 out_err0: 1150 for (i = vmw_res_context; i < vmw_res_max; ++i) 1151 idr_destroy(&dev_priv->res_idr[i]); 1152 1153 if (dev_priv->ctx.staged_bindings) 1154 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1155 out_no_pci_or_version: 1156 pci_release_regions(pdev); 1157 return ret; 1158 } 1159 1160 static void vmw_driver_unload(struct drm_device *dev) 1161 { 1162 struct vmw_private *dev_priv = vmw_priv(dev); 1163 struct pci_dev *pdev = to_pci_dev(dev->dev); 1164 enum vmw_res_type i; 1165 1166 unregister_pm_notifier(&dev_priv->pm_nb); 1167 1168 vmw_sw_context_fini(dev_priv); 1169 vmw_fifo_resource_dec(dev_priv); 1170 1171 vmw_svga_disable(dev_priv); 1172 1173 vmw_vkms_cleanup(dev_priv); 1174 vmw_kms_close(dev_priv); 1175 vmw_overlay_close(dev_priv); 1176 1177 if (dev_priv->has_gmr) 1178 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1179 1180 vmw_release_device_early(dev_priv); 1181 if (dev_priv->has_mob) { 1182 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1183 vmw_sys_man_fini(dev_priv); 1184 } 1185 vmw_devcaps_destroy(dev_priv); 1186 vmw_vram_manager_fini(dev_priv); 1187 ttm_device_fini(&dev_priv->bdev); 1188 vmw_release_device_late(dev_priv); 1189 vmw_fence_manager_takedown(dev_priv->fman); 1190 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1191 vmw_irq_uninstall(&dev_priv->drm); 1192 1193 ttm_object_device_release(&dev_priv->tdev); 1194 1195 for (i = vmw_res_context; i < vmw_res_max; ++i) 1196 idr_destroy(&dev_priv->res_idr[i]); 1197 1198 vmw_mksstat_remove_all(dev_priv); 1199 1200 pci_release_regions(pdev); 1201 } 1202 1203 static void vmw_postclose(struct drm_device *dev, 1204 struct drm_file *file_priv) 1205 { 1206 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1207 1208 ttm_object_file_release(&vmw_fp->tfile); 1209 kfree(vmw_fp); 1210 } 1211 1212 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1213 { 1214 struct vmw_private *dev_priv = vmw_priv(dev); 1215 struct vmw_fpriv *vmw_fp; 1216 int ret = -ENOMEM; 1217 1218 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1219 if (unlikely(!vmw_fp)) 1220 return ret; 1221 1222 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev); 1223 if (unlikely(vmw_fp->tfile == NULL)) 1224 goto out_no_tfile; 1225 1226 file_priv->driver_priv = vmw_fp; 1227 1228 return 0; 1229 1230 out_no_tfile: 1231 kfree(vmw_fp); 1232 return ret; 1233 } 1234 1235 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1236 unsigned long arg, 1237 long (*ioctl_func)(struct file *, unsigned int, 1238 unsigned long)) 1239 { 1240 struct drm_file *file_priv = filp->private_data; 1241 struct drm_device *dev = file_priv->minor->dev; 1242 unsigned int nr = DRM_IOCTL_NR(cmd); 1243 unsigned int flags; 1244 1245 /* 1246 * Do extra checking on driver private ioctls. 1247 */ 1248 1249 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1250 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1251 const struct drm_ioctl_desc *ioctl = 1252 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1253 1254 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1255 return ioctl_func(filp, cmd, arg); 1256 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1257 if (!drm_is_current_master(file_priv) && 1258 !capable(CAP_SYS_ADMIN)) 1259 return -EACCES; 1260 } 1261 1262 if (unlikely(ioctl->cmd != cmd)) 1263 goto out_io_encoding; 1264 1265 flags = ioctl->flags; 1266 } else if (!drm_ioctl_flags(nr, &flags)) 1267 return -EINVAL; 1268 1269 return ioctl_func(filp, cmd, arg); 1270 1271 out_io_encoding: 1272 DRM_ERROR("Invalid command format, ioctl %d\n", 1273 nr - DRM_COMMAND_BASE); 1274 1275 return -EINVAL; 1276 } 1277 1278 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1279 unsigned long arg) 1280 { 1281 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1282 } 1283 1284 #ifdef CONFIG_COMPAT 1285 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1286 unsigned long arg) 1287 { 1288 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1289 } 1290 #endif 1291 1292 static void vmw_master_set(struct drm_device *dev, 1293 struct drm_file *file_priv, 1294 bool from_open) 1295 { 1296 /* 1297 * Inform a new master that the layout may have changed while 1298 * it was gone. 1299 */ 1300 if (!from_open) 1301 drm_sysfs_hotplug_event(dev); 1302 } 1303 1304 static void vmw_master_drop(struct drm_device *dev, 1305 struct drm_file *file_priv) 1306 { 1307 } 1308 1309 bool vmwgfx_supported(struct vmw_private *vmw) 1310 { 1311 #if defined(CONFIG_X86) 1312 return hypervisor_is_type(X86_HYPER_VMWARE); 1313 #elif defined(CONFIG_ARM64) 1314 /* 1315 * On aarch64 only svga3 is supported 1316 */ 1317 return vmw->pci_id == VMWGFX_PCI_ID_SVGA3; 1318 #else 1319 drm_warn_once(&vmw->drm, 1320 "vmwgfx is running on an unknown architecture."); 1321 return false; 1322 #endif 1323 } 1324 1325 /** 1326 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1327 * 1328 * @dev_priv: Pointer to device private struct. 1329 * Needs the reservation sem to be held in non-exclusive mode. 1330 */ 1331 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1332 { 1333 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1334 1335 if (!ttm_resource_manager_used(man)) { 1336 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE); 1337 ttm_resource_manager_set_used(man, true); 1338 } 1339 } 1340 1341 /** 1342 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1343 * 1344 * @dev_priv: Pointer to device private struct. 1345 */ 1346 void vmw_svga_enable(struct vmw_private *dev_priv) 1347 { 1348 __vmw_svga_enable(dev_priv); 1349 } 1350 1351 /** 1352 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1353 * 1354 * @dev_priv: Pointer to device private struct. 1355 * Needs the reservation sem to be held in exclusive mode. 1356 * Will not empty VRAM. VRAM must be emptied by caller. 1357 */ 1358 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1359 { 1360 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1361 1362 if (ttm_resource_manager_used(man)) { 1363 ttm_resource_manager_set_used(man, false); 1364 vmw_write(dev_priv, SVGA_REG_ENABLE, 1365 SVGA_REG_ENABLE_HIDE | 1366 SVGA_REG_ENABLE_ENABLE); 1367 } 1368 } 1369 1370 /** 1371 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1372 * running. 1373 * 1374 * @dev_priv: Pointer to device private struct. 1375 * Will empty VRAM. 1376 */ 1377 void vmw_svga_disable(struct vmw_private *dev_priv) 1378 { 1379 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1380 /* 1381 * Disabling SVGA will turn off device modesetting capabilities, so 1382 * notify KMS about that so that it doesn't cache atomic state that 1383 * isn't valid anymore, for example crtcs turned on. 1384 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1385 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1386 * end up with lock order reversal. Thus, a master may actually perform 1387 * a new modeset just after we call vmw_kms_lost_device() and race with 1388 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1389 * to be inconsistent with the device, causing modesetting problems. 1390 * 1391 */ 1392 vmw_kms_lost_device(&dev_priv->drm); 1393 if (ttm_resource_manager_used(man)) { 1394 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1395 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1396 ttm_resource_manager_set_used(man, false); 1397 vmw_write(dev_priv, SVGA_REG_ENABLE, 1398 SVGA_REG_ENABLE_HIDE | 1399 SVGA_REG_ENABLE_ENABLE); 1400 } 1401 } 1402 1403 static void vmw_remove(struct pci_dev *pdev) 1404 { 1405 struct drm_device *dev = pci_get_drvdata(pdev); 1406 1407 drm_dev_unregister(dev); 1408 vmw_driver_unload(dev); 1409 } 1410 1411 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw) 1412 { 1413 struct drm_minor *minor = vmw->drm.primary; 1414 struct dentry *root = minor->debugfs_root; 1415 1416 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM), 1417 root, "system_ttm"); 1418 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM), 1419 root, "vram_ttm"); 1420 if (vmw->has_gmr) 1421 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR), 1422 root, "gmr_ttm"); 1423 if (vmw->has_mob) { 1424 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB), 1425 root, "mob_ttm"); 1426 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM), 1427 root, "system_mob_ttm"); 1428 } 1429 } 1430 1431 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1432 void *ptr) 1433 { 1434 struct vmw_private *dev_priv = 1435 container_of(nb, struct vmw_private, pm_nb); 1436 1437 switch (val) { 1438 case PM_HIBERNATION_PREPARE: 1439 /* 1440 * Take the reservation sem in write mode, which will make sure 1441 * there are no other processes holding a buffer object 1442 * reservation, meaning we should be able to evict all buffer 1443 * objects if needed. 1444 * Once user-space processes have been frozen, we can release 1445 * the lock again. 1446 */ 1447 dev_priv->suspend_locked = true; 1448 break; 1449 case PM_POST_HIBERNATION: 1450 case PM_POST_RESTORE: 1451 if (READ_ONCE(dev_priv->suspend_locked)) { 1452 dev_priv->suspend_locked = false; 1453 } 1454 break; 1455 default: 1456 break; 1457 } 1458 return 0; 1459 } 1460 1461 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1462 { 1463 struct drm_device *dev = pci_get_drvdata(pdev); 1464 struct vmw_private *dev_priv = vmw_priv(dev); 1465 1466 if (dev_priv->refuse_hibernation) 1467 return -EBUSY; 1468 1469 pci_save_state(pdev); 1470 pci_disable_device(pdev); 1471 pci_set_power_state(pdev, PCI_D3hot); 1472 return 0; 1473 } 1474 1475 static int vmw_pci_resume(struct pci_dev *pdev) 1476 { 1477 pci_set_power_state(pdev, PCI_D0); 1478 pci_restore_state(pdev); 1479 return pci_enable_device(pdev); 1480 } 1481 1482 static int vmw_pm_suspend(struct device *kdev) 1483 { 1484 struct pci_dev *pdev = to_pci_dev(kdev); 1485 struct pm_message dummy; 1486 1487 dummy.event = 0; 1488 1489 return vmw_pci_suspend(pdev, dummy); 1490 } 1491 1492 static int vmw_pm_resume(struct device *kdev) 1493 { 1494 struct pci_dev *pdev = to_pci_dev(kdev); 1495 1496 return vmw_pci_resume(pdev); 1497 } 1498 1499 static int vmw_pm_freeze(struct device *kdev) 1500 { 1501 struct pci_dev *pdev = to_pci_dev(kdev); 1502 struct drm_device *dev = pci_get_drvdata(pdev); 1503 struct vmw_private *dev_priv = vmw_priv(dev); 1504 struct ttm_operation_ctx ctx = { 1505 .interruptible = false, 1506 .no_wait_gpu = false 1507 }; 1508 int ret; 1509 1510 /* 1511 * No user-space processes should be running now. 1512 */ 1513 ret = vmw_kms_suspend(&dev_priv->drm); 1514 if (ret) { 1515 DRM_ERROR("Failed to freeze modesetting.\n"); 1516 return ret; 1517 } 1518 1519 vmw_execbuf_release_pinned_bo(dev_priv); 1520 vmw_resource_evict_all(dev_priv); 1521 vmw_release_device_early(dev_priv); 1522 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0); 1523 vmw_fifo_resource_dec(dev_priv); 1524 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1525 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1526 vmw_fifo_resource_inc(dev_priv); 1527 WARN_ON(vmw_request_device_late(dev_priv)); 1528 dev_priv->suspend_locked = false; 1529 if (dev_priv->suspend_state) 1530 vmw_kms_resume(dev); 1531 return -EBUSY; 1532 } 1533 1534 vmw_fence_fifo_down(dev_priv->fman); 1535 __vmw_svga_disable(dev_priv); 1536 1537 vmw_release_device_late(dev_priv); 1538 return 0; 1539 } 1540 1541 static int vmw_pm_restore(struct device *kdev) 1542 { 1543 struct pci_dev *pdev = to_pci_dev(kdev); 1544 struct drm_device *dev = pci_get_drvdata(pdev); 1545 struct vmw_private *dev_priv = vmw_priv(dev); 1546 int ret; 1547 1548 vmw_detect_version(dev_priv); 1549 1550 vmw_fifo_resource_inc(dev_priv); 1551 1552 ret = vmw_request_device(dev_priv); 1553 if (ret) 1554 return ret; 1555 1556 __vmw_svga_enable(dev_priv); 1557 1558 vmw_fence_fifo_up(dev_priv->fman); 1559 dev_priv->suspend_locked = false; 1560 if (dev_priv->suspend_state) 1561 vmw_kms_resume(&dev_priv->drm); 1562 1563 return 0; 1564 } 1565 1566 static const struct dev_pm_ops vmw_pm_ops = { 1567 .freeze = vmw_pm_freeze, 1568 .thaw = vmw_pm_restore, 1569 .restore = vmw_pm_restore, 1570 .suspend = vmw_pm_suspend, 1571 .resume = vmw_pm_resume, 1572 }; 1573 1574 static const struct file_operations vmwgfx_driver_fops = { 1575 .owner = THIS_MODULE, 1576 .open = drm_open, 1577 .release = drm_release, 1578 .unlocked_ioctl = vmw_unlocked_ioctl, 1579 .mmap = drm_gem_mmap, 1580 .poll = drm_poll, 1581 .read = drm_read, 1582 #if defined(CONFIG_COMPAT) 1583 .compat_ioctl = vmw_compat_ioctl, 1584 #endif 1585 .llseek = noop_llseek, 1586 .fop_flags = FOP_UNSIGNED_OFFSET, 1587 }; 1588 1589 static const struct drm_driver driver = { 1590 .driver_features = 1591 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM | DRIVER_CURSOR_HOTSPOT, 1592 .ioctls = vmw_ioctls, 1593 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1594 .master_set = vmw_master_set, 1595 .master_drop = vmw_master_drop, 1596 .open = vmw_driver_open, 1597 .postclose = vmw_postclose, 1598 1599 .dumb_create = vmw_dumb_create, 1600 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1601 1602 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1603 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1604 .gem_prime_import_sg_table = vmw_prime_import_sg_table, 1605 1606 DRM_FBDEV_TTM_DRIVER_OPS, 1607 1608 .fops = &vmwgfx_driver_fops, 1609 .name = VMWGFX_DRIVER_NAME, 1610 .desc = VMWGFX_DRIVER_DESC, 1611 .major = VMWGFX_DRIVER_MAJOR, 1612 .minor = VMWGFX_DRIVER_MINOR, 1613 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1614 }; 1615 1616 static struct pci_driver vmw_pci_driver = { 1617 .name = VMWGFX_DRIVER_NAME, 1618 .id_table = vmw_pci_id_list, 1619 .probe = vmw_probe, 1620 .remove = vmw_remove, 1621 .driver = { 1622 .pm = &vmw_pm_ops 1623 } 1624 }; 1625 1626 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1627 { 1628 struct vmw_private *vmw; 1629 int ret; 1630 1631 ret = aperture_remove_conflicting_pci_devices(pdev, driver.name); 1632 if (ret) 1633 goto out_error; 1634 1635 ret = pcim_enable_device(pdev); 1636 if (ret) 1637 goto out_error; 1638 1639 vmw = devm_drm_dev_alloc(&pdev->dev, &driver, 1640 struct vmw_private, drm); 1641 if (IS_ERR(vmw)) { 1642 ret = PTR_ERR(vmw); 1643 goto out_error; 1644 } 1645 1646 pci_set_drvdata(pdev, &vmw->drm); 1647 1648 ret = vmw_driver_load(vmw, ent->device); 1649 if (ret) 1650 goto out_error; 1651 1652 ret = drm_dev_register(&vmw->drm, 0); 1653 if (ret) 1654 goto out_unload; 1655 1656 vmw_fifo_resource_inc(vmw); 1657 vmw_svga_enable(vmw); 1658 drm_client_setup(&vmw->drm, NULL); 1659 1660 vmw_debugfs_gem_init(vmw); 1661 vmw_debugfs_resource_managers_init(vmw); 1662 1663 return 0; 1664 out_unload: 1665 vmw_driver_unload(&vmw->drm); 1666 out_error: 1667 return ret; 1668 } 1669 1670 drm_module_pci_driver(vmw_pci_driver); 1671 1672 MODULE_AUTHOR("VMware Inc. and others"); 1673 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1674 MODULE_LICENSE("GPL and additional rights"); 1675 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1676 __stringify(VMWGFX_DRIVER_MINOR) "." 1677 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1678 "0"); 1679